JPH0438530A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPH0438530A JPH0438530A JP14570790A JP14570790A JPH0438530A JP H0438530 A JPH0438530 A JP H0438530A JP 14570790 A JP14570790 A JP 14570790A JP 14570790 A JP14570790 A JP 14570790A JP H0438530 A JPH0438530 A JP H0438530A
- Authority
- JP
- Japan
- Prior art keywords
- task
- identifier
- level
- instruction
- execution level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 12
- 230000010365 information processing Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 241000479656 Bessa Species 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、複数のタスクが実行される情報処理装置に関
し、特にあるタスクから他のタスクへ移行する際の特定
処理を起動するかどうかを判定する実行レベル情報の処
理に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing device that executes a plurality of tasks, and in particular, a method for determining whether or not to start specific processing when transitioning from one task to another. This relates to processing of execution level information to be determined.
従来、この種の実行レベル情報のうちの特定処理を起こ
す実行レベルを説明する。ネクストレベル（ＮＬ）識別
子は、特定処理を起こす最も高い実行レベルを保持して
おり、次に起こすタスクがＮＬ識別子で示される実行レ
ベル以下の実行レベルであればいつでも特定処理が起き
ていた。Conventionally, of this type of execution level information, an execution level that causes a specific process will be explained. The next level (NL) identifier holds the highest execution level at which a specific process will occur, and the specific process will occur whenever the next task to occur is at an execution level lower than or equal to the execution level indicated by the NL identifier.
上述した従来のＮＬＪ別子の内容は、その内容で示され
る実行レベル以下の実行レベルのタスクへ移行する際は
、必ず特定処理に制御が移るので、特定処理を起こす必
要がない実行レベルへ移行する場合にも特定処理を実行
してしまう欠点がある。The content of the conventional NLJ bessa described above is such that when moving to a task with an execution level lower than the execution level indicated by the content, control is always transferred to a specific process, so the transition is made to an execution level where there is no need to cause a specific process. There is a drawback that specific processing is executed even when
本発明の目的は、このような欠点を除き、特定処理を起
こす必要のある実行レベルを示すようにした情報処理装
置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and provide an information processing apparatus that indicates an execution level at which a specific process needs to occur.
本発明の構成は、２つ以上のタスクが実行されるＣＰＵ
を含む情報処理装置において、前記タスクに与えられた
実行レベルを保持するタスクレベル識別子と、前記タス
ク終了命令の際、特定処理に制御を移すべき次のタスク
の実行レベルを保持するネクストレベル識別子と、前記
タスク終了命令の際に前記ネクストレベル識別子と次に
実行されるタスクの前記タスクレベル識別子を比較する
比較器と、この比較器が前記実行レベルの情報の一致を
判定した時に、特定処理へ制御を移す命令シーケンサと
を備えることを特徴とする。The configuration of the present invention is based on a CPU on which two or more tasks are executed.
an information processing device including: a task level identifier that holds the execution level given to the task; and a next level identifier that holds the execution level of the next task to which control should be transferred to a specific process when the task end command is issued. , a comparator that compares the next level identifier and the task level identifier of the task to be executed next at the time of the task end instruction; and when the comparator determines that the execution level information matches, the process proceeds to specific processing. and an instruction sequencer for transferring control.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例のブロック図である。図中
、１はタスクの命令コード及びデータを保持したメモリ
であり、命令コードはバス２を経由して命令デコーダ３
で解釈される。もし、タスクの終了命令であれば、次に
実行されるタスクの実行レベルを保持したタスクレベル
（ＴＬ）識別子４と、特定処理を起こす実行レベルを保
持した５のＮＬ識別子５とを比較器６で比較し、この比
較結果が一致していれば命令シーケンサ７に信号を出力
し、特定処理へ制御を移すようにしている。FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, 1 is a memory that holds the instruction code and data of the task, and the instruction code is sent to the instruction decoder 3 via bus 2.
It is interpreted as If it is a task termination instruction, a comparator 6 compares the task level (TL) identifier 4 that holds the execution level of the next task to be executed with the NL identifier 5 of 5 that holds the execution level that causes a specific process. If the comparison results match, a signal is output to the instruction sequencer 7 to transfer control to specific processing.
以上説明したように本発明は、−タスクから他のタスク
へ移行するタスク終了命令の際、特定処理を起こすべき
実行レベルを保持したＮＬ識別子と、次に実行するタス
クの実行レベルを保持したＴＬ識別子を比較し、これら
が一致した時のみ、特定処理を起すようにすることによ
り、特定の実行レベルに移行する時のみ特定処理を起こ
すことができ、ある実行レベルに移る時にのみ必要な特
定処理を起こすシステムにおいて効率的に処理ができる
という効果がある。As explained above, the present invention provides: - When a task end instruction is issued to transfer from a task to another task, an NL identifier that holds the execution level at which a specific process should be caused, and a TL identifier that holds the execution level of the task to be executed next; By comparing identifiers and causing specific processing only when they match, specific processing can be triggered only when moving to a specific execution level, and specific processing that is necessary only when moving to a certain execution level. This has the effect of allowing efficient processing in systems that cause problems.
第１図は、本発明の一実施例のブロック図である。
１・・・メモリ、２・・・バス、３・・・命令デコーダ
、４・・・ＴＬ識別子、５・・・ＮＬ識別子、６・・・
比較器、７・・・命令シーケンサ。FIG. 1 is a block diagram of one embodiment of the present invention. 1... Memory, 2... Bus, 3... Instruction decoder, 4... TL identifier, 5... NL identifier, 6...
Comparator, 7...Instruction sequencer.
Claims (1)
装置において、前記タスクに与えられた実行レベルを保
持するタスクレベル識別子と、前記タスク終了命令の際
、特定処理に制御を移すべき次のタスクの実行レベルを
保持するネクストレベル識別子と、前記タスク終了命令
の際に前記ネクストレベル識別子と次に実行されるタス
クの前記タスクレベル識別子を比較する比較器と、この
比較器が前記実行レベルの情報の一致を判定した時に、
特定処理へ制御を移す命令シーケンサとを備えることを
特徴とする情報処理装置。In an information processing device including a CPU that executes two or more tasks, a task level identifier that holds the execution level given to the task, and a next task to which control should be transferred to a specific process when the task end instruction is issued. a comparator that compares the next level identifier with the task level identifier of the next task to be executed at the time of the task termination instruction; When determining the match of
An information processing device comprising: an instruction sequencer that transfers control to specific processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14570790A JPH0438530A (en) | 1990-06-04 | 1990-06-04 | Information processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14570790A JPH0438530A (en) | 1990-06-04 | 1990-06-04 | Information processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438530A true JPH0438530A (en) | 1992-02-07 |
Family
ID=15391263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14570790A Pending JPH0438530A (en) | 1990-06-04 | 1990-06-04 | Information processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438530A (en) |
-
1990
- 1990-06-04 JP JP14570790A patent/JPH0438530A/en active Pending
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