JPS60201709A - Agc circuit - Google Patents

Agc circuit

Info

Publication number
JPS60201709A
JPS60201709A JP5880384A JP5880384A JPS60201709A JP S60201709 A JPS60201709 A JP S60201709A JP 5880384 A JP5880384 A JP 5880384A JP 5880384 A JP5880384 A JP 5880384A JP S60201709 A JPS60201709 A JP S60201709A
Authority
JP
Japan
Prior art keywords
circuit
output
signal
amplitude
amplifier circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5880384A
Other languages
Japanese (ja)
Inventor
Kyoji Sakamura
坂村 恭司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5880384A priority Critical patent/JPS60201709A/en
Publication of JPS60201709A publication Critical patent/JPS60201709A/en
Pending legal-status Critical Current

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To obtain an AGC circuit which ensures a stable output amplitude with no effect of a temperature change by extracting not only signals but a reference potential out of an output stage of a main amplifier circuit. CONSTITUTION:A detection circuit 2 detects the output peak value of an amplifier circuit 31 which amplifies an input signal with the gain varying by a control signal. While only the DC component is extracted at a division point of a load resistance 32 of the circuit 31 through an LPF5. Then the output of the circuit 2 is compared with that of the LPF5, and a comparator delivers a control signal in response to the obtained difference of outputs. In such a constitution, the output signal of an AGC circuit is deflected in an amplitude of alphaRL.ILO centering on an output terminal potential VLO obtained in a no-signal mode. Thus the amplitude of a signal can be prescribed by a product of the resistance 32 and a current flowing to the resistance 32. Therefore the variation can be reduced effectively to the variance of the power supply voltage, temperatures, etc.

Description

【発明の詳細な説明】 ′ 〔技術分野〕 本発明は、パルス符号伝−送路等に用いられる波形伝送
用AGC(自動利得制御)回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an AGC (automatic gain control) circuit for waveform transmission used in pulse code transmission lines and the like.

〔従来技術〕[Prior art]

従来から、同軸ケーブルおよび元ファイバーケーブル伝
送装置等に使用されるAGC回路Kbいては1本来、パ
ルス波彰伝送を基本とする技術に基くため、伝送路によ
る波形の劣化および減衰を補償し再生するための中継器
を伝送路に、ある一定区間ごとに設置している。したが
って、該中継器には、環境条件の変動、中継距離のばら
つきなどによって影響を受ける波形劣化量および減衰量
を補償するためのAGC回路が使われている。
Conventionally, the AGC circuit Kb used in coaxial cable and original fiber cable transmission equipment, etc. is originally based on technology based on pulsed wave transmission, so it compensates for waveform deterioration and attenuation due to the transmission line and reproduces it. Repeaters for this purpose are installed on the transmission line at certain intervals. Therefore, the repeater uses an AGC circuit to compensate for waveform deterioration and attenuation that are affected by changes in environmental conditions, variations in relay distance, and the like.

従来から該AGC回路は主として、主信号を増幅するた
めの主増幅回路と、該主増幅回路の出力信号の波高値を
検出するピーク検出回路と、主増幅回路の増幅率を制御
するための信号を発生する比較回路から構成される。
Conventionally, the AGC circuit mainly includes a main amplifier circuit for amplifying the main signal, a peak detection circuit for detecting the peak value of the output signal of the main amplifier circuit, and a signal for controlling the amplification factor of the main amplifier circuit. It consists of a comparison circuit that generates

第1図に従来のAGC回路を示す。】は主増幅回路であ
シ、制御信号により、その増幅率を可変とすることがで
きる。、2は主増幅回路の出力信号のピーク電位を検出
し7保持するためのピーク検出回路である。3は2つの
入力電位を比較する比較回路である。4は基準電位発生
回路であ91本例では電源電圧vs を抵抗分割rよシ
所定の基準宜圧が得られる様にしている。
FIG. 1 shows a conventional AGC circuit. ] is the main amplifier circuit, and its amplification factor can be made variable by a control signal. , 2 is a peak detection circuit for detecting and holding the peak potential of the output signal of the main amplifier circuit. 3 is a comparison circuit that compares two input potentials. Reference numeral 4 denotes a reference potential generation circuit 91. In this example, the power supply voltage vs is divided by a resistor r so that a predetermined reference voltage can be obtained.

このAGC回路は、入力信号を増幅して得られた出力信
号のピーク電位を検出し、その電位が基準電位発生回路
4から与えられた電位と同じになる様に比較回路3によ
シ主増幅回路lが制御されるところのいわゆる負帰還回
路となっている。
This AGC circuit detects the peak potential of the output signal obtained by amplifying the input signal, and uses the comparator circuit 3 to perform main amplification so that the peak potential becomes the same as the potential given from the reference potential generation circuit 4. It is a so-called negative feedback circuit in which circuit l is controlled.

第2図に主増幅回路の出力の波形および直流電位、設定
基準電位の関係を示す。同図(a)は、 AGC回路が
定常状態となっている場合であシ、波形のピーク電位が
設定基準電位10と同一になっている。同図(b)は波
形のピーク電位が基準電位10まで達していない過渡状
態を示している。この場合、比較回路3の出力信号は主
増幅回路の利得を増大させる様に、つまシ出力振幅を増
大させる様に動作する。同図(e)は、波形のピーク電
位が基準電位10を越している過渡状態を示している。
FIG. 2 shows the relationship between the waveform of the output of the main amplifier circuit, the DC potential, and the set reference potential. FIG. 5A shows a case where the AGC circuit is in a steady state, and the peak potential of the waveform is the same as the set reference potential 10. FIG. 4B shows a transient state in which the peak potential of the waveform has not reached the reference potential 10. In this case, the output signal of the comparator circuit 3 operates to increase the gain of the main amplifier circuit and to increase the output amplitude of the output. FIG. 4(e) shows a transient state in which the peak potential of the waveform exceeds the reference potential 10.

この場合、比較回路3の出力信号は主増幅回路の利得を
減少させる様に、つま夛出力振幅を減少させる様に動作
する。したがってこのAGC回路は、基準電位10に出
力波形ピーク電位が一致するまで、主増幅回路の利得が
変化する。いわゆるAGC動作を行なう。
In this case, the output signal of the comparator circuit 3 operates to reduce the gain of the main amplifier circuit and thus reduce the output amplitude. Therefore, in this AGC circuit, the gain of the main amplifier circuit changes until the output waveform peak potential matches the reference potential 10. A so-called AGC operation is performed.

この従来回路では、主増幅回路の直流出力電位を決デす
る回路と基準電位を発生する回路が独立しているため、
電源電圧変動環境温度変動に対して該2つの電位差が変
化し、その結果として出力信号の振幅が変化しやすいと
いう欠点があった。
In this conventional circuit, the circuit that determines the DC output potential of the main amplifier circuit and the circuit that generates the reference potential are independent.
There is a drawback that the difference between the two potentials changes in response to changes in power supply voltage and environmental temperature, and as a result, the amplitude of the output signal tends to change.

また、前記2つの回路の直流電位の温度等に対する変動
を等しく保つためには、それらを全く相似な回路構成と
じなければならない等1回路規模の増大をまねくという
欠点があった。
In addition, in order to maintain the same variation in the direct current potential of the two circuits with respect to temperature, etc., they must be combined into completely similar circuit configurations, resulting in an increase in the scale of one circuit.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、主増幅回路の出力段から信号のみなら
ず、基準電位をも取り出すことによって上記欠点を除去
し、安定な出力振幅を与えるAGC回路を提供すること
にある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an AGC circuit that eliminates the above drawbacks and provides stable output amplitude by extracting not only a signal but also a reference potential from the output stage of a main amplifier circuit.

〔発明の構成〕[Structure of the invention]

本発明のAGC回路は、入力信号を制御信号に応じて可
変する利得で増幅する増幅回路と、前記増幅回路の出力
のピーク値を検出する検出回路と。
The AGC circuit of the present invention includes an amplifier circuit that amplifies an input signal with a gain that is variable according to a control signal, and a detection circuit that detects the peak value of the output of the amplifier circuit.

前記増幅回路の負荷抵抗の按分点の信号からその直流分
を出力するF波器と、前記検出回路、F波器の出力を比
較し、その差分に応じて前記制御信号を出力する比較回
路とを有することを特徴とする。
an F-wave device that outputs a DC component from a signal at a distribution point of the load resistance of the amplifier circuit; a comparison circuit that compares the outputs of the detection circuit and the F-wave device and outputs the control signal according to the difference; It is characterized by having the following.

〔発明の実施例〕[Embodiments of the invention]

次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第3図を参照すると1本発明の第一の実施例は。Referring to FIG. 3, a first embodiment of the present invention is shown.

主増幅回路31の出力段をエミッタ接地形とした構成で
ある。該出力部は一端を電源r他端をコレクタに接続さ
れたコレクタ負荷抵抗32の所定の按分点を低域F波器
5を介して比較回路3の入力としている。その他の部分
は従来回路と同一構成である。
This configuration is such that the output stage of the main amplifier circuit 31 is emitter grounded. The output section has one end connected to a power source and the other end connected to a collector, and a predetermined distribution point of a collector load resistor 32 is input to the comparator circuit 3 via a low-frequency F wave generator 5. The other parts have the same configuration as the conventional circuit.

第4図を参照してその動作を説明する。無信号時(平衡
時)の出力電位V は電源電圧vs、コレO フタ負荷抵抗RL、および無信号時負荷電流ILOを用
いて表わすと。
Its operation will be explained with reference to FIG. The output potential V when there is no signal (at equilibrium) is expressed using the power supply voltage vs, the lid load resistance RL, and the load current ILO when there is no signal.

V=V−RL・工い LOB となる。一方、按分比αで負荷抵抗からタップを取シ出
すと、交流成分は低域ろ波器5で除去され。
V=V-RL・Work LOB. On the other hand, when the tap is taken out from the load resistor at the proportional division ratio α, the AC component is removed by the low-pass filter 5.

その直流電位は V、 −RL・”LO+αRL”1.0=V−(1−α
)・RLIIILO と表わせる。ところがこのAGC回路は出力部・号振幅
のピークが上記タップの電位に一致するまで。
Its DC potential is V, -RL・"LO+αRL"1.0=V-(1-α
)・RLIIILO. However, in this AGC circuit, until the peak of the signal amplitude at the output section matches the potential of the above-mentioned tap.

主増幅回路の利得を変化させる様に動作する。したがっ
て直流成分を持たない符号および正弦波等の信号は、無
信号時出力端子電位vLoを中心として上下対称に振れ
、その振幅(0−P値。
It operates to change the gain of the main amplifier circuit. Therefore, signals such as codes and sine waves that do not have a DC component swing vertically symmetrically around the no-signal output terminal potential vLo, and their amplitude (0-P value).

zero to pea、k value)はvO−P
 =’P ’LO”” αRL・ILOとなる。
zero to pea, k value) is vO-P
='P'LO'''' αRL・ILO.

この様に、信号の振幅を負荷抵抗とそれを流れる電流の
積で規定できるため電源電圧変動、温一度変勧などに対
する変化を低減するのに有効である。
In this way, the signal amplitude can be defined by the product of the load resistance and the current flowing through it, which is effective in reducing changes due to power supply voltage fluctuations, temperature changes, etc.

更に半導体集積回路等にてこのAGC回路を実現する場
合においても非常に有効である。なぜならば、半導体集
積回路においては、一般に、抵抗値が増大するとそれを
流れる電流が減少するため抵抗値と電流値の積はほぼ一
定に保たれるので、この実施例の様に出力振幅が負荷抵
抗と負荷電流の積に比例(比例定数αは一足)する回路
構成は非常に有効な手段となる。
Furthermore, it is also very effective when implementing this AGC circuit with a semiconductor integrated circuit or the like. This is because in semiconductor integrated circuits, as the resistance value increases, the current flowing through it generally decreases, so the product of the resistance value and the current value remains approximately constant. A circuit configuration that is proportional to the product of resistance and load current (the proportionality constant α is one foot) is a very effective means.

次に本発明の第二の実施例を第5図に示す。これは主増
幅回路41の出力部を差動型とした構成である。基本的
な動作原理は第一の実施例と同じであるので説明は略す
Next, a second embodiment of the present invention is shown in FIG. This is a configuration in which the output section of the main amplifier circuit 41 is of a differential type. The basic operating principle is the same as that of the first embodiment, so the explanation will be omitted.

上記の実施例ではNPN型バイポーラトランジスタと正
の電源電圧を用いて説明を行ったが、言うまでもなくP
NP型バイポーラトランジスタ。
Although the above embodiment was explained using an NPN type bipolar transistor and a positive power supply voltage, it goes without saying that P
NP type bipolar transistor.

フィールドエフェクトトランジスタ(いわゆるMO8型
トランジスタ)を用い、負の電源電圧でも動作原理は同
一である。さらに、ピーク検出回路で第4図の波形の上
側のピークを検出する代シに下側のピーク(ボトム)を
検出しても同様の効果を得ることができる。
A field effect transistor (so-called MO8 type transistor) is used, and the operating principle is the same even with a negative power supply voltage. Furthermore, the same effect can be obtained by using the peak detection circuit to detect the lower peak (bottom) of the waveform in FIG. 4 instead of detecting the upper peak.

〔発明の効果〕〔Effect of the invention〕

本発明によれば以上説明した様に、出力負荷抵抗の按分
点から直流基準電圧を得る構成とするととにより、安定
なAGC回路を実現できる。
According to the present invention, as explained above, a stable AGC circuit can be realized by obtaining the DC reference voltage from the distribution point of the output load resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のAGC回路を示すブロック図、第2図(
a) 、 (b) 、 (e)は第1図の動作を示す波
形図。 第3図は本発明の第一の実施例を示すブロック図、第4
図は第3図の動作を示す波形図、第5図は本発明の第二
の実施例を示すブロック図である。 1.31.41・・・・・・主増幅回路、2・・・・・
・ピーク検出回路、3・・・・・・比較回路、4・・・
・・・基準電位発生回路、5・・・・・・・低AF波器
。 Y1侶 v2@ /ρ /θ −一一一一了 $ 3 ’7 聚4−父 1戸
Figure 1 is a block diagram showing a conventional AGC circuit, and Figure 2 (
a), (b), and (e) are waveform diagrams showing the operation of FIG. 1; FIG. 3 is a block diagram showing the first embodiment of the present invention, and FIG.
This figure is a waveform diagram showing the operation of FIG. 3, and FIG. 5 is a block diagram showing a second embodiment of the present invention. 1.31.41... Main amplifier circuit, 2...
・Peak detection circuit, 3... Comparison circuit, 4...
...Reference potential generation circuit, 5...Low AF wave device. Y1 priest v2 @ /ρ /θ -1111ryo $ 3 '7 Ju 4 - Father 1 family

Claims (1)

【特許請求の範囲】[Claims] 入力信号を制御信号に応じて可変する利得で増幅する増
幅回路と、前記増幅回路の出力のピーク値を検出する検
出回路と、前記増幅回路の負荷抵号を出力する比較回路
とを有することを特徴とするAGC回路。
The present invention includes an amplifier circuit that amplifies an input signal with a gain that is variable according to a control signal, a detection circuit that detects a peak value of the output of the amplifier circuit, and a comparison circuit that outputs a load resistance of the amplifier circuit. Features AGC circuit.
JP5880384A 1984-03-27 1984-03-27 Agc circuit Pending JPS60201709A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5880384A JPS60201709A (en) 1984-03-27 1984-03-27 Agc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5880384A JPS60201709A (en) 1984-03-27 1984-03-27 Agc circuit

Publications (1)

Publication Number Publication Date
JPS60201709A true JPS60201709A (en) 1985-10-12

Family

ID=13094750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5880384A Pending JPS60201709A (en) 1984-03-27 1984-03-27 Agc circuit

Country Status (1)

Country Link
JP (1) JPS60201709A (en)

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