JPH11136268A - Field bus interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the field bus interface circuit in which oscillation is prevented without largely depressing a digital signal. SOLUTION: The field bus interface circuit is an improved one of a conventional circuit where a feeding and a digital signal are sent through a common transmission line to conduct communication. The circuit has a feedback resistor that produces a feedback voltage proportional to a current from a field bus, a switch circuit 51 that adjusts a current from the field bus, and a switch control circuit 55 that controls the switch circuit 51 corresponding to the DC component of the feedback voltage and outputs a digital signal directly to the switch circuit 51 independent of the feedback voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field bus interface circuit for performing communication by a field bus for transmitting both power supply and digital signals through a common transmission line, and relates to a field bus interface circuit which prevents oscillation and operates stably. It is related to the circuit.

[0002]

2. Description of the Related Art A field bus used for measurement and control of a plant supplies electric power to field devices together with digital transmission of signals. The field devices transmit signals over the field bus while receiving power supply from the field bus. Such an apparatus is disclosed in, for example, JP-A-5-41709 and JP-A-6-41709.
No. 3,334,670 and JP-A-8-293892.

FIG. 8 schematically shows such a system.
In the figure, a field bus (trunk cable) 1
Has terminators 2 at both ends to adjust the impedance on the bus. The power supply 3 supplies a voltage to the field bus 1. The upper communication device 4 is connected to the field bus 1 and communicates with the field device 5 via the field bus 1. The field device 5 is a field bus 1
A signal is input to the field bus 1 and converted into electric power. For example, signal processing such as pressure and differential pressure is performed, and a signal is output to the field bus 1. The junk box 6 is provided in the field bus 1, and is branched from the field bus 1 by a spar (cable) 7 and connected to the field device 5.

Next, a field bus interface circuit used in the field device 5 will be described with reference to FIG. In the figure, a switch circuit 51 inputs a current from a terminal T1 connected to the + side of the field bus. Resistance R
f has one end connected to a terminal T2 connected to the negative side of the field bus, and converts a current input to the circuit into a voltage.
The switch control circuit 52 receives the voltage detected by the resistor Rf and controls the switch circuit 51 to adjust the amount of current. The shunt regulator 53 receives a current supply from the switch circuit 51 with a Zener diode, for example, and generates a constant voltage. The capacitor C1 is charged by receiving the current supply from the switch circuit 51, and becomes a current supply source of the circuit. That is, the shunt regulator 53 and the capacitor C1 serve as a power supply for the circuit.

This will be described in more detail. Switch circuit 51
Comprises a current mirror circuit CMC, a current source I, a transistor Q1, and a resistor R1.

The current mirror circuit CMC includes a resistor R2
R3 and transistors Q2 and Q3. The resistor R2 has one end connected to the terminal T1 and the other end connected to the emitter of the transistor Q2. The resistor R3 has one end connected to the terminal T1, the other end connected to the current source I, and the other end connected to the emitter of the transistor Q3. Transistor Q2 has a base connected to the collector, and a collector connected to the collector of transistor Q1. Transistor Q3
Has a base connected to the base of the transistor Q2 and a collector connected to the other end of the current source I.

The other end of the current source I is connected to the other end of the resistor Rf via the shunt regulator 53 or the capacitor C1. The current source I is provided for a current for starting the circuit, and may be a resistor instead of the current source I.

The output of the switch control circuit 52 is input to the base of the transistor Q1, and the emitter is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the other end of the resistor Rf.

The switch control circuit 52 includes an operational amplifier U and resistors R4 to R7. The operational amplifier U inputs the output to the base of the transistor Q1. Then, a voltage obtained by dividing the bias voltage Vr by the resistors R4 and R5 is input to the non-inverting input terminal (+). The difference between the total voltage of the bias voltage Vr, the reference voltage Vs, and the digital signal Vd, and the feedback voltage Vf of the resistor Rf are applied to the inverting input terminal (-).
The divided voltage is input. Here, the reference voltage Vs
Is specified to input a current for operating the circuit. Further, the bias voltage Vr and the reference voltage Vs are created by electric power supplied from the field bus. The digital signal Vd is generated by, for example, a circuit for measuring pressure, differential pressure, and the like.

[0010] Such an apparatus will be described below. FIG.
10 is a waveform chart for explaining the operation of the device of FIG. here,
The resistance values are R4 = R6, R5 = R7. Current flows from the field bus 1 by the current source I and the capacitor C
1 is charged, made to have a constant voltage by the shunt regulator 53, and supplied to each circuit (including a measurement circuit not shown). Thereby, the bias voltage Vr and the reference voltage V
s is created. Then, assuming that the digital signal Vd is not output, the operational amplifier U has a non-inverting input terminal (+).
Is output to the base of the transistor Q1 so that the voltage at the inverting input terminal (-) becomes equal to that at the inverting input terminal (-). As a result, the transistor Q1 is connected to the collector
A current flows between the emitters, and a current flows through the current mirror circuit CMC. As a result, the reference current I
s (= (1 / Rf) .Vs. (R5 / R4)) flows.

Then, for example, with the pressure, the differential pressure, etc.,
A digital signal Vd is generated.
7 and the non-inverting input terminal (+) of the operational amplifier U.
Is input to As a result, the operational amplifier U outputs an output corresponding to the digital signal Vd to the base of the transistor Q1, while comparing the output with the feedback voltage Vf. Then, the current of the current mirror circuit CMC changes, and finally, the current flowing through the resistor Rf is changed from the reference current Is to the reference current Is +
Digital current Id (= (1 / Rf) · Vd · (R5 / R
4)).

[0012]

In such a circuit, for example, a noise filter 54 shown in FIG. 11 is provided between the circuit and the field bus 1 in order to improve noise immunity.
The noise filter 54 includes coils L1 and L2 and capacitors Ca and Cb. The noise filter 54
Connected to terminals T1 and T2, and also connected to terminals T3 and T4 connected to Fieldbus 1. In the case of such a configuration, the output may become unstable, causing oscillation. This is because, unlike the conventional 4-20 mA transmission, the transmission speed is increased by converting the transmission to a digital signal. That is, an inductance is added to the load of the current control loop of the field bus interface circuit, a resonance point is formed with the capacitance component of the field bus interface circuit and the capacitance of the noise filter, and the loop phase of the current control system is rotated.

[0013] Even if the noise filter 54 is not provided, if the spar 7 is lengthened, oscillation may similarly occur due to impedance mismatch of the cable.

Even if the spar 7 has an appropriate length, the inductance of an arrester, an ammeter or the like provided between the field bus 1 and the field device 5 causes the spar 7 to have an appropriate length.
Similarly, oscillation may be caused.

As a method for preventing the above,
It is conceivable to insert a capacitor between the inverting input terminal (-) of the operational amplifier U and the output to perform phase compensation. However, the high-frequency characteristics of the operational amplifier U are deteriorated, and the digital signal placed on the field bus 1 is dull. In order to satisfy a field bus standard of a digital signal having a slew rate of 0.2 V / μsec or less and a level of 10% to 90% within 8 sec, the digital signal cannot be largely blunted.

SUMMARY OF THE INVENTION An object of the present invention is to realize a field bus interface circuit which can prevent oscillation without greatly slowing down a digital signal.

[0017]

SUMMARY OF THE INVENTION The present invention relates to a field bus interface circuit for performing communication via a field bus for transmitting both power supply and digital signals through a common transmission line, and a feedback voltage proportional to a current from the field bus. And a switch circuit for adjusting the current from the field bus, and controlling the switch circuit in accordance with the DC component of the feedback voltage.
And a switch control circuit for directly outputting the digital signal to the switch circuit without depending on the feedback voltage.

According to the present invention, the switch control circuit controls the switch circuit according to the DC component of the feedback voltage. Then, the switch control circuit directly outputs a digital signal regardless of the feedback voltage to control the switch circuit.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of the present invention. Hereinafter, the same components as those in FIG. The switch control circuit 55 receives the voltage detected by the resistor Rf, controls the switch circuit 51, and adjusts the amount of current.

The switch control circuit 55 includes an operational amplifier U, resistors R4 to R7, and capacitors C2 and C3. The operational amplifier U inputs the output to the base of the transistor Q1. The bias voltage Vr is applied to the non-inverting input terminal (+).
Is divided by resistors R4 and R5. At the inverting input terminal (-), the difference between the total voltage of the bias voltage Vr and the reference voltage Vs and the feedback voltage Vf of the resistor Rf is equal to the resistance R6.
The voltage divided by R7 is input. The capacitor C2 is provided between the inverting input terminal (-) and the output of the operational amplifier U. When the digital signal Vd, which is a high-frequency signal, is input to the non-inverting input terminal (+) of the operational amplifier U, the operational amplifier U and the capacitor C2 operate as a buffer. That is, the impedance of the capacitor C2 is made sufficiently smaller than the resistances of the resistors R4 and R5. The capacitor C3 is provided in parallel with the resistor R6, passes the digital signal Vd as a high-frequency signal, and directly inputs the digital signal Vd to the non-inverting input terminal (+) of the operational amplifier U. That is, the impedance of the capacitor C3 is changed by the resistors R6 and R7.
Small enough.

The operation of such a device will be described below.
Here, the resistance values are R4 = R6, R5 = R7. A current flows in from the field bus by the current source I, charges the capacitor C1, and makes the voltage constant by the shunt regulator 53 and supplies it to each circuit. As a result, a bias voltage Vr and a reference voltage Vs are generated. If the digital signal Vd is not output, the transistor Q1 is turned on by the operational amplifier U such that the voltages at the non-inverting input terminal (+) and the inverting input terminal (-) become the same.
Output to the base. Thus, with the output of the operational amplifier U, the transistor Q1 causes a current to flow between the collector and the emitter, and a current flows to the current mirror circuit CMC. As a result, the reference current Is (= (1 /
Rf) .Vs. (R5 / R4)) flows.

Then, for example, with pressure, differential pressure, etc.,
A digital signal Vd is generated, which passes through the capacitor C3 and is input to the non-inverting input terminal (+) of the operational amplifier U. A buffer is constituted by the operational amplifier U and the capacitor C2, and the digital signal Vd input to the non-inverting input terminal (+) is output to the base of the transistor Q1. Then, the current of the current mirror circuit CMC changes to change from the reference current Is to the reference current Is + the digital current Id (≒ (1 / R1) · Vd · (R2 / R3)). Here, it is assumed that the reciprocal of the transconductance of transistor Q1 is sufficiently smaller than R1. Also, R2 /
R3 is a current ratio of the current mirror circuit CMC.

As described above, the DC power supply control is accurately performed by the current control feedback loop, and the transmission of the digital signal to the field bus is not performed by the current control feedback loop, but directly by the digital signal feedback loop. Outputs a signal proportional to. By using the voltage follower for the operational amplifier U in an AC manner, the AC gain of the feedback loop is remarkably reduced and the band becomes narrower, so that oscillation due to instability of the current control feedback loop can be prevented. In other words, transmission is possible without impairing the waveform of the digital signal at all, and
Since it can withstand inductive loads (noise filters, long spurs, arresters containing inductance, ammeters, etc.), a stable fieldbus interface circuit can be realized.

FIG. 2 shows a second embodiment in which the current mirror circuit CMC is changed. In the figure, FIG.
The current mirror circuit CMC shown in FIG.
Is added. The transistor Q4 has a base connected to the collector of the transistor Q2, an emitter connected to the base of the transistor Q2, and a collector grounded.

The operation of such a device will be described below.
The collector current Ic1 of the transistor Q1 is shown as follows. Ic1 = Ic2 + (Ic2 / β2 + Ic3 / β3) / β
4 Ic2: Collector current of transistor Q2 Ic3: Collector current of transistor Q3 β2: Current amplification factor of transistor Q2 β3: Current amplification factor of transistor Q3 β4: Current amplification factor of transistor Q4

Here, since the current amplification factor ≫1, Ic
If 2 ≒ Ie2 and Ic2≫Ic2 / β2, the following is obtained. Ic1 = Ie2 + (Ic3 / β3) / β4

When the voltage drop of the resistors R2 and R3 is sufficiently larger than the thermal voltage of the transistor, the current ratio of the current mirror is determined substantially only by the resistance ratio. If Ie3 ≒ Ic3, the following is obtained. Ie2 × R2 = Ie3 × R3 Ie2 = (R3 / R2) × Ie3 ≒ (R3 / R2) × I
c3

Therefore, the following is obtained. Ic1 = (R3 / R2) × Ic3 + (Ic3 / β3) /
β4 The collector current Ic3 of the transistor Q3 is as follows. Ic3 = Ic1 × (R2 / R3) × (1 / (1+ (R3
/ R2) / β3 / β4)

Similarly, the current mirror circuit CMC of the apparatus shown in FIG. 1 is obtained as follows. Ic3 = Ic1 × (R2 / R3) × (1 / (1+ (R3
/ R2) / β3)

Usually, in order to suppress unnecessary current consumption inside the circuit, the mirror current ratio (R) is set so that Ic3≫Ic2.
2 / R3) is set to a high value (for example, 50). Therefore, the error term (R3 / R2) in the equation of the collector current Ic3 is obtained.
The effect of / β3 cannot be ignored. Irrespective of the constant collector current Ic1, the collector-emitter voltage of the transistor Q3 fluctuates due to fluctuations in the voltage between the terminals T1 and T2, and Ic3 (≒ Is) fluctuates due to fluctuations in β3. Impedance (= ΔVt / ΔIs,
Vt: the voltage between the terminals T1 and T2) fluctuates and drops.

However, in the field bus, the input impedance viewed from the field bus is 3 kΩ or more (frequency: between 0.25 fr and 1.25 fr, fr = 31.
25 kHz). The terminal voltage of the device is specified to be 9 to 32V. For this reason, it is necessary to prevent the input impedance from decreasing.

Therefore, the current mirror circuit C shown in FIG.
Since the MC reduces the error portion of the collector current Ic3 to 1 / β4, it can be almost ignored, preventing the input impedance from lowering and preventing the input impedance from fluctuating.

According to actual measurements by the inventors, in the actual measurement using the apparatus of FIG. 1, the input impedance was 2 kΩ when the measurement frequency was 39 kHz and the voltage between terminals was 9 V, but in the apparatus of FIG. 2, the input impedance was 6 kΩ. It became.

Thus, the capacitance of the noise filter provided between the field bus interface circuit and the field bus can be increased, so that the noise immunity is improved. Further, the variation in the input impedance characteristic is small with respect to the temperature variation, the terminal voltage variation, and the transistor variation, so that the margin design can be easily performed.

Further, the current mirror circuit CMC is not limited to the device shown in FIGS. 1 and 2, but may be the third embodiment shown in FIG. 3 or the fourth embodiment shown in FIG.

In FIG. 3, the current mirror circuit CMC shown in FIG. 1 is configured without the resistors R2 and R3. That is, the emitters of the transistors Q2 and Q3 are directly connected to the terminal T1. In this case, the transistors Q2 and Q3 have different types of transistors to change the current ratio.

In FIG. 4, the current mirror circuit CMC shown in FIG. 1 is configured without the transistor Q2 and the resistor R3. That is, the resistor R2 has one end connected to the terminal T1 and the other end connected to the collector of the transistor Q1. Then, the transistor Q3 has an emitter connected to the terminal T1.

FIG. 5 shows an embodiment in which the switch circuit 51 is modified. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The switch circuit 51 includes an FET Q5
And resistors R8 and R9 and diodes D1 and D2.

The drain of the FET Q5 is connected to the terminal T1. FET Q5 is an n-channel junction FET
At the time of startup, the voltage across the resistor R9 is zero, so that the transistor Q5 is turned on, and a startup current for the circuit flows. The resistor R8 has one end connected to the source of the FET Q5 and the other end connected to the shunt regulator 53. The resistor R9 has one end connected to the other end of the resistor R8 and the other end connected to the FET Q
5 gate. Diodes D1 and D2 are connected in series. Then, the anode of the diode D1 is connected to F
Connected to the gate of ETQ5, the output of operational amplifier U is input to the cathode of diode D2. Diode D1,
D2 shifts the output voltage of the operational amplifier U to the positive side.

In such a device, if the reciprocal of the transconductance of the FET Q5 is sufficiently smaller than R8, the digital current becomes Id ≒ (1 / R8) × Vd.

FIG. 6 shows an embodiment in which the switch circuit 51 is modified. The switch circuit 51 includes a transistor Q6, an FET Q7, resistors R11 and R12, and diodes D3, D4 and D5.

The transistor Q6 has a collector connected to the terminal T1.
Connect to The FET Q7 has a drain connected to the terminal T1. The resistor R11 has one end connected to the emitter of the transistor Q6 and the other end connected to the shunt regulator 53. The resistor R12 has one end connected to the source of the FET Q7, the other end connected to the gate of the FET Q7, and to the base of the transistor Q6. The FET Q7 is an n-channel junction FET and supplies a current bias for the diodes D3 to D5 and a base current to the transistor Q6. Therefore, a starting current flows. Diode D3 ~
D5 is connected in series, the anode of the diode D3 is connected to the base of the transistor Q6, and the output of the switch control circuit 52, that is, the output of the operational amplifier U, is connected to the cathode of the diode D5. Diodes D3 to D5
Shifts the output voltage of the operational amplifier U to the positive side.

In such a device, if the reciprocal of the transconductance of the transistor Q6 is sufficiently smaller than R11, the digital current becomes Id ≒ (1 / R11) × Vd.
As described above, various types of switch circuits 51 are conceivable.

FIG. 7 shows an embodiment in which the switch control circuit 55 is modified. The switch control circuit 55 includes an operational amplifier U, resistors R4 to R7, R13, and a capacitor C
4, C5.

The output of the operational amplifier U is input to the base of the transistor Q1 via the resistor R13. Then, a voltage obtained by dividing the bias voltage Vr by the resistors R4 and R5 is input to the non-inverting input terminal (+). The sum of the bias voltage Vr and the reference voltage Vs, the resistance Rf
Is input by dividing the difference from the feedback voltage Vf by resistors R6 and R7. The capacitor C4 is provided between the inverting input terminal (-) and the output terminal of the operational amplifier U, reduces the sensitivity of the feedback voltage Vf from the resistor Rf to the AC component, and the output of the operational amplifier U is affected by the digital signal Vd. To prevent changes.

The capacitor C5 inputs the digital signal Vd from one end, and outputs the digital signal Vd to the base of the transistor Q1 from the other end. Here, the capacitor C5
Serves as a DC cutoff.

The operation of such an apparatus will be described below.
A current flows in from the field bus by the current source I, charges the capacitor C1, and makes the voltage constant by the shunt regulator 53 and supplies it to each circuit. As a result, a bias voltage Vr and a reference voltage Vs are generated. Then, the transistor Q1 is turned on by the operational amplifier U such that the voltage of the non-inverting terminal (+) becomes equal to the voltage of the inverting terminal (-).
Is output via a resistor R13. This allows
With the output of the operational amplifier U, a current flows through the transistor Q <b> 1 between the collector and the emitter, and a current flows through the current mirror 51. As a result, the reference current Is
(= (1 / Rf) .Vs. (R5 / R4)) flows.
At this time, the resistor R13 prevents the digital signal Vd and the output of the operational amplifier U from being connected with low impedance.

Then, for example, with pressure, differential pressure, etc.,
A digital signal Vd is generated, and the digital signal passes through the capacitor C5 and is directly input to the switch circuit 51, that is, the base of the transistor Q1. In response to the digital signal Vd, the switch circuit 51 inputs the digital current Id (× (1 / R1) × Vd × (R2 / R3)) from the field bus.

As described above, the power supply current control in the DC region is accurately performed by the feedback loop of the current control in which the AC gain is suppressed, and the digital signal which is a high frequency signal is directly subjected to the current control without performing the feedback of the current control. Therefore, oscillation due to an inductance load can be prevented.

The switch control circuit 52 uses the reference voltage Vs.
The same operation can be performed by unbalancing the resistor 4 and the resistor R6 or the resistor R5 and the resistor R7.

Then, the reference voltage Vs and the digital signal Vd
Are connected in series, but the digital signal V
d may be input to the non-inverting input terminal (+) of the operational amplifier U via a capacitor. That is, the reference voltage Vs is configured to be directly input to the resistor R6.

As described above, various types of switch control circuits 55 are conceivable. In short, the switch control circuit 55 controls the direct current Is used for the power supply by the current control loop, and transmits the digital signal Vd by directly changing the switch circuit 51.

The present invention is not limited to this, and the resistor Rf may be provided on the terminal T1 side. Accordingly, the internal configurations of the switch circuit 51 and the switch control circuit 55 also change.

[0054]

According to the present invention, the following effects can be obtained. According to claims 1 to 4, direct current supply control is accurately performed in a feedback loop of current control, and transmission of a digital signal to a field bus is not performed in a feedback loop of current control but directly. Outputs a signal proportional to the digital signal. Therefore, it is possible to prevent oscillation due to the current control feedback loop. In other words, transmission is possible without impairing the waveform of the digital signal at all, and since it can withstand inductive loads (noise filters, long spurs, arresters including inductance, ammeters, etc.), a stable fieldbus interface circuit is realized. be able to.

According to the fifth aspect, the capacitance of the capacitor of the noise filter provided between the field bus interface circuit and the field bus can be increased, so that the noise immunity is improved. Further, the variation in the input impedance characteristic is small with respect to the temperature variation, the terminal voltage variation, and the transistor variation, so that the margin design can be easily performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a third embodiment of the present invention.

FIG. 4 is a configuration diagram showing a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram showing a fifth embodiment of the present invention.

FIG. 6 is a configuration diagram showing a sixth embodiment of the present invention.

FIG. 7 is a configuration diagram showing a seventh embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a plant system.

FIG. 9 is a diagram showing a configuration of a conventional fieldbus interface circuit.

FIG. 10 is a diagram for explaining the operation of the device of FIG. 9;

FIG. 11 is a configuration diagram illustrating an example of a noise filter.

[Explanation of symbols]

 51 switch circuit 55 switch control circuit CMC current mirror circuit C2 capacitor C3 capacitor C4 capacitor C5 capacitor Q1 transistor Rf resistance U operational amplifier

Claims (5)

[Claims] 1. A field bus interface circuit for performing communication by a field bus for transmitting both power supply and digital signals through a common transmission line, comprising: a feedback resistor for generating a feedback voltage proportional to a current from the field bus; A switch circuit for adjusting a current from the field bus; and a switch control for controlling the switch circuit in accordance with a DC component of the feedback voltage and for directly outputting a digital signal to the switch circuit without depending on the feedback voltage. A fieldbus interface circuit comprising: 2. A switch control circuit for controlling a switch circuit by outputting a voltage corresponding to a feedback voltage, a first capacitor being provided between an inverting input terminal and an output terminal, and a digital signal transmitted to a field bus. 2. The fieldbus interface circuit according to claim 1, further comprising an operational amplifier for inputting a signal to a non-inverting input terminal via a second capacitor and directly outputting a digital signal to a switch circuit for control. 3. A switch control circuit comprising: an operational amplifier that outputs a voltage corresponding to a feedback voltage to a switch circuit; and an operational amplifier provided between a non-inverting terminal and an output terminal of the operational amplifier. 2. The fieldbus interface circuit according to claim 1, further comprising: a second capacitor that inputs a digital signal and outputs the digital signal to the switch circuit. 4. A switch circuit comprising at least a transistor whose base current is controlled by an output of a switch control circuit, and a current mirror circuit which controls a current from a field bus by a collector current of the transistor. The fieldbus interface circuit according to claim 1, wherein: 5. The field bus interface circuit according to claim 4, wherein said current mirror circuit is of a base current compensation type.