JPS6048609A - Automatic level adjusting circuit - Google Patents

Abstract

PURPOSE:To reduce the dispersion in level setting by providing an amplifier, a comparator, a clamp circuit, a buffer circuit and an attenuation circuit so as to set easily a maximum value of a control current to the attenuation circuit thereby preventing the fluctuation of a recovery time of a time constant circuit. CONSTITUTION:An input signal given to an input terminal 2 is given to the amplifier 46 via the attenuation circuit 24, its amplified output is extracted from an output terminal 12 and also compared with a reference level by the comparator 28. A potential output level of the comparator 28 is set by the clamp circuit 70 to a prescribed voltage or below and its output becomes a base input of a transistor (TR)74 as the buffer circuit. The operating current in response to the input flows to the TR74 and a capacitor 84 of the time constant circuit 82 is charged by a prescribed time constant. That is, an attack time and the recovery time to drive a TR42 are set by the circuit 82. The operating current flowing to the TR74 becomes a base input of the TR42 via the circuit 82 and a control current is given to the attenuation circuit 24 by the TR42.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic level adjustment circuit, and more particularly to an automatic level adjustment circuit that adjusts the amplitude level of an alternating current signal such as an audio signal according to an input signal level.

FIG. 1 shows a conventional automatic level adjustment circuit. The signal given to the input terminal 2 is transmitted through a resistor 4 and a capacitor 6,
It is taken out from the output terminal 12 via the amplifier 8 and the capacitor lO, and the diode 14
After being detected by the resistor 16, the signal is smoothed by the capacitor 8, converted into a DC level signal corresponding to the input signal level, and applied to the base of the transistor 20. The transistor 20 constitutes a voltage buffer circuit, and is connected between the power supply line and the base of the transistor 22 with its collector facing the power supply line side. The transistor 22 is connected as a variable impedance element between the connection point between the resistor 4 and the capacitor 6 and the reference potential point, with its emitter facing the reference potential point.

According to such a configuration, the base current of the transistor 22 is controlled in accordance with the signal level applied from the input terminal 2, the input impedance is adjusted, and the output terminal 12
can take out a level-adjusted output signal.

However, when such a circuit is constructed using a semiconductor integrated circuit, capacitors 6.
10.18, the number of external connection terminals (bins) is large, and it is required to reduce the number of terminals (bins), improve temperature characteristics due to the temperature coefficient of the diode, and enable arbitrary level setting.

Therefore, the automatic level adjustment circuit shown in Fig. 2 was proposed.
It satisfies the above requirements. In this circuit, amplifier 8
The capacitor 6 on the input side of the amplifier 8 is removed, an attenuation circuit 24 is installed which makes it possible to adjust the amount of attenuation, and a constant bias is applied from the voltage source 26, and the capacitor 10 on the output side of the amplifier 8 is removed. An output terminal 12 is formed.

The output of the amplifier 8 is applied to the non-inverting input terminal (+) of the comparator 28, and a level setting terminal 30 formed at the inverting input terminal (-) is connected to a variable terminal connected between the power supply terminal 32 and the reference potential point. A constant comparison level is set from resistor 34. A capacitor 40 constituting a time constant setting circuit is connected between a terminal 38 formed on the output side of this comparator 28 via a resistor 36 and a reference potential point, and a DC level obtained via this capacitor 40 is connected. The signal is transistor 4
given on the basis of 2. The transistor 42 is used to adjust the amount of attenuation of the attenuation circuit 24 according to the base input, and its collector is connected to the adjustment input section of the attenuation circuit 24, and a resistor is connected between its emitter and the reference potential point. 4
4 are connected.

However, this circuit has the disadvantage that when a fixed resistor is used for level setting, the set level varies for small level settings due to variations in the values thereof. A capacitor 4 constituting a time constant setting circuit is also connected to the output side of the comparator 28.
0 is directly connected, automatic level adjustment circuit (ALC circuit)
When a huge input that exceeds the control capability range is applied,
There are disadvantages such as the charging voltage increases to near the power supply voltage, resulting in a long recovery time, and furthermore, it is difficult to set the maximum value of the control current to the attenuation circuit 24.

An object of the present invention is to provide an automatic level adjustment circuit that facilitates the setting of the maximum value of the control current to the attenuation circuit, prevents fluctuations in the time constant circuit recovery time, and reduces variations in level settings. do.

This invention includes a DC amplifier installed in a signal system, a comparator that compares the output of the DC amplifier with a reference level,
A clamp circuit that sets the output of this comparator to a potential below a certain value, a buffer circuit to which the output of the comparator obtained through this clamp circuit is given, and a signal system installed in the front stage of the DC amplifier. The present invention is characterized in that it further includes an attenuation circuit that adjusts the input signal level using the output of the buffer circuit.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

FIG. 3 shows an embodiment of the automatic level adjustment circuit of the present invention. In the figure, a signal to be level-adjusted applied to input terminal 2 is applied to amplifier 46 via attenuation circuit 24, and its amplified output is taken out from output terminal 12.

The input of the amplifier 46 is supplied from the voltage source 26 via a resistor 48, and a feedback circuit is formed between the input and output terminals of the amplifier 46 by a resistor 50, 52 and a capacitor 56 connected to an external terminal 54. has been done.

The output of the amplifier 46 is applied to the inverting input terminal (-) of the current output type comparator 28, and the output is applied to the non-inverting input terminal (-) of the comparator 28 of the current output type.
A voltage source 26 is connected to the level setting terminal 30 formed at +).
A voltage obtained by dividing a reference voltage generated between a terminal 58 formed on the positive electrode side and a reference potential point using resistors 60 and 62 is applied.

A clamp circuit 70 consisting of diodes 64, 66, 68 is installed between the output side of the comparator 28 and a reference potential point, and the output of the comparator 28 is applied to the base of a transistor 74 serving as a buffer circuit. A drive voltage V is applied to the collector of this buffer transistor 74 from a power supply terminal 76.
cc is applied, and a time constant setting terminal 80 is formed at the emitter via a resistor 78. The time constant circuit 82 includes a resistor 78, a resistor 84 connected to a time constant setting terminal 80, and a capacitor 86.

The operation will be explained based on the above configuration. The input signal applied to input terminal 2 is applied to amplifier 46 via attenuation circuit 24, and its amplified output is taken out from output terminal I2 and compared with a reference level between comparators. The amplification gain of the amplifier 46 is set constant by resistors 50, 52 and capacitor 56. Also, unlike the conventional circuit, the reference level applied to the level setting terminal 30 formed at the non-inverting input terminal (+) of the comparator 28 is obtained by dividing the reference voltage generated by the voltage source 26 with a resistor 60.62. ing.

The output level of the comparator 28 is set at a potential below a certain voltage by a clamp circuit 70, and its output becomes the base input of a transistor 74. An operating current corresponding to this input flows through the transistor 74, and the capacitor 84 of the time constant circuit 82 is charged with a fixed time constant. That is, the active time and recovery time for driving the transistor 42 are set by the time constant circuit 82. The operating current flowing through transistor 74 becomes the base input of transistor 42 via time constant circuit 82, and as a result, transistor 42 provides a control current to attenuation circuit 24.

According to such a circuit, the input signal level and the resistor 60.
Based on the comparison with the reference level set at 62, the attenuation amount of the attenuation circuit 24 is controlled, and the signal level can be controlled. In particular, if the capacitor 84 of the time constant circuit 82 is charged to the maximum, the maximum value of the control current rs flowing through the transistor 42 is the value obtained by dividing the transistor H-emitter voltage VF by the resistance value R of the resistor 86. (VF/
R), which sets the maximum control current of the attenuation circuit 24 and determines the maximum amount of attenuation.

In addition, since the maximum charging voltage of the capacitor 84 is IVF, it is possible to prevent the recovery time from becoming extremely long due to unnecessary charging of the capacitor 84 even in response to strong input signals.
Furthermore, it is possible to prevent the recovery time from changing greatly due to differences in the power supply voltage Vcc. Further, since the comparison reference voltage set in the comparator 28 is obtained by dividing the voltage output from the voltage source 26, it is not affected by ripples included in the power supply voltage Vcc.

Furthermore, in this circuit, by controlling the operating current of the comparator 28, the operation and non-operation of the ALC circuit can be controlled.

FIG. 4 shows a specific example of the circuit configuration of the automatic level adjustment circuit of the present invention, and the same parts as those of the automatic level adjustment circuit shown in FIG. 3 are given the same reference numerals.

In the figure, attenuation circuit 24 includes transistors 87, 88 .
It consists of 90.92.94.96 and resistor 98.100. The emitters of the transistors 86 and 88 are connected to the power supply line to which the power supply voltage Vcc is applied from the power supply terminal 76 via the resistors 98 and 100, and the bases of the transistors 87 and the base collectors of the transistors 88 are connected in common, and the transistors 87 .88 and resistance 98.10
0 constitutes a current mirror circuit. The base and collector of transistor 90 are connected in common and input terminal 2
is connected to the formed signal input side.

A constant bias is applied to the base of the transistor 92 from the voltage source 26. transistor 90.92
The emitters of are connected in common through transistors 94 and 96 as diodes having a common base and collector, and a transistor 42 is connected between the emitters of transistors 94 and 96 and a reference potential point through a resistor 44 on the emitter side. A control current Is is applied to the attenuation circuit 24 by the transistor 42 . Signal attenuation is input terminal 2
This is obtained by an input resistor (not shown) connected to the attenuation circuit 24.

The voltage source 26 has a resistor 10 between the power supply line and the reference potential point.
2.104 is connected, and the voltage obtained by dividing the power supply voltage Vcc is taken out via the buffer circuit 106.

Further, the comparator 28 is provided with a pair of transistors 108 and 110 having a common emitter, and each transistor 108 and 110 have a common emitter.
The base of 08.110 is a voltage shift diode 112
．． 114 to the emitters of transistors 116 and 118.

The collectors of each of the transistors 116 and 118 are grounded, the amplified output of the amplifier 46 is applied to the base of the transistor 116, and the output of the voltage source 26 divided by a variable resistor 120 is applied to the base of the transistor 118. ing. Transistors 122 and 124 are connected between the collectors of the transistors 108 and 110 and the reference potential point with their emitters facing the reference potential point. Further, a transistor 126 is connected between the emitters of the transistors 108 and 110 and the power supply line, with the emitter facing the power supply line.
The bases and collectors of transistors 128 are commonly connected. The emitter of the transistor 128 is connected to the power supply line, and a constant current source 130 for setting the operating current of the comparator 28 is installed between the base and collector of the transistor 128 and a reference potential point. The output of this comparator 28 is taken out from the collectors of transistors 108 and 122 and applied to the base of buffer transistor 74. In this embodiment, the reference level set in the comparator 28 is set by a variable resistor 120 instead of a fixed resistor, and the emitter area of the buffer transistor 74 is set large to increase current capacity. A base input provided from the emitter of transistor 74 to the base of transistor 42 is provided via resistor 132.

According to such a configuration, all the circuits except a part of the time constant circuit 82 and the variable resistor 120 can be configured with semiconductor integrated circuits, and stable level adjustment can be performed.
It is possible to obtain the same effects as in the above embodiment.

As explained above, according to the present invention, it is easy to set the maximum operating current to the attenuation circuit, and the time constant circuit recovery time due to differences in power supply voltage or huge input that exceeds the controllable range of the ALC. It is possible to prevent variations in level settings and reduce variations in level settings.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing a conventional automatic level adjustment circuit, FIG. 3 is a circuit diagram showing an embodiment of the automatic level adjustment circuit of the present invention, and FIG. 4 is a circuit diagram showing an embodiment of the automatic level adjustment circuit of the present invention. FIG. 2 is a circuit diagram showing a specific example of a circuit configuration. 24... Attenuation circuit, 2nd... Comparator, 46... Amplifier, 70... Clamp circuit, 74... Transistor as a Bazza circuit, 82... Time constant circuit. Figure 1 Figure 2

Claims (1)

[Claims] A DC amplifier installed in the signal system, a comparator that compares the output of this DC amplifier with a reference level, a clamp circuit that sets the output of this comparator to a potential below a certain value, and a The present invention is characterized by comprising a buffer circuit to which the output of the comparator is applied, and an attenuation circuit installed in a signal system before the DC amplifier and adjusting the input signal level with the output of the buffer circuit. Automatic level adjustment circuit.