JPS60197322A - Method of inner layer reference hole in multi-layer circuit board - Google Patents

Method of inner layer reference hole in multi-layer circuit board

Info

Publication number
JPS60197322A
JPS60197322A JP5278984A JP5278984A JPS60197322A JP S60197322 A JPS60197322 A JP S60197322A JP 5278984 A JP5278984 A JP 5278984A JP 5278984 A JP5278984 A JP 5278984A JP S60197322 A JPS60197322 A JP S60197322A
Authority
JP
Japan
Prior art keywords
circuit board
inner layer
multilayer circuit
positions
conductor pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5278984A
Other languages
Japanese (ja)
Other versions
JPH0451291B2 (en
Inventor
Toru Murayama
徹 村山
Kazuo Enomoto
和夫 榎本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Chemical Products Co Ltd
Kyocera Chemical Corp
Original Assignee
Toshiba Chemical Products Co Ltd
Toshiba Chemical Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Chemical Products Co Ltd, Toshiba Chemical Corp filed Critical Toshiba Chemical Products Co Ltd
Priority to JP5278984A priority Critical patent/JPS60197322A/en
Publication of JPS60197322A publication Critical patent/JPS60197322A/en
Publication of JPH0451291B2 publication Critical patent/JPH0451291B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Drilling And Boring (AREA)

Abstract

PURPOSE:To drill reference holes with no locating hole, by smoothly grinding two adjacent sides on the outer periphery of a substrate to expose the outer edge section of a conductive pattern layer formed therein with inner layer reference holes so that the positions of the reference holes are obtained from discontinuous points. CONSTITUTION:All four sides of a multi-layer circuit board 3 are smoothed by grinding them while the outer edge section of a conductive layer 1b of the board 3 is exposed, and the positions of discontinuous points PX, PY on the conductive pattern layer are determined by means of a detector. When the positions of the discontinuous points have been obtained for every side, the positions distant from the discontinuous points PX, PY by known distances X, Y are set as the positions of reference holes, and therefore, the drill positions are determined in accordance with the positions of the reference holes, thereby inner layer reference holes 8 are drilled at predetermined positions.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明は多層回路基板の内層基準穴の穿孔方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for drilling inner layer reference holes in a multilayer circuit board.

[発明の技術的背景] 一般に多層回路基板には、第1図に拡大断面で示すよう
に、表層および裏層の導体パターン層1a、Inの他に
複数層の絶縁層2a 、 2b 、・・・・・・を介し
て各絶縁層間に導体パターン層1b、1c。
[Technical Background of the Invention] In general, a multilayer circuit board includes a conductor pattern layer 1a on a surface layer and a back layer, and a plurality of insulating layers 2a, 2b, . . . in addition to In, as shown in an enlarged cross section in FIG. Conductor pattern layers 1b, 1c are interposed between each insulating layer through...

・・・・・・が設けられている。...... is provided.

これらの導体パターン層1a1’lb、・・・111は
一般に銅箔により形成されており、絶縁層はガラス繊維
−エポキシ樹脂、紙−エポキシ樹脂、紙−フェノール樹
脂等の複合材料により構成されている。
These conductor pattern layers 1a1'lb, . . . 111 are generally made of copper foil, and the insulating layer is made of a composite material such as glass fiber-epoxy resin, paper-epoxy resin, paper-phenol resin, etc. .

これらの導体パターン層1a、Ib、・・・1nは表層
および裏層合せて4層、6層、8層等多くの層からなっ
ており、中間層の導体パターン11b。
These conductor pattern layers 1a, Ib, .

1c、・・・は全で所定のパターンにエツチングされた
状態で絶縁層2a12b・・・間に埋め込まれている。
1c, . . . are all etched into a predetermined pattern and embedded between the insulating layers 2a, 12b, .

これら中間の導体パターン層1b、1c1・・・は、多
層回路基板3が完成した状態では外部からは微かに見え
る程度であり、完全に透視することは不可能である。
These intermediate conductor pattern layers 1b, 1c1, . . . are only slightly visible from the outside when the multilayer circuit board 3 is completed, and cannot be completely seen through.

この多層回路基板は、各種電気部品を取付けて使用する
際、所定の層の導体パターンに外部から穿孔された穴の
内面に金属めつき(スルーホールめっき)を施すことに
より、外部と導体パターン間を電気的に接続可能とされ
る。
When using this multilayer circuit board with various electrical components installed, metal plating (through-hole plating) is applied to the inner surface of the hole drilled from the outside in the conductor pattern of a predetermined layer. can be electrically connected.

穿孔は所望の導体パターンの位置に確実に行なう必要が
あるため、通常基準になる穴(内層基準穴)を予め2個
以上穿けておき、この内層基準穴の位置を基準として図
面寸法に基づいて所定の位置に穿孔することが行われて
いる。
Since it is necessary to make the holes reliably at the desired conductor pattern positions, two or more reference holes (inner layer reference holes) are usually drilled in advance, and the holes are drilled based on the drawing dimensions using the inner layer reference hole positions as a reference. Drilling holes in predetermined locations is performed.

この内層基準穴の穿孔方法としては、従来から次のよう
な方法が採ら゛れている。
Conventionally, the following method has been used to form the inner layer reference hole.

(イ)表面層に微かに現れる中間層の内層基準穴のパタ
ーンを基にして、第2図に示すように、まずざぐり用ド
リル4を使用して内装基準穴より大きめのさぐり穴5を
この導体パターン層の位置まで正確に開げる。
(b) Based on the pattern of the inner layer reference hole of the intermediate layer that slightly appears on the surface layer, first use a counterbore drill 4 to drill a hole 5 larger than the inner reference hole, as shown in Figure 2. Open accurately to the position of the conductor pattern layer.

これによって導体パターン層1bがざくり穴5の底に見
えるようになるので、この露出した導体パターン層1b
の内層基準穴6を目視しながら所定の位置に多層回路基
板全体を貫通して内層基準穴を穿孔する。
As a result, the conductor pattern layer 1b becomes visible at the bottom of the counterbore hole 5, so the exposed conductor pattern layer 1b
The inner layer reference holes are drilled through the entire multilayer circuit board at predetermined positions while visually checking the inner layer reference holes 6.

(ロ)予め第3図に示すように、導体パターン層1bの
内層基準穴の部分に粘着剤により塩化ビニル樹脂フィル
ムの小片7を貼っておき、多層回路基板3の完成後にお
いても導体パターン層1bの内層基準穴6の位置が外部
から容易に透視可能なようにしておき、この位置に(イ
)の場合と同様にざぐり用ドリルによりざぐり穴を開け
て所定の導体パターン層1bの内層基準穴の位置を露出
させ、その後導体パターン層1bの内層基準穴6の位置
に目視により穿孔する。この方法では、外部から内層基
準穴の位置がわかり易いうえに、ざくり穴を開ける際に
さぐり用ドリルが塩化ビニル樹脂フィルムの小片7を排
出するタイミングに注意することにより誤って深くざく
り過ぎることが防止できる。
(b) As shown in FIG. 3, a small piece 7 of vinyl chloride resin film is pasted with an adhesive on the inner layer reference hole portion of the conductor pattern layer 1b, and even after the multilayer circuit board 3 is completed, the conductor pattern layer The position of the inner layer reference hole 6 of the conductor pattern layer 1b is made so that it can be easily seen from the outside, and a counterbore hole is drilled at this position with a counterbore drill as in the case of (a) to set the inner layer reference of the predetermined conductor pattern layer 1b. The position of the hole is exposed, and then the hole is visually drilled at the position of the inner layer reference hole 6 of the conductor pattern layer 1b. With this method, the position of the inner layer reference hole is easy to see from the outside, and by paying attention to the timing when the digging drill ejects the small piece 7 of the PVC resin film when counterboring the hole, it is possible to prevent the hole from being bored too deep by mistake. can.

[背景技術の問題点] しかしながら、これら(イ)、(ロ)のいずれの方法に
おいても、所定の導体パターン層1bの内層基準穴6の
位置に穿孔するのに、まずおおよその位置に大きめのざ
くり穴を開けて中間導体パターン層1bの内層基準穴6
を露出させ、その後多層回路基板3全体を貫通して内層
基準穴6を穿孔するという2工程を必要とし、作業性が
悪いうえに特に前工程のざくり穴の穿孔には熟練を要す
るため、自動化が困難であるという欠点があった。
[Problems in the Background Art] However, in both methods (a) and (b), in order to drill holes at the positions of the inner layer reference holes 6 of the predetermined conductor pattern layer 1b, first, a larger hole is drilled at the approximate position. Make a counterbore hole and make an inner layer reference hole 6 of the intermediate conductor pattern layer 1b.
It requires two steps: exposing the multilayer circuit board 3 and then drilling the inner layer reference hole 6 through the entire multilayer circuit board 3, which is not easy to work with and requires skill especially in drilling the countersunk holes in the previous process, so automation is not possible. The disadvantage was that it was difficult.

また第4図に示すようにざぐり穴5の位置が内層基準穴
6の位置より大きくずれた場合には、ドリルの位置決め
が難しくなる上に上面に連結した2つの穴の輪郭が形成
されて外観上好ましくないという難点があった。
Furthermore, as shown in Fig. 4, if the position of the counterbore hole 5 deviates significantly from the position of the inner layer reference hole 6, it becomes difficult to position the drill, and the outline of two connected holes is formed on the top surface, resulting in an external appearance. The problem was that it was not very desirable.

[発明の目的] 本発明は、このような従来の欠点を解消すべくなされた
もので、ざぐり穴を穿設することなく1工程で容易に導
体パターンの所定の位置に内層基準穴を穿孔することの
できる多層回路基板の内層基準穴の穿孔方法を提供する
ことを目的とする。
[Object of the Invention] The present invention has been made to solve these conventional drawbacks, and is capable of easily drilling inner layer reference holes at predetermined positions of a conductor pattern in one step without drilling counterbored holes. An object of the present invention is to provide a method for drilling inner layer reference holes in a multilayer circuit board.

[発明の概要] すなわち本発明の多層回路基板の内層基準穴の穿孔方法
は、(A)多層回路基板の外周の少なくとも隣り合う2
つの辺部を研削して平滑化するとともに多層1回路基板
の内層基準穴の形成された導体パターン層の外縁部を露
出させる工程と、(B)前・記露出された導体パターン
層の外縁部の不連続点を検出する工程と、 (C)検出された導体パターン層の外縁部の不連続点の
位置から内層基準穴の位置をめてこの位置に穿孔する工
程 とからなることを特徴としている。
[Summary of the Invention] That is, the method for drilling inner layer reference holes in a multilayer circuit board according to the present invention includes: (A) at least two adjacent holes on the outer periphery of a multilayer circuit board;
(B) the step of grinding and smoothing the two sides and exposing the outer edge of the conductor pattern layer in which the inner layer reference hole of the multilayer circuit board is formed; (B) the outer edge of the exposed conductor pattern layer; (C) locating an inner layer reference hole from the position of the detected discontinuity point on the outer edge of the conductor pattern layer and drilling a hole at this position. There is.

[発明の実施例] 以下本発明の一実施例を図面に基づいて説明する。[Embodiments of the invention] An embodiment of the present invention will be described below based on the drawings.

第5図は多層回路基板の導体パターンを概念的に示す平
面図である。
FIG. 5 is a plan view conceptually showing the conductor pattern of the multilayer circuit board.

第5図において、多層回路基板3の導体パターン層1b
の外縁部には、通常内層基準穴6の設けられている導体
パターンAの外縁部とこれと電気的に独立した導体パタ
ーンBの外縁部が露出しているが、導体パターンを形成
する際、この外縁部には通常各辺毎に複数の導体パター
ンのない部分、ずなわち導体パターンの不連続部分Cが
現われる。
In FIG. 5, the conductor pattern layer 1b of the multilayer circuit board 3
The outer edge of the conductor pattern A, where the inner layer reference hole 6 is normally provided, and the outer edge of the conductor pattern B, which is electrically independent from the outer edge of the conductor pattern A, are exposed at the outer edge of the conductor pattern. In this outer edge, a plurality of portions without a conductor pattern, ie, discontinuous portions C of the conductor pattern usually appear on each side.

この不連続部分Cは多層回路基板3の設計段階において
決められるものであるから、この不連続部分Cと内層基
準穴6との相対位置関係は予め決定されている。
Since this discontinuous portion C is determined at the design stage of the multilayer circuit board 3, the relative positional relationship between this discontinuous portion C and the inner layer reference hole 6 is determined in advance.

なお、回路設計上からはこのような電気的に独立した2
つの導体パターンが同−辺に露出できない場合であった
り、不連続点の位置が不適当な場合には、内層基準穴〇
から辺に平行に延長した位置に位置検出用の導体パター
ンを別に設けこれに切欠部を形成して不連続部としても
よい。
Note that from a circuit design point of view, two electrically independent
If two conductor patterns cannot be exposed on the same side, or if the discontinuity point is at an inappropriate position, install a separate conductor pattern for position detection at a position extending parallel to the side from the inner layer reference hole 〇. A notch may be formed in this to form a discontinuous portion.

しかして、この実施例においては、多層回路基板3の完
成後、この多層回路基板3の4つの辺が研削され、各辺
が平温にされるとともに多層回路基板3の導体パターン
層1bの外縁部が露出される。
In this embodiment, after the multilayer circuit board 3 is completed, the four sides of the multilayer circuit board 3 are ground, each side is brought to a normal temperature, and the outer edge of the conductor pattern layer 1b of the multilayer circuit board 3 is ground. part is exposed.

次にこの多層回路基板3の導体パターンの各辺における
導体パターンの不連続点PX、PYの位置が検出される
。この不連続点Px、Pvの位置の検出手段としては電
気接点による方法が簡便であるが、この方法に限らず、
例えば光学的に検出することも可能である。
Next, the positions of discontinuous points PX and PY of the conductor pattern on each side of the conductor pattern of this multilayer circuit board 3 are detected. As a means for detecting the positions of these discontinuous points Px and Pv, a method using electrical contacts is convenient, but it is not limited to this method.
For example, optical detection is also possible.

第6図はこのような不連続部−の検出に用いられる内層
基準尺検出装置の1例を示す平面図、@7図はその■方
向から見た側面図である。
FIG. 6 is a plan view showing an example of an inner layer standard measuring device used for detecting such a discontinuous portion, and FIG.

この検出装置8は、上面に位置決め用のストッパー9.
9を備えた基盤10と、多層回路基板3を固定するため
の真空吸盤11.11と、多層回路基板3の辺部に露出
した導体パターン層の不連続点を検出する3組の不連続
点検知装置12とから構成されている。
This detection device 8 has a positioning stopper 9 on the top surface.
9, a vacuum suction cup 11.11 for fixing the multilayer circuit board 3, and three sets of discontinuities for detecting discontinuities in the conductor pattern layer exposed on the sides of the multilayer circuit board 3. It is composed of a detection device 12.

不連続点検知装置12は、真空吸盤11.11に固定さ
れる多層回路基板3の辺部に沿って配置された流体シリ
ンダー13と、この流体シリンダー13のピストン14
の先端に固定されたローラー状電気接点15と、この電
気接点15のおよその位置を計測する目盛板16と、図
示を省略した、電気接点15の導体パターンとの接触の
有無を検出する検出回路および電気接点の位置信号をド
リルの駆動制御回路に送ってドリルを内層基準穴の穿孔
位置へ移動させる穿孔位置制御回路とから構成されてい
る。17は目盛板の指標、18は導体パターンへ検出電
圧を供給するための電極である。
The discontinuity detection device 12 includes a fluid cylinder 13 disposed along the side of the multilayer circuit board 3 fixed to a vacuum suction cup 11.11, and a piston 14 of the fluid cylinder 13.
A roller-shaped electrical contact 15 fixed to the tip of the electrical contact 15, a scale plate 16 for measuring the approximate position of the electrical contact 15, and a detection circuit (not shown) for detecting the presence or absence of contact between the electrical contact 15 and the conductor pattern. and a drilling position control circuit that sends a position signal of the electrical contact to a drive control circuit of the drill to move the drill to the drilling position of the inner layer reference hole. Reference numeral 17 indicates an index of the scale plate, and reference numeral 18 indicates an electrode for supplying a detection voltage to the conductor pattern.

この検出装置8においては、まず導体パターンの内層基
準穴に穿孔すべき多層回路基板3が一辺をストッパー9
.9に当接されて位置決めされ、次いで真空吸盤11に
吸引固定される。
In this detection device 8, first, the multilayer circuit board 3 to be drilled into the inner layer reference hole of the conductor pattern has one side attached to the stopper 9.
.. 9 and is positioned, and then suctioned and fixed to the vacuum suction cup 11.

次に電極18を多層回路基板3の導体パターンAの任意
の位置に接触させ、流体シリンダー13を作動させて第
8図に示すようにピストン14先端の電気接点15を多
層回路基板19の露出した導体パターン1bに当接させ
た状態で多層回路基板19の各辺に沿って移動させる。
Next, the electrode 18 is brought into contact with an arbitrary position of the conductor pattern A of the multilayer circuit board 3, and the fluid cylinder 13 is actuated to connect the electric contact 15 at the tip of the piston 14 to the exposed surface of the multilayer circuit board 19, as shown in FIG. It is moved along each side of the multilayer circuit board 19 while in contact with the conductive pattern 1b.

このとぎ、電極18と電気接点15との電気的接続が断
たれた位置が不連続点とされる。
At this point, the position where the electrical connection between the electrode 18 and the electrical contact 15 is broken is defined as a discontinuity point.

このようにして各辺の不連続点の位置がめられた後、第
5図における不連続点Px、Pvからそれぞれ既知のX
、Yの距離だけ移動させた位置が内層M単穴の位置と判
断される。したがって、この位置データに基づいてドリ
ルを位置決めし、穿孔すれば所定の位置に内層基準穴を
穿孔することができる。なお、対象とする多層回路基板
の辺部に多数の不連続点がある場合には、そのうちの任
意の不連続点を基準として使用すればよい。
After the positions of the discontinuous points on each side have been determined in this way, from the discontinuous points Px and Pv in FIG.
, Y is determined to be the position of the single hole in the inner layer M. Therefore, by positioning the drill based on this position data and drilling, it is possible to drill the inner layer reference hole at a predetermined position. Note that if there are many discontinuous points on the side of the target multilayer circuit board, any one of them may be used as a reference.

なお、辺に沿って設けた内装基準穴の位置が完全に辺と
平行になっている場合には、上述したように直交する2
つの辺の不連続点を検出しただけで内装基準穴を穿孔す
ることが可能であるが、必要に応じて他の辺についても
不連続点を検出してこれを基準と實るようにしてもよい
In addition, if the position of the interior reference hole provided along the side is completely parallel to the side, the two orthogonal holes as described above
It is possible to drill an interior reference hole by simply detecting a discontinuous point on one side, but if necessary, it is also possible to detect discontinuous points on other sides and use this as a reference. good.

さらにドリルの位置決めをこの不連続点の位置データを
基に、自動で行なわせることも可能であるが、必要に応
じて不連続点の位置を多層回路基板上に標示し、作図に
より内層基準穴の位置をめて、この位置に手作業により
内層基準穴を穿設することも可能である。
Furthermore, it is possible to automatically position the drill based on the position data of this discontinuous point, but if necessary, the position of the discontinuous point can be marked on the multilayer circuit board and the inner layer reference hole can be drawn by drawing. It is also possible to manually drill an inner layer reference hole at this position.

[発明−の効果] 以上説明したように本発明によれば、多層回路基板の内
層基準穴を1工程で容易に穿設することができ、また内
層基準穴の位置検出および穿孔を特に人手に頼らず行な
うこともできるので、全体のシステムを自動化すること
が可能である。
[Effects of the Invention] As explained above, according to the present invention, the inner layer reference hole of a multilayer circuit board can be easily drilled in one step, and the position detection and drilling of the inner layer reference hole can be particularly done manually. Since it can be done without relying on other people, it is possible to automate the entire system.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は多層回路基板を概念的に示す拡大断面図、第2
図は内層基準穴までざぐり穴を穿設した状態を示す断面
図、第3図は他の従来の方法に用いられる塩化ビニル樹
脂の小片を埋設した多層回路基板の拡大断面図、第4図
は従来の方法においてざぐり穴の底部に現われた内層基
準穴を示す平面図、第5図は多層回路基板を概念的に示
す平面図、第6図は本発明の実施例に使用する内層基準
式検出装置を示す平面図、第7図はその側面図、第8図
は電気接点およびその多層回路基板への当接位置を示す
正面図である。 1a・・・1n・・・導体パターン層 2a、2b・・・絶縁層 3・・・・・・・・・・・・・・・多層回路基板4・・
・・・・・・・・・・・・・ざぐり用ドリル5・・・・
・・・・・・・・・・・ざぐり穴6・・・・・・・・・
・・・・・・内層基準穴7・・・・・・・・・・・・・
・・塩化ビニル樹脂フィルムの小片 8・・・・・・・・・・・・・・・内層基準式検出装置
9・・・・・・・・・・・・・・・・ストッパー11・
・・・・・・・・・・・・・・真空吸盤12・・・・・
・・・・・・・・・・不連続点検知装置13・・・・・
・・・・・・・・・・流体シリンダー14・・・・・・
・・・・・・・・・ピストン15・・・・・・・・・・
・・・・・電気接点PX、PY・・・・・・不連続点 代理人弁理士 須 山 佐 − 第1図 第2図 第3図 第4図 第5園 第7図 10 第8図 7
Figure 1 is an enlarged sectional view conceptually showing a multilayer circuit board, Figure 2
The figure is a cross-sectional view showing a state in which a counterbore hole has been drilled up to the inner layer reference hole, Figure 3 is an enlarged cross-sectional view of a multilayer circuit board in which small pieces of vinyl chloride resin used in another conventional method are embedded, and Figure 4 is A plan view showing an inner layer reference hole appearing at the bottom of a counterbore hole in the conventional method, FIG. 5 is a plan view conceptually showing a multilayer circuit board, and FIG. 6 is an inner layer reference type detection used in an embodiment of the present invention. FIG. 7 is a plan view showing the device, FIG. 7 is a side view thereof, and FIG. 8 is a front view showing the electrical contacts and their contact positions on the multilayer circuit board. 1a...1n...Conductor pattern layers 2a, 2b...Insulating layer 3...Multilayer circuit board 4...
・・・・・・・・・・・・Countersboring drill 5・・・・・・
・・・・・・・・・Counterbore hole 6・・・・・・・・・
・・・・・・Inner layer reference hole 7・・・・・・・・・・・・・・・
・・Small piece of vinyl chloride resin film 8 ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・Vacuum sucker 12・・・・・・
......Discontinuity point detection device 13...
......Fluid cylinder 14...
・・・・・・・・・Piston 15・・・・・・・・・・
...Electrical contacts PX, PY...Discontinuity point Patent attorney Sa Suyama - Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Garden Figure 7 Figure 10 Figure 8 7

Claims (2)

【特許請求の範囲】[Claims] (1) (A)多層回路基板の外周の少なくとも隣り合
う2つの辺部を研削して平滑化するとともに多層回路基
板の内層基準穴の形成された導体パターン層の外縁部を
露出させる工程と、 (B)前記露出された導体パターン層の外縁部の不連続
点を検出する工程と、 (C)検出された導体パターン層の外縁部の不連続点の
位置から内層基準穴の位置をめてこの位置に穿孔する工
程 とからなることを特徴とする多層回路基板の内層基準穴
の穿孔方法。
(1) (A) A step of grinding and smoothing at least two adjacent sides of the outer periphery of the multilayer circuit board and exposing the outer edge of the conductor pattern layer in which the inner layer reference hole of the multilayer circuit board is formed; (B) detecting a discontinuous point on the outer edge of the exposed conductive pattern layer; (C) locating the inner layer reference hole from the position of the detected discontinuous point on the outer edge of the conductive pattern layer; A method for drilling an inner layer reference hole in a multilayer circuit board, the method comprising the step of drilling a hole at this position.
(2)(A>の研削および(B)(7)導体パターンの
外縁部の不連続点の検出が多層回路基板の3つの辺部に
ついて行なわれる特許請求の範囲第1項記載の多層回路
基板の内層基準穴の穿孔方法。
The multilayer circuit board according to claim 1, wherein (2) (A>) grinding and (B) (7) detection of discontinuous points on the outer edge of the conductor pattern are performed on three sides of the multilayer circuit board. How to drill the inner layer reference hole.
JP5278984A 1984-03-19 1984-03-19 Method of inner layer reference hole in multi-layer circuit board Granted JPS60197322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5278984A JPS60197322A (en) 1984-03-19 1984-03-19 Method of inner layer reference hole in multi-layer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5278984A JPS60197322A (en) 1984-03-19 1984-03-19 Method of inner layer reference hole in multi-layer circuit board

Publications (2)

Publication Number Publication Date
JPS60197322A true JPS60197322A (en) 1985-10-05
JPH0451291B2 JPH0451291B2 (en) 1992-08-18

Family

ID=12924598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5278984A Granted JPS60197322A (en) 1984-03-19 1984-03-19 Method of inner layer reference hole in multi-layer circuit board

Country Status (1)

Country Link
JP (1) JPS60197322A (en)

Also Published As

Publication number Publication date
JPH0451291B2 (en) 1992-08-18

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