JPH0132763Y2 - - Google Patents

Info

Publication number
JPH0132763Y2
JPH0132763Y2 JP1982045444U JP4544482U JPH0132763Y2 JP H0132763 Y2 JPH0132763 Y2 JP H0132763Y2 JP 1982045444 U JP1982045444 U JP 1982045444U JP 4544482 U JP4544482 U JP 4544482U JP H0132763 Y2 JPH0132763 Y2 JP H0132763Y2
Authority
JP
Japan
Prior art keywords
overlay
notch
conductive pattern
insulating substrate
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982045444U
Other languages
Japanese (ja)
Other versions
JPS58147274U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4544482U priority Critical patent/JPS58147274U/en
Publication of JPS58147274U publication Critical patent/JPS58147274U/en
Application granted granted Critical
Publication of JPH0132763Y2 publication Critical patent/JPH0132763Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案はエツチング等により形成した導電パタ
ーンの必要な部分にオーバレイを貼付けて構成さ
れる印刷配線板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printed wiring board constructed by pasting overlays on necessary parts of a conductive pattern formed by etching or the like.

従来の印刷配線板としては第1図に示すように
絶縁基板1上にエツチングなどの方法により導電
パターン2を形成し、この絶縁基板1上に上記導
電パターン2の必要な部分、たとえばランド部に
相当する位置に透孔3を形成したポリイミドフイ
ルムやポリエステルフイルムなどよりなるオーバ
レイ4を貼付けて構成しているが、この導電パタ
ーン2とオーバレイ4の透孔3の位置合せが重要
となつてくる。従来、この位置合せは、オーバレ
イ4を貼付ける際に目視で位置決めして行つてい
たが、その位置合せは不正確になるものであつ
た。
In a conventional printed wiring board, as shown in FIG. 1, a conductive pattern 2 is formed on an insulating substrate 1 by a method such as etching. An overlay 4 made of polyimide film, polyester film, or the like with through holes 3 formed in corresponding positions is pasted, but alignment of the conductive pattern 2 and the through holes 3 of the overlay 4 is important. Conventionally, this alignment has been performed by visually determining the position when pasting the overlay 4, but this alignment has been inaccurate.

このようなことから、第2図、第3図に示すよ
うに、数本のガイドピン5を立設した基台6を用
い、絶縁基板1に設けた位置決め孔7を上記ガイ
ドピン5にはめこみ、続いてオーバレイ4に設け
た位置決め孔8をガイドピン5にはめこんで絶縁
基板1とオーバレイ4を位置決めしてオーバレイ
4を絶縁基板1に熱圧着などで貼付ける方法が採
用されている。
For this reason, as shown in FIGS. 2 and 3, a base 6 on which several guide pins 5 are set up is used, and positioning holes 7 provided in the insulating substrate 1 are fitted into the guide pins 5. Next, a method is adopted in which the positioning holes 8 provided in the overlay 4 are inserted into the guide pins 5 to position the insulating substrate 1 and the overlay 4, and the overlay 4 is attached to the insulating substrate 1 by thermocompression bonding or the like.

しかしながら、最近の印刷配線板は高密度化が
進み目視による位置決めはいうまでもなく、ガイ
ドピン5による位置決めでも十分な精度の位置決
めが行えず、しかもガイドピン5をむやみに増す
ことは作業性の点で不利となり、またワークサイ
ズも大きくなつてきており、オーバレイ4は通常
25μm接着剤付でも100μm以下と薄いためガイド
ピン5の周辺では正確に位置決めができても、ガ
イドピン5から離れた位置では少しの外力が加え
られるだけでも位置ずれを生じやすく不安定なも
のとなつていた。
However, as the density of printed wiring boards has increased recently, it is not possible to perform positioning with sufficient accuracy even with the guide pins 5, let alone visual positioning, and unnecessarily increasing the number of guide pins 5 impedes work efficiency. Overlay 4 is usually at a disadvantage as the work size is increasing.
Even with 25μm adhesive, it is thin at less than 100μm, so even if it is possible to accurately position it around the guide pin 5, it is likely to shift position away from the guide pin 5 even if a small amount of external force is applied, making it unstable. I was getting used to it.

しかも、この絶縁基板1の導電パターン2とオ
ーバレイ4との接着後の位置ずれの確認は、第4
図に示すように導電パターン2のランド部2aと
オーバレイ4の透孔3とのずれ、すなわち、円形
の導電ランド2aと同心円のオーバレイ4の透孔
3によるランド被覆部の寸法hを測定することに
より確認したり、第5図に示すように導電パター
ン2のランド部2aに設ける部品取付孔9とオー
バレイ4の透孔3との寸法h′を測定することによ
り行つていたが、これは手間を要し、作業性の悪
いものとなつていた。
Moreover, confirmation of positional deviation after adhesion between the conductive pattern 2 of the insulating substrate 1 and the overlay 4 is performed in the fourth step.
As shown in the figure, measure the deviation between the land portion 2a of the conductive pattern 2 and the through hole 3 of the overlay 4, that is, the dimension h of the land covered portion by the circular conductive land 2a and the concentric through hole 3 of the overlay 4. This was done by checking the dimensions h' between the component mounting hole 9 provided in the land portion 2a of the conductive pattern 2 and the through hole 3 of the overlay 4 as shown in FIG. This was time-consuming and resulted in poor workability.

本考案は以上のような従来の欠点を除去するも
のであり、オーバレイの貼付け状態の確認が簡単
かつ確実に行える印刷配線板を提供することを目
的とするものである。
The present invention eliminates the above-mentioned conventional drawbacks, and aims to provide a printed wiring board in which the state of overlay attachment can be easily and reliably confirmed.

上記目的を達成するために本考案は絶縁基板上
に形成する導電パターンに影響を与えない位置に
槍先状の切欠部を有する導体部分を設け、この槍
先状の切欠部によりオーバレイの貼付け状態を検
出できる構成としたものである。
In order to achieve the above object, the present invention provides a conductor portion having a spear tip-shaped notch at a position that does not affect the conductive pattern formed on the insulating substrate, and this spear tip shaped notch allows the overlay to be attached easily. The structure is such that it can detect.

以下、本考案の実施例を図面第6図〜第9図に
より説明する。
Embodiments of the present invention will be described below with reference to FIGS. 6 to 9.

まず第6図、第7図において、10は絶縁フイ
ルムや硬質絶縁板よりなる絶縁基板でこの絶縁基
板10上には、あらかじめ貼付けた銅箔などをエ
ツチングして構成した導電パターン11が形成さ
れるとともに、この導電パターン11に影響を与
えないような位置に、上記エツチング時に槍先状
の切欠部12を有する導電層13を設け、この絶
縁基板10上には上記導電パターン11のランド
部に相当する部分に透孔14を形成したポリイミ
ドフイルムやポリエステルフイルムなどからなる
オーバレイ15を接着剤などを用いて貼付けられ
ている。このオーバレイ15の上記導電層13の
切欠部12に相当する部分はランド用透孔などの
直線端部が位置するようになつている。また、上
記切欠部12は第7図に示すようにその中心から
の寸法mをずれの許容公差0.2mmとしてある。
First, in FIGS. 6 and 7, reference numeral 10 denotes an insulating substrate made of an insulating film or a hard insulating plate. On this insulating substrate 10, a conductive pattern 11 is formed by etching a copper foil or the like that has been pasted in advance. At the same time, a conductive layer 13 having a spear tip-shaped notch 12 is provided at a position that does not affect the conductive pattern 11 during the etching, and a conductive layer 13 is provided on the insulating substrate 10 corresponding to the land portion of the conductive pattern 11. An overlay 15 made of polyimide film, polyester film, or the like with through holes 14 formed therein is attached using an adhesive or the like. A portion of this overlay 15 corresponding to the notch 12 of the conductive layer 13 is arranged such that a straight end portion of a through hole for a land or the like is located. Further, as shown in FIG. 7, the notch 12 has a dimension m from its center with an allowable deviation of 0.2 mm.

なお、導電層13に設ける切欠部12としては
第8図に示すようにV字状としても、第9図に示
すように方形状の中央にV字状部を設けた構成と
することもできる。
Note that the notch 12 provided in the conductive layer 13 may have a V-shape as shown in FIG. 8, or may have a V-shape in the center of a rectangular shape as shown in FIG. .

すなわち、本考案では、この切欠部12として
先端にV字状部を有するものであればよい。
That is, in the present invention, the notch 12 may have a V-shaped portion at its tip.

また、この切欠部12を設けた導電層13は印
刷配線板の完成品とするときにはスクラツプとし
て打抜かれてすてることもできる。
Furthermore, the conductive layer 13 provided with the notch 12 can be punched out and discarded as scrap when it is used as a finished printed wiring board.

以上のように本考案の印刷配線板は構成される
ため導電パターンとオーバレイとの貼合せ状態が
一目で確認でき、切欠部の幅内にオーバレイの端
部が位置すれば良品と判断することができ、かつ
貼合せ時に位置決めする目やすとしても有効とな
り、歩留りの大幅な向上が計れ、高密度の導電パ
ターンを有するものにおいても有効となるなどの
利点をもち、実用的価値の大なるものである。
Since the printed wiring board of the present invention is constructed as described above, the bonding condition between the conductive pattern and the overlay can be confirmed at a glance, and if the end of the overlay is located within the width of the notch, it can be judged as a good product. It has the advantage of being effective as a guide for positioning during lamination, greatly improving yield, and being effective even for products with high-density conductive patterns, and has great practical value. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の印刷配線板の組立工程の一部を
示す要部の分解斜視図、第2図は他の従来の印刷
配線板の組立工程の一部を示す要部の分解斜視
図、第3図は同組立時の断面図、第4図、第5図
は従来の印刷配線板の位置ずれを検査する部分を
示す要部の上面図、第6図は本考案の印刷配線板
の一実施例を示す要部の斜視図、第7図は同要部
の上面図、第8図、第9図は他の実施例の位置決
め用の切欠部の上面図である。 10……絶縁基板、11……導電パターン、1
2……切欠部、13……導電層、14……透孔、
15……オーバレイ。
FIG. 1 is an exploded perspective view of main parts showing a part of a conventional printed wiring board assembly process, FIG. 2 is an exploded perspective view of main parts showing a part of another conventional printed wiring board assembly process, Figure 3 is a cross-sectional view of the assembly, Figures 4 and 5 are top views of the main parts of the conventional printed wiring board that inspects the positional deviation, and Figure 6 is the printed wiring board of the present invention. FIG. 7 is a perspective view of a main part showing one embodiment, FIG. 7 is a top view of the main part, and FIGS. 8 and 9 are top views of a notch for positioning of other embodiments. 10... Insulating substrate, 11... Conductive pattern, 1
2... Notch, 13... Conductive layer, 14... Through hole,
15...Overlay.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板上に導電パターンとともにこの導電パ
ターンに影響を与えない部分に先端にV字状部を
有する切欠部をもつた導電層を設け、この絶縁基
板の導電パターンのランド部に相当する部分に透
孔をもち、さらに前記切欠部に対応する位置に直
線状端部をもつオーバレイを貼付けて構成してな
る印刷配線板。
A conductive layer having a notch with a V-shaped portion at the tip is provided along with the conductive pattern on the insulating substrate in a portion that does not affect the conductive pattern, and a conductive layer is provided on the insulating substrate with a cutout portion having a V-shaped portion at the tip. A printed wiring board having a hole and further having an overlay attached thereto having a linear end at a position corresponding to the notch.
JP4544482U 1982-03-29 1982-03-29 printed wiring board Granted JPS58147274U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4544482U JPS58147274U (en) 1982-03-29 1982-03-29 printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4544482U JPS58147274U (en) 1982-03-29 1982-03-29 printed wiring board

Publications (2)

Publication Number Publication Date
JPS58147274U JPS58147274U (en) 1983-10-03
JPH0132763Y2 true JPH0132763Y2 (en) 1989-10-05

Family

ID=30056464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4544482U Granted JPS58147274U (en) 1982-03-29 1982-03-29 printed wiring board

Country Status (1)

Country Link
JP (1) JPS58147274U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4607612B2 (en) * 2005-02-09 2011-01-05 日東電工株式会社 Wiring circuit board and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519015U (en) * 1978-07-24 1980-02-06
JPS5541556A (en) * 1978-09-19 1980-03-24 Nippon Kogaku Kk <Nikon> Digital servo unit
JPS5540550B2 (en) * 1977-06-22 1980-10-18

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5540550U (en) * 1978-09-06 1980-03-15

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5540550B2 (en) * 1977-06-22 1980-10-18
JPS5519015U (en) * 1978-07-24 1980-02-06
JPS5541556A (en) * 1978-09-19 1980-03-24 Nippon Kogaku Kk <Nikon> Digital servo unit

Also Published As

Publication number Publication date
JPS58147274U (en) 1983-10-03

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