JPS6018945A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6018945A
JPS6018945A JP58126651A JP12665183A JPS6018945A JP S6018945 A JPS6018945 A JP S6018945A JP 58126651 A JP58126651 A JP 58126651A JP 12665183 A JP12665183 A JP 12665183A JP S6018945 A JPS6018945 A JP S6018945A
Authority
JP
Japan
Prior art keywords
film
moisture
insulating film
psg
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58126651A
Other languages
Japanese (ja)
Inventor
Masahiro Yamada
正弘 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58126651A priority Critical patent/JPS6018945A/en
Publication of JPS6018945A publication Critical patent/JPS6018945A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the generation of Al corrosion by the intrusion of moisture by obviating the formation of an inter-layer insulating film under a bonding pad in a semiconductor device using phosphorus silicate glass as the inter- layer insulating film. CONSTITUTION:A thermal oxide film 202 for isolating an element is formed on an Si substrate 201, and a phosphorus silicate glass (PSG) film is deposited as an inter-layer insulating film 203 and etched and formed. The film 203 on the scribing line side is removed gradually through etching from a bonding pad 204 region at that time. A passivation film 205 is shaped. When dicing a semiconductor device, one part of the film 205 is broken off at the dicing end of a scribing line. Consequently, it is considered that moisture intrudes from a path shown by the arrow, but moisture is difficult to be absorbed because there is no film 203 on the scribing line side of the pad 204. Even when moisture intrudes, Al corrosion is not generated because the film 203 is not formed under the pad 204.

Description

【発明の詳細な説明】 本発明は、層間絶縁膜にＰＳＧを用いる半導体装置に関
する。半導体装置（以下ＩＣと略）の層間絶縁膜は、以
前からＰＳＧを用いることが多い・これはＰＳＧに含ま
れるリンが半導体が特性上嫌う、可動イオン等のゲッタ
リング効果をもつこと、手軽知かつ安価に形成出来るこ
と、シリコーン基板との舎外が良いなどの理由からであ
る。ところが、ＰＳＧはリンを含んでいるため、非常に
吸湿性であり、吸湿した時は、リン酸が出来て、これが
工Ｃの配線層として用いられているｈｎを腐食すること
がある。そのため、ＰＳＧに外部からの水の侵入を防ぐ
ために、パッシベーション膜を形成している。ところが
、チップにダイソングされた時、チップ端からの水の侵
入によりＡ２腐食を起こす場合があり、この時は、スク
ライブライン周辺のＡＩ！、（主にボンディングバンド
の腐食が顕著である。これについて従来例第１図をもっ
て説明する。シリコン基板１０１上に、熱酸化膜１０２
が形成され、ＰＳＧ膜１０３が層間絶縁膜として形成さ
れたのち、Ａ２ポンディングパッド１０４を設け、パッ
シベーション膜１０６を形成する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device using PSG as an interlayer insulating film. The interlayer insulating film of semiconductor devices (hereinafter abbreviated as IC) has often used PSG for a long time.This is because the phosphorus contained in PSG has a gettering effect on mobile ions, etc., which semiconductors dislike due to their characteristics. This is because it can be formed at a low cost and can be used outside the building with a silicone substrate. However, since PSG contains phosphorus, it is highly hygroscopic, and when it absorbs moisture, it produces phosphoric acid, which can corrode the hn used as the wiring layer of the engineering C. Therefore, a passivation film is formed in the PSG to prevent water from entering from the outside. However, when the chip is die-sung, A2 corrosion may occur due to water entering from the end of the chip. , (Corrosion of the bonding band is remarkable. This will be explained with reference to FIG. 1 of the conventional example. A thermal oxide film 102 is
After the PSG film 103 is formed as an interlayer insulating film, an A2 bonding pad 104 is provided and a passivation film 106 is formed.

ここでスクライブライン１０５は、熱酸化膜１０２及び
ＰＳＧ膜１０３の形成されていない領域である。さて、
このような膜構成をもって工Ｃをダイソングすると、ス
クライブライン上の切れ口では上記パッシベーション膜
１０６の一部がかける。Here, the scribe line 105 is an area where the thermal oxide film 102 and the PSG film 103 are not formed. Now,
When process C is die-sung with such a film configuration, a portion of the passivation film 106 is covered at the cut end on the scribe line.

そこで、矢印で示した経路によりスクライブラインに沿
って水分が侵入していく。このときスクライブラインの
際に吸湿性の、Ｐ　Ｓ　Ｇ膜１０３が存在しているため
侵入してきた水分はＰＳＧ膜１０３に吸収されていき、
水との反応によって生じたリン酸によりボンディングバ
ンド１０４が腐食される。本発明は、かかる欠点をのぞ
くものであり、第２図に実施例を示す。Therefore, moisture enters along the scribe line along the path shown by the arrow. At this time, since the hygroscopic PSG film 103 is present at the scribe line, the invading moisture is absorbed by the PSG film 103.
The bonding band 104 is corroded by the phosphoric acid generated by the reaction with water. The present invention eliminates this drawback, and an embodiment thereof is shown in FIG.

シリコン基板２０１上に素子分離用熱酸化膜２０２を形
成後、層間絶縁膜２０６を堆積後エツチング形成する。After forming a thermal oxide film 202 for element isolation on a silicon substrate 201, an interlayer insulating film 206 is deposited and etched.

ここで、ポンディングパッド２０４領域よりスクライブ
ライン側（外側）は、この時ＰＳＧ膜２０３をエツチン
グ除去していく。At this time, the PSG film 203 on the scribe line side (outside) of the bonding pad 204 area is removed by etching.

次にパッシベーション膜２０５を形成する０この工Ｃを
ダイシングすると、従来例と同じように、パッシベーシ
ョン膜２０５の一部がスクライブラインのダイシング端
でかける。これによって、矢印で示した経路により水分
の侵入が考えられる。Next, when this process C for forming the passivation film 205 is diced, a part of the passivation film 205 is cut off at the dicing end of the scribe line, as in the conventional example. As a result, moisture can enter through the path indicated by the arrow.

ところが、吸湿性のＰＳＧ膜２０３がＡＲポンディング
パッド２０４のスクライブライン側に存在していないた
め、水分を吸湿しにくい。万一、水分の侵入が起きても
Ａ℃ポンディングパッド２０４下にＰＳＧ膜２０３が形
成されていないためＡＡ腐食は起きにくい。However, since the hygroscopic PSG film 203 is not present on the scribe line side of the AR bonding pad 204, it is difficult to absorb moisture. Even if moisture intrusion occurs, AA corrosion is unlikely to occur because the PSG film 203 is not formed under the A° C. bonding pad 204.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図・・・従来のパッド周辺の断面図第２図・・・本
発明のパッド周辺の断面図１０３．２０５がＰＳＧ膜、
１０４，２０４がＡ℃配線層。 以　上 出願人　株式会社諏訪精工舎　− さ 代理人　弁理士　最上　務ノ′Fig. 1: Cross-sectional view around the conventional pad Fig. 2: Cross-sectional view around the pad of the present invention 103.205 shows the PSG film,
104 and 204 are A°C wiring layers. Applicant Suwa Seikosha Co., Ltd. - Agent Patent Attorney Tsutomu Mogami

Claims (1)

【特許請求の範囲】[Claims] 層間絶縁膜にリンシリケートガラス（以下ＰＳＧ）を用
いる半導体装置に於いて、ボンディングバンド下には該
層間絶縁膜が形成されていないことを特徴とする半導体
装置。A semiconductor device using phosphosilicate glass (hereinafter referred to as PSG) for an interlayer insulating film, characterized in that the interlayer insulating film is not formed below a bonding band.
JP58126651A 1983-07-12 1983-07-12 Semiconductor device Pending JPS6018945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58126651A JPS6018945A (en) 1983-07-12 1983-07-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58126651A JPS6018945A (en) 1983-07-12 1983-07-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6018945A true JPS6018945A (en) 1985-01-31

Family

ID=14940481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58126651A Pending JPS6018945A (en) 1983-07-12 1983-07-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6018945A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502332A (en) * 1991-09-19 1996-03-26 Fujitsu Limited Semiconductor device having a belt cover film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502332A (en) * 1991-09-19 1996-03-26 Fujitsu Limited Semiconductor device having a belt cover film
US5580812A (en) * 1991-09-19 1996-12-03 Fujitsu Limited Semiconductor device have a belt cover film

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