JPH0366123A - Semiconductor integrated circuit device and formation thereof - Google Patents

Abstract

PURPOSE:To prevent corrosion of wiring and improve the reliability of wiring by making a laminated wiring layer, that is formed by laminating a metallic film and an aluminum film, pass through an opening that is formed at the base layer insulation film of a semiconductor board peripheral part, and connecting the above wiring to the principal surface of the semiconductor board after interposing the metallic film between the laminated films. CONSTITUTION:The same ground potential as that of a p<-> type well region 3 is supplied to an n<-> type well region 2. A PtSi film 14 is provided on respective principal surfaces of a p<-> type semiconductor region 10 and the n<-> type well region 2 which are exposed in an opening 13 at a peripheral part, and the PtSi film 14 is covered with a laminated wiring layer 15. Consequently, in a cleaning process after patterning is performed by dry etching on the laminated wiring layer, no aluminum nor PtSi films 15a and 14 in the laminated wiring layer 15 is exposed in the same water solution and then, the aluminum film 15b in the above layer 15 does not suffer corrosion under battery action. Then discontinuity and the like of the laminated wiring 15 is prevented and the reliability of wiring in a semiconductor IC device is thus improved.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is particularly applicable to a semiconductor integrated circuit device having a guard ring portion and a scribe region at the outer edge of a semiconductor substrate. It's about technology.

- [Prior Art] As semiconductor integrated circuit devices become more highly integrated, the wiring width of aluminum wiring that connects elements is becoming narrower. When the wiring width of this aluminum wiring becomes thinner, the size of aluminum crystal grains becomes close to or larger than the wiring width of the aluminum wiring, so the crystal grain boundaries cross in the width direction of the aluminum wiring, and this aluminum wiring is caused by stress migration. The wire breaks. Therefore, the aluminum wiring is coated with a metal film such as TiW (titanium tungsten) that suppresses the growth of aluminum crystal grains between the aluminum wiring and the interlayer insulating film underlying the aluminum wiring to prevent wire breakage due to stress migration of the aluminum wiring. A method is proposed.

However, since the TiW film has a large work function difference with the semiconductor region (particularly the p-type semiconductor region), when the TiW film is directly interposed between the aluminum wiring and the semiconductor region,
It becomes impossible to form good ohmic contact between the aluminum wiring and the semiconductor region. Therefore, a metal film, such as a PtSi (platinum silicide) film, is interposed between the TiW film of the aluminum wiring having the above-mentioned laminated structure and the semiconductor substrate to reduce the difference in work function between the two.

On the other hand, in a semiconductor integrated circuit device (semiconductor chip) equipped with a MISFET, in the area (outer edge of the semiconductor/substrate) between the area where the bonding pad is provided on the outer periphery and the final end (scribe area), A guard ring portion is provided. This guard ring portion is composed of a semiconductor region formed on the main surface of the semiconductor substrate, the periphery of which is defined by an element isolation insulating film. This guard ring portion supplies, for example, a ground potential for the purpose of supplying a potential to the semiconductor substrate and capturing metal contaminants such as Na + ions.

The supply of the ground potential in this guard ring part was formed in the same process as the aluminum wiring connected to the semiconductor region constituting the source region or drain region of the MISFET provided in the active region inside the semiconductor substrate. This is done using aluminum wiring. This aluminum wiring has a laminated structure using the aforementioned TiW film as a base metal film.

The opening for connecting the aluminum wiring (hereinafter simply referred to as laminated wiring) that supplies this ground potential to the main surface of the semiconductor region of the guard ring portion is formed in the semiconductor region constituting the source region or drain region of the MISFET. It is formed in the same process as forming the opening for connecting. Here, as described above, a PtSi film is interposed between the laminated wiring and the semiconductor region in order to establish good ohmic contact between the two. Therefore, this Pt5i film is also formed on the main surface of the semiconductor region exposed within the opening formed in the guard ring portion.

In addition, the final end of the semiconductor substrate and the MISF inside the semiconductor substrate
Between the active region where the ET is provided, a part of the interlayer #l edge film underlying the laminated wiring is removed, and metal contaminants such as Na'' ions are removed from the final edge of the semiconductor substrate into the inside of the semiconductor substrate. The active region of the active region is blocked by an intrusion route along the interface between the interlayer insulating film and the element isolation insulating film. This removal of a part of the glabella M edge film is performed in the same step as the step of forming an opening for connecting the laminated wiring.

Furthermore, if the laminated wiring is provided in the scribe area (the area that is cut during scribing), it may cause damage to the diamond cutter used in the scribing process, such as clogging. For this reason, an empty area is provided at a predetermined interval between the scribe area and the end of the laminated wiring connected to the main surface of the semiconductor region of the guard ring portion on the scribe area side.

Also, before dry etching technology became popular,
Wet etching was used to pattern the interlayer insulating film to form openings for connecting wiring (corresponding to the aforementioned laminated wiring) to the source and drain regions of the MI 5FET.

When wet etching this interlayer 1!41 Am film, the end point of etching was determined at the time when the main surface of the semiconductor substrate was exposed. The end point of this etching is determined by exposing the aforementioned guard ring portion having a large opening area or a part of the semiconductor region in the vicinity thereof.

In this manner, in the outer edge portion of the semiconductor substrate (the guard ring portion), first, the opening formed in the glabella connective film below the laminated wiring is used to supply the ground potential and to block the intrusion route of metal contaminants. It is formed for such purposes. A ptSi film is formed on the main surface of the semiconductor region of the guard ring portion exposed in this opening. This P t S
The i film connects the laminated wiring and the main surface of the semiconductor region of the guard link portion. This laminated wiring is used to prevent damage to the diamond cutter during scribing.
The entire principal surface of the semiconductor substrate exposed in the opening is not covered, but only a portion of the exposed principal surface of the semiconductor substrate excluding the scribe region side is covered.

[Problem to be solved by the invention]

However, the inventor of the present invention discovered the following problems as a result of failure analysis of the semiconductor integrated circuit device described above.

Patterning of the laminated wiring is carried out by dry etching from wet etching 1 in order to improve pattern accuracy as the degree of integration increases.

A chlorine-based gas is used in the step of patterning the laminated wiring by dry etching. Since the chlorine in this gas remains on the sidewalls of the patterned laminated wiring even after dry etching, it is necessary to remove this chlorine through a cleaning step. In this cleaning process, the PtSi film formed on the main surface of the semiconductor substrate exposed in the opening formed at the outer edge of the semiconductor substrate and the laminated aluminum wiring are exposed to the same cleaning solution (aqueous solution). do. As a result, the aluminum wiring of the laminated structure, which has the same potential (for example, ground potential) as the PtSi film in the opening at the outer edge, becomes electrically conductive with the aqueous solution interposed therebetween. Here, when the standard electrode potential of hydrogen is O [V], the standard electrode potential of aluminum is 1.66 [V], and the standard electrode potential of PL is -1.22 [V]. That is, since the standard electrode potential difference between aluminum and pt is large, a battery action occurs between the aluminum of the laminated wiring exposed in the same aqueous solution and the platinum in the opening of the outer edge. As a result, there is a problem in that the laminated wiring, particularly the laminated wiring connected to the semiconductor region of the guard ring portion, and the aluminum wiring of the laminated wiring (internal power supply wiring) to which the same potential is applied are corroded.

An object of the present invention is to provide a technique that can prevent corrosion of wiring and improve reliability of wiring in a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) A metal film (for example, Ti) is placed on the surface of the underlying interlayer insulating film to reduce the growth of aluminum film crystal grains from the surface side.
A laminated wiring formed by laminating a W film and an aluminum film is connected between the metal film of the laminated wiring and the semiconductor substrate through an opening formed in the base interlayer insulating film at the outer edge (guard ring part) of the semiconductor substrate. Metal film that reduces the work function difference (
For example, the entire area inside the opening is connected to the main surface of the semiconductor substrate with a Pt5jRI) interposed therebetween.

(2) Forming a base layer rJJ#8 edge film over the entire main surface of the semiconductor substrate, and forming an opening in the base interlayer insulating film at the outer edge of the semiconductor substrate to form a base layer rJJ#8 edge film on the entire main surface of the semiconductor substrate. a step of exposing the semiconductor substrate; and a step of forming a metal film that reduces the work function difference between the metal film that reduces the growth of aluminum crystal grains and the semiconductor substrate on the main surface of the semiconductor substrate exposed in the opening; 2. A laminated film in which a metal film and an aluminum film are laminated from the surface side to reduce the growth of the aluminum crystal grains. forming a pattern, and improving the pattern accuracy of the laminated film by dry etching,
forming a laminated wiring that covers at least the entire area inside the opening.

0 [Function] According to the above-mentioned means (1) or (2), aluminum and Pt are not exposed in the same aqueous solution in the cleaning step for removing chlorine after dry etching, so that aluminum and Pt are Battery action no longer occurs, and corrosion of aluminum in the laminated wiring is prevented.

[Embodiments of the invention]

Embodiments of the present invention will be specifically described below with reference to the drawings.

It should be noted that throughout the explanation of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example I] A schematic configuration of a semiconductor integrated circuit device according to Example I of the present invention is as follows:
This will be explained using FIG. 2 (a plan view of main parts).

Note that FIG. 2 shows the state before each semiconductor chip 30 is separated (the state of the wafer before the scribing step).

As shown in FIG. 2, a plurality of semiconductor chips (semiconductor substrates) 30 are provided on the wafer 25. As shown in FIG. The wafer 25 and the semiconductor substrate 30 are made of, for example, single crystal silicon. A scribe region 26 (shaded region in FIG. 2) is provided between each semiconductor substrate 30. By cutting this scribe region 26 in a scribing process, each semiconductor substrate 30 is separated.

The scribe area 26 does not remain when the semiconductor integrated circuit device is completed (after the scribing process).

The semiconductor integrated circuit device of Example ① is a complementary MISFET.
It is equipped with a logic circuit consisting of.

The logic circuit composed of this complementary MISFET is provided in an active region 27 inside the semiconductor substrate 30 (in the region surrounded by the two-dot chain line in FIG. 2). This semiconductor substrate 1
A plurality of bonding pads 28 are provided around the inner active region 27 . This pounding pad 2
In the region from the region where 8 is provided to the final end (scribe region) of the semiconductor substrate 30 (outer edge portion: the region between the broken line and the final end of the semiconductor substrate 30 in FIG. 2),
A guard ring portion 12-29 is provided.

Next, the structure of the outer edge portion and the active region 27 of the semiconductor integrated circuit device of Example I will be explained with reference to FIG. 2 (a sectional view of the main part taken along line II in FIG. 2).

As shown on the left side of FIG. 1, the semiconductor integrated circuit device of Example 1 has a p-channel MISFET Qp and an n-channel MISFET Qp (not shown) in the active region 27 inside the semiconductor substrate 1.
It is equipped with FETQn, etc. Further, as shown on the right side of FIG. 1, the semiconductor integrated circuit device of the embodiment I includes a guard ring portion 29 between the region where the bonding pad 28 is arranged and the scribe region 26. .

First, the structure of the p-channel MISFET QP provided in the active region 27 inside the semiconductor substrate 1 will be explained.

As shown on the left side of FIG.
TQp is formed on the main surface of the p-type semiconductor substrate 1 within a region defined by an element isolation insulating film 4 selectively provided on the main surface of the non-active region of the semiconductor substrate 1. - Provided on the main surface of the type well region 2.

The p-channel MISFET QP includes a gate insulating film 5 provided on the main surface of the n-type well region 2, a gate electrode 6 provided on the gate insulating film 5, and a gate electrode 6 provided in self-alignment with the gate electrode 6. a pair of p-type semiconductor regions 8 constituting a source region and a drain region, and a source region provided in self-alignment with the gate electrode 6 with sidewall spacers 9 interposed on the side walls of the gate electrode 6; It is composed of a pair of P' type semiconductor regions 11 and the like that constitute a drain region.

The gate insulating film 5 is made of, for example, a silicon oxide film formed by thermally oxidizing a substrate.

The gate electrode 6 is made of, for example, a polycrystalline silicon film. The polycrystalline silicon film constituting this gate electrode 6 has
Impurities are introduced or diffused to reduce the resistance value. Around this gate electrode 6, this gate electrode 6
An insulating film 7 is provided, which is made of one silicon oxide 13-4 element formed by thermally oxidizing a polycrystalline silicon film constituting the film.

The source and drain regions are composed of a pair of p-type semiconductor regions 8 and a pair of P'-type semiconductor regions. In other words, the source region and train region are LDD (
Lightly Doped Drajn) structure.

A laminated wiring 15 is connected to the pair of P' type semiconductor regions 11 constituting the source region and drain region through an opening 13 provided in the circumferential insulating film 12. The laminated wiring 15 extends from the main surface side of the semiconductor substrate 1, for example, by T.
It is composed of a laminated film in which a jW film 15a and an aluminum film 15b are sequentially laminated.

The aluminum film 15b constituting this laminated film contains, for example, approximately 0.5 [wt%] of copper and 1,0 [wt%] f.
It is composed of an aluminum alloy film containing a high degree of silicon. The TiW film 15a has a thickness of 10%, for example.
It contains a certain amount of Ti. The TjW film 15a is provided for the purpose of reducing (reducing) the growth of crystal grains in the aluminum film 15b constituting the laminated wiring 15.

Therefore, by providing this TiW film 15a, the crystal grain size is made smaller than the wiring width of the aluminum film 15b, and since the crystal grain boundaries do not cross the wiring width direction of the aluminum film 15b, the aluminum film 15b Cutting due to stress migration can be reduced. The product Ni1l[! line! A metal, for example, a Pt5j film 14 is provided between the TiW film 15a of No. 5 and the p' type semiconductor region 11 to reduce the difference in work function between the two. This ptSi film 14 is selectively provided only on the main surface of the p' type semiconductor region 11 exposed within the opening 13.

By interposing this PtSi film 14 between the laminated wiring 15 and the p'' type semiconductor region 11, good ohmic contact is formed between the laminated wiring 15 and the p'' type half region 11. be able to.

The interlayer adhesive film 12 may be subjected to CV under high temperature and low pressure conditions, for example.
A silicon oxide film deposited by the D method, PSG (Phospho 5i1ica) deposited on top of this silicon oxide film
It is composed of a laminated film of te G 1ass) films.

The silicon oxide film constituting this interlayer insulating film 12 is made of the PS
This is provided especially for the purpose of preventing P in the G film from leaking to the main surface portion 5 16 of the p′ type semiconductor region 11 .

The PSG film constituting the interlayer rim film 12 is, for example, 80
Reflow is performed at a temperature of 0 to 900° C. to flatten the surface.

The laminated wiring 15 has an opening I7 provided in the interlayer #LfA edge film 16 provided in the upper layer of the laminated wiring 15.
The second layer wiring 18 is connected through the second layer.

The second layer wiring 18 is a laminated film having the same structure as the laminated wiring 15, although it is not limited to this structure.

The interlayer M edge film 16 is, for example, a silicon oxide film deposited by plasma CVD, an SOG (Spin On Glass) film provided on the upper layer of this silicon oxide film, and further deposited on the upper layer of this SOG film by plasma CVD. It is composed of a silicon oxide film. The silicon oxide films provided on the upper and lower layers of the SOG film are the glabella insulating film 16.
This is provided for the purpose of maintaining the mechanical strength and dielectric strength of the SOG film and reducing moisture absorption of the SOG film.

A passivation film 19 is provided on the upper layer of the second layer arrangement [18]. This passivation film 19
is mainly composed of a silicon nitride film deposited by, for example, plasma CVD.

Next, the outer edge portion of the semiconductor substrate 1, that is, the guard ring portion 2
9 and its vicinity will be explained.

As described above, the guard ring portion 29 is provided at the outer edge of the semiconductor substrate 1. This guard ring part 29
consists of a P' type semiconductor region 10 provided on the main surface of the P' type well region 3, the periphery of which is defined by an element isolation insulating film 4. Furthermore, the p-type well region 3 and the scribe region 26 (the first
An n-type well region 2 is provided between the region on the right side of the broken line in the figure.

This n-type well region 2 is, for example, a scribe region 26.
In order to insulate and separate the p-type well region 3 in which the test device is provided and the p-type well region 3 in which the guard ring portion 29 is provided when a test device is provided in the test device. It is provided.

The distance between the p-type semiconductor region 10, which is the guard ring portion 29, and the scribe region 26 is, for example, from step to step 18.
- They are separated by about 0 to 20' [μm]. A laminated wiring 15 is connected to the p' type semiconductor region 10 through an opening 13 provided in the interlayer insulating film 12.

This laminated wiring 15 is connected to the p-channel MiSFETQp
A pair of p° type semiconductor regions 1 forming source and drain regions of ! It is formed in the same process as the stacked arrangement 1*15 connected to. For example, a ground potential (for example, a circuit reference potential of 0 [V]) is applied to the laminated wiring 15 connected to the p-type semiconductor region 10. The main purpose of supplying the ground potential to the P type semiconductor region 10 is to supply the potential to the V type well region 2 and capture metal contaminants such as Na'' ions.Connected to the P type semiconductor region 1G The scribe area 26 side of the laminated wiring 15 is
In order to prevent shortening of the life of the diamond cutter due to clogging during the scribing process, it is provided apart from above the scribing area 26. The distance between the end of the laminated wiring 15 on the scribe region 26 side and the scribe region 26 is, for example, about 10 to 15 [μml].

The opening 13 for connecting the laminated wiring 15 to the p-type semiconductor region 10 also has a Na"
It is provided to prevent metal contaminants such as ions from entering the active region 27 inside the semiconductor substrate 1 from the outside of the semiconductor substrate 1 . This opening 13 is formed in the same step as the step of forming an opening 13 in the interlayer insulating film 12 for connecting the laminated wiring 15 to the p° type semiconductor region 11 constituting the source region or drain region of the p-channel MISFET QP. has been done. Therefore, on the main surface of the p' type semiconductor region 10 exposed in the 'opening 13,
Similar to the main surface of the P' type semiconductor region 11 exposed in the opening 13 provided in the region of the p-channel MISFET QP, a PtSi film 14 is formed. Also,
The opening 13 provided at the outer edge of the semiconductor substrate 1 extends not only to the main surface of the p° type semiconductor region 10 but also to the n − type well region provided between the guard ring portion 29 and the scribe region 26. A part of the main surface of No. 2 is also exposed. In other words, the "type well region 2 is supplied with the same ground potential as the p-type well region 3.

19-=20 The p° type semiconductor region 10. exposed within the opening 13 at the outer edge. On each main surface of the n-type well region 2,
A PtSi film 14 film type 4 is formed, and this PtSi film 14 film type 4 is formed.
It is covered with the laminated wiring 15. In other words, the entire area of the opening 13 at the outer edge is covered with the laminated wiring 15. Therefore, in the cleaning step 8 (chlorine removal step) after patterning the laminated wiring 15 by dry etching, the laminated wiring 15 is etched.
The aluminum film 15b of No. 5 and the PtSi film 14 are no longer exposed in the aqueous solution, and the aluminum film 15b of the laminated wiring 15 is no longer corroded by battery action, thereby preventing disconnection of the laminated wiring 15. , it is possible to improve the reliability of wiring of a semiconductor integrated circuit device.

Further, in the region between the scribe region 26 and the active region 27 inside the semiconductor substrate 1, the interlayer insulating film 1
6 is provided with an opening 17, and passivation film 19 is provided with an opening 20, respectively. The purpose of these openings 17 and 20 is to block the intrusion path of metal contaminants passing through the interfaces of the interlayer insulating film 16 and the passivation film 19, respectively.

As explained above, in the semiconductor integrated circuit device of Example I, 1. a metal film (TiW film) 15a is provided on the surface of the base interlayer insulating film 12 from the surface side to reduce the growth of crystal grains of the aluminum film 15b; The metal film (TiW film) 15a of the laminated wiring 15 and the semiconductor substrate are passed through the opening 13 formed in the base interlayer insulating film 12 at the outer edge of the semiconductor substrate 1, and the laminated wiring 15 formed by laminating the aluminum film 15b is connected to the semiconductor substrate. A metal film (PtSi film) 14 that reduces the work function difference with 1 (p type semiconductor region 1G) is interposed, and the entire area inside the opening 13 is connected to the main surface of the p ° type semiconductor region IO. There is. With this configuration, the laminated wiring 1
In the cleaning process for removing chlorine after patterning 5 by dry etching, the aluminum film 15b of the laminated wiring 15 and the main surface of the P° type semiconductor region 10 are formed in the opening 13 at the outer edge of the semiconductor substrate 1. ptS
ill14 is no longer exposed in the same aqueous solution. Therefore, no battery action occurs between aluminum and PT, and the aluminum film 15b of the laminated wiring 15 is no longer corroded. Thereby, the reliability of the wiring of the semiconductor integrated circuit device can be improved.

Next, a method for manufacturing the semiconductor integrated circuit device of Example I will be explained using FIGS. 3 to 7 (cross-sectional views of main parts shown for each manufacturing process).

First, an n-type well region 2 is selectively formed on the main surface of a p-type semiconductor substrate 1. After this, n-type well region 2
In the region where P-type semiconductor substrate 1 is not formed,
A p-type well region 3 is formed on the main surface of the substrate.

Next, the main surfaces of the non-active regions of the n-type well region 2 and the p-type well region 3 are selectively oxidized to form an insulating film 4 corresponding to the amount of silicon oxide.

Next, in the active region defined by this inter-element isolation insulating film 4, the main surfaces of each of the n- type well region 2 and the p-type well region 3 are exposed. After this, by thermal oxidation,
As shown in the third figure, the exposed n-type well region 2. A D1-M edge film 5 is formed on each main surface of the p-type well region 3.

Next, a conductive film, such as a polycrystalline silicon film 6, is deposited over the entire surface of the semiconductor substrate 1 by CVD. Thereafter, this polycrystalline silicon film 6 is patterned by photolithography to form a gate electrode 6.

Thereafter, by thermally oxidizing the polycrystalline silicon film constituting the gate electrode 6, an insulating film 7 made of a silicon oxide film is formed around the gate electrode 6.

Next, in the region where the p-channel MISFET QP is to be formed, a p-type impurity such as B is ion-implanted by ion implantation, mainly using the gel 1 to the electrode 6 and the insulating film 7 as a mask.
- type well region 2, p-channel MIS
A pair of p-type semiconductor regions 8 forming the source region and drain region of FETQP are formed. Therefore, the pair of p-type semiconductor regions 8 are formed in self-alignment with the gate electrode 6.

Next, a silicon oxide film, for example, is coated on the entire surface of the semiconductor JK board 1.
Deposited by VD method. Thereafter, this silicon oxide film is etched by an anisotropic etching process by an amount corresponding to the thickness of the deposited film, and sidewall spacers 9 are formed on the side walls of the gate electrode 6.

Next, as shown in FIG.
In the region where p-channel MISFET Qp is formed, a p-type impurity, such as B, is introduced into the main surface of the n-type well region 2 by ion implantation, mainly using the gate electrode 6 and the sidewall spacer 9 as a mask, and the source of the p-channel MISFET Qp is A pair of p' type semiconductor regions 11 constituting a region and a drain region are formed. Therefore, this p° type semiconductor region 11 is formed in self-alignment with the gate electrode 6 with the sidewall spacer 9O interposed therebetween.

In this way, the source region and drain region of the P-channel MISFET Qp are composed of the pair of p-type semiconductor regions 8 and the pair of p-type semiconductor regions 11, and have an LDD structure.

Also, at the same time in this step, a guard ring portion 29 is formed on the main surface of the P-type well region 3 at the outer edge of the semiconductor substrate 1.
A p-type semiconductor region 10 is formed.

Next, a silicon oxide film is deposited over the entire surface of the semiconductor substrate 1 by the CVD method under, for example, high temperature and low pressure conditions. After this,
For example, a PSG film is deposited on top of this silicon oxide film to form an interlayer insulating film 12.

Next, as shown in FIG. 5, the interlayer #! ! The A edge film 12 is patterned to form openings 13. During this time, by forming the RoE 3, one of the main surfaces of the p'-type semiconductor region 11 constituting the source region or drain region of the P-channel MISFET Qp and the main surface of the n-type well region 2 at the outer edge of the semiconductor substrate 1 is formed. and a guard ring portion 2 at the outer edge of the semiconductor substrate 1.
Each of the main surfaces of the P' type semiconductor region lO constituting S is exposed.

Next, in order to form on the entire surface of the semiconductor substrate 1 a metal film that reduces the contact resistance between the metal film that reduces the growth of aluminum crystal grains and each of the P' type semiconductor regions 10 and 11, for example. A PT film is deposited by sputtering.

This Pt film is deposited to a thickness of, for example, about 25 nm1. Thereafter, by performing heat treatment for about 10 minutes at a temperature of about 475 [:°C] in an oxygen atmosphere, the main surfaces of each of the p-type semiconductor regions 1O111 exposed in the openings 13 are heated. is selectively silicided to form a Pt5i film 14. Thereafter, the PT film remaining on the interlayer insulating film 12 is removed by a hot aqua regia treatment for about 15 minutes at a temperature of, for example, 50°C, thereby forming the opening 13 as shown in FIG. Close-up semiconductor region 1O111 exposed inside
The PtSi film 14 is selectively left only on each main surface.

Next, a metal film that reduces the growth of aluminum crystal grains, such as a TiW film 15a, is deposited over the entire surface of the substrate by sputtering. This TiW film 15a has a thickness of, for example, 200
Deposit to a film thickness of about [nm:l].

Next, on the entire surface of the semiconductor substrate 1, this TiW I
For example, an aluminum film 15b is deposited on the I 15 a by sputtering to form a laminated film 15. This aluminum film 15b has a thickness of, for example, 500 [n
It is deposited to a film thickness of about ml. In this way, by providing the TiW film 15a as the underlying metal film of the aluminum film 15b, the growth of aluminum crystal grains is reduced, so that disconnection due to stress migration of the aluminum film 15b can be reduced. After this, the seventh
As shown in the figure, the laminated wiring 15 is patterned by photolithography to form the laminated wiring 15. Patterning of the laminated wiring 15 is performed by dry etching using chlorine gas. This laminated wiring 15
As shown in FIG. 7, the p-channel MISFETQ
It is connected through the opening 13 to the main surface of the p-type semiconductor region 11 constituting the p source or drain region, and is connected to the main surface of the p-type semiconductor region 10 and the n- It is connected to a part of the main surface of the mold well region 2 through the opening 13 .

For example, a ground potential is supplied to the laminated wiring 15 connected to the main surface of this p' type semiconductor region 10, and this p' type semiconductor region 10 constitutes a guard ring portion 29.

Next, a silicon oxide film is deposited over the entire surface of the semiconductor substrate 1 by, for example, plasma CVD. Thereafter, an SOG film, for example, is deposited on top of this silicon oxide film. After this, this S
A silicon oxide film is deposited on the OG film by, for example, a 27-28 degree plasma CVD method to form an interlayer insulating film 16. Thereafter, an opening 17 is formed in this interlayer insulating film 16 by photolithography. This opening 17 is for connecting the second layer of laminated wiring (18) to the laminated arrangement 15, and is also formed at the outer edge of the semiconductor substrate 1 to block the intrusion route of metal contaminants. do.

Next, a laminated wiring 18 is formed on the entire surface of the semiconductor substrate 1 by the same process as that for the laminated wiring 15.

Next, for example, a plasma CV
A silicon nitride film is deposited by the D method to form a passivation film 1.
form 9. Thereafter, this passivation film 19 is patterned by photolithography to form an opening 20. By forming this opening 20, the bonding pad 28 is exposed. Further, in order to block the intrusion route of the metal contaminants mentioned above, an opening 20 is formed in the passivation film 19 at the outer edge of the semiconductor substrate 1, similarly to the interlayer insulating films 12 and 16.

By sequentially performing these series of steps, the first
The semiconductor integrated circuit device of Example 2 shown in the figure is completed.

As explained above, the semiconductor integrated circuit device of Example 2 includes the step of forming the base interlayer insulating film 12 on the entire main surface of the semiconductor substrate 1, and the step of forming the base interlayer insulating film 12 on the outer edge of the semiconductor substrate 1. forming an opening 13 in the opening 13 to expose the main surface of the semiconductor substrate 1; and forming a metal film (TiW) on the main surface of the semiconductor substrate 1 exposed in the opening 13 to reduce the growth of aluminum crystal grains. Step of forming a metal film (PtSi film) 14 that reduces the work function difference between the film) 15a and the semiconductor substrate 1, and reduces the work function difference formed on the main surface of the semiconductor substrate 1 within the opening 13. Metal film (PtSi film) 1
Step 4 of forming a laminated film 15 on the entire surface of the base insulating film 12, including a metal film (TiW film) 15a and an aluminum film 15b, which reduce the growth of the aluminum crystal grains, from the surface side. and a step of patterning the laminated film 15 by dry etching to form a laminated wiring 15 covering at least the entire area inside the opening 13. With this configuration, in the cleaning step for removing chlorine after patterning the laminated film 15 with dry etching, the aluminum film 15a and the ptSi film 14 are not exposed to the film chamber 4 in the same aqueous solution. Battery action with PT no longer occurs, and corrosion of the aluminum of the laminated wiring 15 is prevented. Thereby, the reliability of the wiring of the semiconductor integrated circuit device can be improved.

[Embodiment 2] Next, a schematic configuration of a semiconductor integrated circuit device according to Embodiment 2 of the present invention will be described with reference to FIG. 8 (cross-sectional view of main parts).

As shown in FIG. 8, the semiconductor integrated circuit device of Example (2) has an opening 13 formed in the interlayer insulating film 12 at the outer edge of the semiconductor substrate in the semiconductor integrated circuit device of Example (2).
The main surfaces of the p° type semiconductor region 10 (guard ring portion 29) and the n− type well region 2 exposed within the opening 13 are entirely covered with the laminated wiring 15.

As explained above, the semiconductor integrated circuit device of Example (2) can achieve the same effects as the semiconductor integrated circuit device of Example (2).

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

To briefly explain the effects obtained by the representative inventions disclosed in this application, they are as follows: In a semiconductor integrated circuit device, the reliability of wiring is improved by preventing corrosion of the aluminum film. can do.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a sectional view of a main part showing a schematic configuration of a semiconductor integrated circuit device according to Embodiment 2 of the present invention, and FIG. 2 is a schematic configuration of the semiconductor integrated circuit device before a scribing process. 3 to 7 are sectional views of essential parts showing each manufacturing process of the semiconductor integrated circuit device, and 31-2 FIG. FIG. 2 is a cross-sectional view of main parts showing a schematic configuration of the device. In the figure, 1...p-type semiconductor substrate, 2...n-type well region, 3...p-type well region, 4. element isolation insulating film, 5... gate insulating film, 6...・Gate electrode, 8・
... p-type semiconductor region, 10.11 ... p-type semiconductor region, 12.16 ... interlayer insulating film, 13 ... opening, 1
4...PtSi film, 15... Laminated wiring, 15a...
-TiW film, 15b...aluminum film, 26...scribe region, 29...guard ring part.

Claims (1)

[Claims] 1. Laminated wiring formed by laminating a metal film and an aluminum film that reduce the growth of crystal grains of the aluminum film from the surface side on the surface of the underlying interlayer insulating film is connected to the outer edge of the semiconductor substrate. connection to the main surface of the semiconductor substrate through the opening formed in the base interlayer insulating film in the opening, with a metal film interposed therebetween that reduces the work function difference between the metal film of the laminated wiring and the semiconductor substrate, and connecting to the main surface of the semiconductor substrate throughout the opening. A semiconductor integrated circuit device characterized by: 2. A ground potential is applied to the laminated wiring connected to the main surface of the semiconductor substrate within an opening formed in a base interlayer insulating film at an outer edge of the semiconductor substrate. semiconductor integrated circuit devices. 3. forming a base interlayer insulating film over the entire main surface of the semiconductor substrate; forming an opening in the base interlayer insulating film at the outer edge of the semiconductor substrate to expose the main surface of the semiconductor substrate; forming, on the main surface of the semiconductor substrate exposed in the opening, a metal film that reduces the work function difference between the metal film that reduces the growth of aluminum crystal grains and the semiconductor substrate;
Forming a laminated film in which a metal film that suppresses the growth of the aluminum crystal grains and an aluminum film are laminated from the surface side on the entire surface of the base interlayer insulating film, including the metal film that reduces the work function difference. A method for forming a semiconductor integrated circuit device, comprising the steps of: patterning the laminated film by dry etching to form a laminated wiring covering at least the entire area within the opening.