JPS60187047A - Manufacture of thick film circuit board - Google Patents
Manufacture of thick film circuit boardInfo
- Publication number
- JPS60187047A JPS60187047A JP4342284A JP4342284A JPS60187047A JP S60187047 A JPS60187047 A JP S60187047A JP 4342284 A JP4342284 A JP 4342284A JP 4342284 A JP4342284 A JP 4342284A JP S60187047 A JPS60187047 A JP S60187047A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- thick film
- layer
- board
- film circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000919 ceramic Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000007772 electroless plating Methods 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000007747 plating Methods 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 26
- 230000004913 activation Effects 0.000 claims description 10
- 238000005553 drilling Methods 0.000 claims 1
- 241000711981 Sais Species 0.000 abstract 1
- 238000005245 sintering Methods 0.000 abstract 1
- 238000001994 activation Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010419 fine particle Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- TXUICONDJPYNPY-UHFFFAOYSA-N (1,10,13-trimethyl-3-oxo-4,5,6,7,8,9,11,12,14,15,16,17-dodecahydrocyclopenta[a]phenanthren-17-yl) heptanoate Chemical compound C1CC2CC(=O)C=C(C)C2(C)C2C1C1CCC(OC(=O)CCCCCC)C1(C)CC2 TXUICONDJPYNPY-UHFFFAOYSA-N 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 244000062175 Fittonia argyroneura Species 0.000 description 1
- 239000005062 Polybutadiene Substances 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910021626 Tin(II) chloride Inorganic materials 0.000 description 1
- IHWJXGQYRBHUIF-UHFFFAOYSA-N [Ag].[Pt] Chemical compound [Ag].[Pt] IHWJXGQYRBHUIF-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920002857 polybutadiene Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 229910052705 radium Inorganic materials 0.000 description 1
- 239000005060 rubber Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000001119 stannous chloride Substances 0.000 description 1
- 235000011150 stannous chloride Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はテレビジョン受像機やビデオテープレコーダな
どの一般電子機器に用いられる厚膜回路基板の製造方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing thick film circuit boards used in general electronic equipment such as television receivers and video tape recorders.
従来例の構成とその問題点
近年、電子機器の１軽薄短小」化や高性能化をはかるこ
とを目的として、それらの電子回路の構成に厚膜回路基
板を用いた混成集積回路モジュールが多く使用されるよ
うになってきた。このモジュールにつかわれる回路基板
としてはフェノール樹脂やエポキシ樹脂などから成る合
成樹脂基板が使われているがこれらの回路基板では十分
な特性が得られず従って厚膜回路基板の多くは、アルミ
ナなどのセラミック基板の表面に主として銀−ノζラジ
ウム系の金属により導体回路を構成し、その同一面上に
酸化ルテニウム系の材料により抵抗体を構成したもので
あるが、昨今はモジュールの小型高密度化をはかること
を狙いとしてセラミック絶縁基板の表裏両面を利用して
回路導体層と抵抗体層を形成し、表裏の配線回路をアル
ミナ基板にあけた貫通孔に導体層を形成することにより
接続したものである。Conventional configurations and their problems In recent years, with the aim of making electronic devices lighter, thinner, shorter, and more compact, and improving their performance, hybrid integrated circuit modules that use thick-film circuit boards have been increasingly used in the configuration of electronic circuits. It has started to be done. The circuit boards used in this module are synthetic resin boards made of phenol resin, epoxy resin, etc., but these circuit boards do not have sufficient characteristics, and therefore many thick film circuit boards are made of ceramics such as alumina. A conductor circuit is constructed on the surface of the substrate mainly using a silver-no-radium metal, and a resistor is constructed on the same surface using a ruthenium oxide-based material, but in recent years, modules have become smaller and more dense. A circuit conductor layer and a resistor layer are formed using both the front and back sides of a ceramic insulating substrate, and the wiring circuits on the front and back are connected by forming a conductor layer in a through hole drilled in the alumina substrate. be.
このような両面厚膜回路基板は一般に第１図Ａ〜Ｄに示
す製造工程を経て作られている。Such double-sided thick film circuit boards are generally manufactured through the manufacturing steps shown in FIGS. 1A to 1D.
すなわち、第１図Ａに示すようにセラミック絶縁基板１
に貫通孔２をあけ、次いで第１図Ｂに示すようにセラミ
ック絶縁基板１０表裏両面に銀−パラジウムなどの貴金
属粉末をガラスフリットと樹脂バインダーで混合した導
体ペーストをそれぞれ配線回路状に塗布するとともに、
貫通孔２の中にもこの導体ペーストを充填して高温焼成
することによシ回路導体層３，３′を形成し、さらに第
１図Ｃに示すように回路導体層の一方の面に酸化ルテニ
ウムから成るグレーズ系の抵抗ペーストを塗布し、高温
焼成することによシ抵抗層４を形成し、しかる後に第１
図りに示すように抵抗層４と回路導体層３，３′の一部
にガラス絶縁ペーストを塗布して絶縁体層６，６′それ
ぞれ形成する工程を経て作られたものである。That is, as shown in FIG. 1A, a ceramic insulating substrate 1
A through hole 2 is made in the ceramic insulating substrate 10, and as shown in FIG. ,
The through hole 2 is also filled with this conductor paste and fired at high temperature to form the circuit conductor layers 3, 3', and as shown in FIG. 1C, one surface of the circuit conductor layer is oxidized. A glaze-based resistance paste made of ruthenium is applied and fired at a high temperature to form a resistance layer 4, and then the first
As shown in the figure, it is made through a process of applying glass insulation paste to a portion of the resistance layer 4 and circuit conductor layers 3, 3' to form insulator layers 6, 6', respectively.
ところがこのような製造方法による厚膜回路基板では、
セラミック絶縁基板に設け／＋１．貫通孔内に導体ペー
ストをスクリーン印刷法により充填するが、この方法で
は貫通孔へ確実に導体ペーストを充すことが極めて困難
であるためその修正作業に大きな労力を要し、かつ接続
が不安定になりやすいことからスルーホール接続の信頼
性が乏しいという欠点があった。However, with thick film circuit boards produced using this manufacturing method,
Provided on ceramic insulating substrate/+1. The through-holes are filled with conductive paste by screen printing, but with this method it is extremely difficult to reliably fill the through-holes with conductive paste, which requires a great deal of effort to correct, and the connection is unstable. This has the disadvantage that the reliability of through-hole connections is poor because it is easy to cause damage.
また一方、このような方法により得られる厚膜回路基板
では、その導体材料に主として銀−パラジウムを使わな
ければならないが、これらの貴金属材料は極めて高価に
つくとともに、銀糸導体材料特有の問題点として、この
厚膜回路基板を使ってモジュールを構成してゆくだめの
はんだづけ工程でいわゆ２銀が溶融したはんだに喰われ
るいわゆる銀喰われ不良や、湿中負荷による銀導体のマ
イグレーションが起り、回路導体間の短絡不良が発生し
やすいなどの欠点があった。On the other hand, thick film circuit boards obtained by this method must mainly use silver-palladium as the conductor material, but these precious metal materials are extremely expensive and have problems specific to silver thread conductor materials. During the soldering process used to construct modules using this thick-film circuit board, so-called silver-eaten defects, where so-called silver is eaten away by molten solder, and migration of silver conductors due to humid loads occur, causing circuit damage. There were drawbacks such as short-circuit failure between conductors.
発明の目的
本発明の目的は、前記欠点に鑑み、スルーホール接続が
確実にできてその接続の信頼性が極めてすぐれ、かつ回
路導体層の特性にもすぐれた厚膜回路基板の製造方法を
提供することである。OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, an object of the present invention is to provide a method for manufacturing a thick film circuit board that can reliably connect through holes, has extremely high reliability of the connection, and has excellent characteristics of the circuit conductor layer. It is to be.
発明の構成
前記目的を達成するだめに本発明は、セラミック絶縁基
板の所定の位置に貫通孔をあけて活性化処理を行い、こ
のセラミック絶縁基板の表裏両面に所望の回路図形状に
グレーズ系の導電ペーストと、必要により少くともその
一方の主面上にグレーズ系の抵抗体ペーストを塗布し、
高温焼成することにより、導体層と、抵抗体層をそれぞ
れ形成する工程、貫通孔と導体層の一部分が露出するよ
うに他の面に耐めっき性を有する絶縁性レジスト層を形
成する工程、露出した貫通孔内壁部と回路導体層の一部
に無電解めっき法により導電金属層を形成する工程を経
て作るものである。Structure of the Invention In order to achieve the above-mentioned object, the present invention involves forming through holes at predetermined positions in a ceramic insulating substrate, performing an activation process, and applying a glaze to the desired circuit diagram shape on both the front and back surfaces of the ceramic insulating substrate. Apply a glaze-based resistor paste to the conductive paste and, if necessary, at least one main surface of the conductive paste.
A step of forming a conductor layer and a resistor layer by high-temperature firing, a step of forming an insulating resist layer with plating resistance on the other surface so that the through hole and a part of the conductor layer are exposed, and an exposure step. The conductive metal layer is formed by electroless plating on the inner wall of the through hole and a part of the circuit conductor layer.
実施例の説明
以下本発明の一実施例について図面を参照しながら説明
する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
第２図Ａ−Ｆは本発明の一実施例における厚膜回路基板
の製造方法を説明するための主要製造工程図である。FIGS. 2A to 2F are main manufacturing process diagrams for explaining a method for manufacturing a thick film circuit board according to an embodiment of the present invention.
第２図において、６はセラミック絶縁基板、７は貫通孔
、８は活性化層、９，９′は厚ｎ々回路導体層１０は厚
膜抵抗体層、１１．１１’は絶縁レジスト層、１２は導
電金属層である。In FIG. 2, 6 is a ceramic insulating substrate, 7 is a through hole, 8 is an activation layer, 9 and 9' are n-thick circuit conductor layers, 10 is a thick film resistor layer, 11 and 11' are insulating resist layers, 12 is a conductive metal layer.
以上のように構成された厚膜回路基板について以下その
実施例を詳細に述べることにする。Examples of the thick film circuit board constructed as described above will be described in detail below.
本実施例による厚膜回路基板は先づ第２図Ａに示すよう
に、アルミナなどのセラミック絶縁基板６の必要個所に
レーザーや、アルミナを生シートの状態で金型を用いて
貫通孔７をあけ高温焼成したセラミック絶縁基板を用い
て、これを塩化第１スズと、塩化パラジウムの塩酸酸性
溶液に順次浸漬することにより、第２図Ｂに示すように
貫通孔γを含むセラミック絶縁基板の全面に金属パラジ
ウムの微粒子核から成る活性化層８を付着した。In the thick film circuit board according to this embodiment, as shown in FIG. 2A, through-holes 7 are first formed in the required locations of a ceramic insulating substrate 6 made of alumina or the like using a laser or a mold using a raw sheet of alumina. By using a ceramic insulating substrate that has been fired at a high temperature and immersing it in an acidic hydrochloric acid solution of stannous chloride and palladium chloride, the entire surface of the ceramic insulating substrate including the through holes γ is formed as shown in FIG. 2B. An activation layer 8 consisting of fine particle nuclei of metallic palladium was deposited on the substrate.
そして、第２図Ｃに示すように、活性処理を施こしたセ
ラミック絶縁基板６の表裏両面に銅、銀。Then, as shown in FIG. 2C, copper and silver are applied to both the front and back surfaces of the activated ceramic insulating substrate 6.
銀−白金、銀−パラジウムの微粉末をガラスフリソトと
樹脂バインダーに混合してペースト状とした導電ペース
トを用いてスクリーン印刷法によシ所望の配線回路図形
状にそれぞれ塗布し、ＳＯＯ〜８６０℃の高温で焼成す
ることにより厚膜回路導体層９，９′を形成した。A conductive paste made by mixing fine powders of silver-platinum and silver-palladium with a glass frit and a resin binder was applied to the desired wiring circuit shape using a screen printing method, and then printed at SOO~860°C. Thick film circuit conductor layers 9 and 9' were formed by firing at a high temperature.
この場合、導電ペーストを高温焼成する際、活性化処理
により付着した金属パラジウムの微粒子核から成る活性
化層８は何ら影響なく、むしろ熱処理によりセラミック
絶縁基板６との密着性が向することが明らかとなった。In this case, it is clear that when the conductive paste is fired at a high temperature, the activation layer 8 consisting of fine particle nuclei of metallic palladium adhered by the activation treatment is not affected at all, and on the contrary, the adhesion with the ceramic insulating substrate 6 is improved by the heat treatment. It became.
次に、第２図りに示すように、厚膜回路導体層９．９′
を形成したセラミック絶縁基板６の少くとも一方の面に
、酸化ルテニウムをガラス７リツトと樹脂バインダーで
混合した抵抗ペーストをスクリーン印刷法により塗布し
、これをＳＯＯ〜８５０℃の高温焼成することにより厚
膜抵抗体層１０を形成した。Next, as shown in the second diagram, the thick film circuit conductor layer 9.9'
A resistive paste made by mixing ruthenium oxide with 7 liters of glass and a resin binder is applied to at least one surface of the ceramic insulating substrate 6 on which a resistor paste is formed using a screen printing method. A film resistor layer 10 was formed.
この場合、厚膜抵抗体層の下面には金属パラジウムの微
粒子核から成る活性化層８が残存しているがこれによる
抵抗体への影響は特にない。また厚膜抵抗体１０は、そ
の抵抗値の調整をレーザートリミング技術を利用して行
った。このようにして、セラミック絶縁基板６の表裏両
面に厚膜回路導体層９，９′と、一方の面に厚膜抵抗体
層１゜を形成したものを、第２図Ｅに示すように、貫通
孔７とその周辺部の厚膜回路導体層９，９′の一部が露
出するように、絶縁性レジスト１１，１１′をセラミッ
ク絶縁基板の表裏両面にスクリーン印刷法によってそれ
ぞれ塗布乾燥した後で、この基板を無電解めっき液に浸
漬し、第２図下に示すように、貫通孔７の内壁面とその
周辺部に露出した厚膜回路導体層面９，９′に導電金属
層１２を析出させることにより、セラミック絶縁基板６
０表裏面に形成した厚膜回路導体層９，９′を貫通孔７
を通して電気的に接続したいわゆる両面厚膜回路基板を
作った。In this case, the activation layer 8 made of fine particle nuclei of metallic palladium remains on the lower surface of the thick film resistor layer, but this has no particular effect on the resistor. Further, the resistance value of the thick film resistor 10 was adjusted using laser trimming technology. In this way, a ceramic insulating substrate 6 with thick film circuit conductor layers 9 and 9' formed on both sides and a thick film resistor layer 1° formed on one side is formed as shown in FIG. 2E. Insulating resists 11 and 11' are applied and dried on both the front and back surfaces of the ceramic insulating substrate by a screen printing method, respectively, so that the through hole 7 and parts of the thick film circuit conductor layers 9 and 9' in the vicinity thereof are exposed. Then, this board is immersed in an electroless plating solution, and as shown in the lower part of FIG. By depositing the ceramic insulating substrate 6
Thick film circuit conductor layers 9 and 9' formed on the front and back surfaces of
We created a so-called double-sided thick film circuit board with electrical connections through it.
なお、第２図Ｅの工程で使用する絶縁レジスト１１．１
１’ としては耐薬品性を有し、無電解めっきに対して
十分に耐えることが必要であるが、その他に厚膜抵抗体
層１０に悪影響をおよＩ！さないことが必要不可欠であ
るが、このような目的に合致する絶縁レジタ）１１．１
１’ として本実施例では、エポキシ樹脂やアクリル樹
脂、シリコン樹脂、環化ゴム系ポリブタジェン樹脂など
の有機系材料の他にガラスなどの無機質系の材料も使用
した。また−１方、この工程で使用する絶縁レジスト１
１として他の実施例では、無電解めっき後に容易にはく
離除去ができる性質のレジスト材料を用いた。そして無
電解めっき後にレジスト１１を除去してから厚膜抵抗体
層１０の抵抗値をレーザートリミング法で行ない、最終
的に樹脂系の永久絶縁レジタ、ト層を形成した。無電解
めっきについては、本実施例ではニッケルと銅の無電解
めっきさらにはニッケルと銅の２層のめっきを行なった
が、いずれの導電金属層１２も厚膜回路導体層９゜９′
と一貫通孔内壁面の活性化層８との密着性は極めて良好
であった。Note that the insulation resist 11.1 used in the process shown in FIG.
1', it is necessary to have chemical resistance and sufficiently withstand electroless plating, but in addition, I! 11.1 (Insulated resistors that meet this purpose)
1', in this example, in addition to organic materials such as epoxy resin, acrylic resin, silicone resin, and cyclized rubber-based polybutadiene resin, inorganic materials such as glass were also used. On the other hand, the insulation resist 1 used in this process
In another example as No. 1, a resist material having a property that can be easily peeled off and removed after electroless plating was used. After electroless plating, the resist 11 was removed and the resistance value of the thick film resistor layer 10 was trimmed by a laser trimming method to finally form a resin-based permanent insulating resistor layer. Regarding electroless plating, in this example, electroless plating of nickel and copper and further plating of two layers of nickel and copper were performed, but both conductive metal layers 12 were formed by thick film circuit conductor layer 9°9'.
The adhesion between the activated layer 8 and the inner wall surface of the continuous hole was extremely good.
なお、本実施例においては、パラジウムの微粒子核から
成る活性化層８は全てセラミック絶縁基板上に最後まで
残存するが、たとえ活性化層８が残存しても、その絶縁
特性には何ら影響ないことが確認できた。In this example, all of the activation layer 8 made of palladium particle nuclei remains on the ceramic insulating substrate until the end, but even if the activation layer 8 remains, it has no effect on its insulation properties. This was confirmed.
発明の効果
以上の説明から明らかなように、本発明による厚膜回路
基板は、セラミック絶縁基板に貫通孔をあけ、活性化処
理を行ってから、セラミック絶縁基板の表裏両面に厚膜
回路導体層と一方の面に厚膜抵抗体層を形成し、必要な
部分に耐無電解めっき性のレジスト層を形成した後で無
電解めっきを行うことにより、貫通孔内壁面と厚膜回路
導体層の一部に導電金属層を析出させる方法により作ら
れたものである。Effects of the Invention As is clear from the above explanation, the thick film circuit board according to the present invention is provided by forming a through hole in a ceramic insulating substrate, performing an activation treatment, and then forming a thick film circuit conductor layer on both the front and back surfaces of the ceramic insulating substrate. By forming a thick film resistor layer on one side and forming a resist layer with resistance to electroless plating on the necessary parts, electroless plating is performed to form a thick film resistor layer on the inner wall surface of the through hole and the thick film circuit conductor layer. It is made by depositing a conductive metal layer on a portion of the device.
従って、本発明による厚膜回路基板は無電解めつき法に
よりスルーホールめっきを行うために、セラミック絶縁
基板表裏の厚膜回路導体間の接続を確実に行うことがで
きその接続の信頼性は極めて高く、さらには表面に露出
する厚膜回路導体層は無電解めっきで析出した導電金属
層により構成されるため、はんだづけによる銀〈われや
耐湿角＼
穂による銀のマクブレーションなど、従来例で使用した
銀至導体材料の欠点は全て解消できるなどの効果が得ら
れた。Therefore, since the thick film circuit board according to the present invention performs through-hole plating by electroless plating, it is possible to reliably connect the thick film circuit conductors on the front and back sides of the ceramic insulating board, and the reliability of the connection is extremely high. The thick film circuit conductor layer, which is high and exposed on the surface, is composed of a conductive metal layer deposited by electroless plating, so it is used in conventional methods such as silver macbrasion using soldering. The results showed that all of the drawbacks of silver-based conductor materials could be overcome.
第１図Ａ−Ｄは従来例による厚膜回路基板の製造工程図
、第２図Ａ−Ｆは本発明の一実施例における厚膜回路基
板の製造方法を示す製造工程図である。
６・・・・・・セラミック絶縁基板、７・・・・・・貫
通孔、８・・・・・・活性化層、 ９ 、９’・・・・
・・厚膜回路導体層、１０・・・・・・厚膜抵抗体層、
１１．１１’・・・・・・絶縁レジスト層、１２・・・
・・・導電金属層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
５′３′1A to 1D are manufacturing process diagrams of a conventional thick film circuit board, and FIGS. 2A to 2F are manufacturing process diagrams showing a method of manufacturing a thick film circuit board according to an embodiment of the present invention. 6...Ceramic insulating substrate, 7...Through hole, 8...Activation layer, 9, 9'...
... Thick film circuit conductor layer, 10... Thick film resistor layer,
11.11'...Insulating resist layer, 12...
...Conductive metal layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 5'3'
Claims (2)
け、前記セラミック絶縁基板に活性化処理を行う工程、
前記セラミック絶縁基板の表裏両面に所望の回路図形状
にグレーズ系の導電ペーストと、必要により少くともそ
の一方の主面上にグレーズ系の抵抗体ペーストをそれぞ
れ塗布し、高温焼成することにより導体層と抵抗体をそ
れぞれ形成する工程、前記貫通孔と導体層の一部が露出
するように他の面に耐めっき性を有する絶縁レジスト層
を形成する工程、前記露出した貫通孔内壁部と回路導体
層の一部に無電解めっき法により導電金属層を形成する
工程から成る厚膜回路基板の製造方法。(1) A step of drilling a through hole in a predetermined position of a ceramic insulating substrate and performing an activation treatment on the ceramic insulating substrate;
A glaze-based conductive paste is applied to both the front and back surfaces of the ceramic insulating substrate in the desired circuit shape, and if necessary, a glaze-based resistor paste is applied to at least one main surface, and the conductive layer is formed by baking at a high temperature. a step of forming an insulating resist layer having plating resistance on the other surface so that a part of the through hole and the conductor layer are exposed, and a step of forming an insulating resist layer having plating resistance on the other surface so that the through hole and a part of the conductor layer are exposed, and the exposed inner wall of the through hole and the circuit conductor. A method for manufacturing a thick film circuit board, which comprises a process of forming a conductive metal layer on a part of the layer by electroless plating.
ジストを使用する特許請求の範囲第１項記載の厚膜回路
基板の製造方法。(2) The method for manufacturing a thick film circuit board according to claim 1, wherein an easily peelable resist is used as the plating-resistant resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4342284A JPS60187047A (en) | 1984-03-07 | 1984-03-07 | Manufacture of thick film circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4342284A JPS60187047A (en) | 1984-03-07 | 1984-03-07 | Manufacture of thick film circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60187047A true JPS60187047A (en) | 1985-09-24 |
Family
ID=12663260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4342284A Pending JPS60187047A (en) | 1984-03-07 | 1984-03-07 | Manufacture of thick film circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60187047A (en) |
-
1984
- 1984-03-07 JP JP4342284A patent/JPS60187047A/en active Pending
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