JPS60165793A - Method of producing multilayer circuit board - Google Patents

Method of producing multilayer circuit board

Info

Publication number
JPS60165793A
JPS60165793A JP1984484A JP1984484A JPS60165793A JP S60165793 A JPS60165793 A JP S60165793A JP 1984484 A JP1984484 A JP 1984484A JP 1984484 A JP1984484 A JP 1984484A JP S60165793 A JPS60165793 A JP S60165793A
Authority
JP
Japan
Prior art keywords
layer
circuit conductor
conductor layer
insulating
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984484A
Other languages
Japanese (ja)
Inventor
中村 恒
寛敏 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1984484A priority Critical patent/JPS60165793A/en
Publication of JPS60165793A publication Critical patent/JPS60165793A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業−にの利用分野) 本発明はテlノビ受像機やビデオテープレコーダなどの
電子回路を構成するための多層配線基板の製造方法に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a multilayer wiring board for configuring electronic circuits such as television receivers and video tape recorders.

(従来例の構成とその問題点) 近年、電子機器の「軽、薄、短、小J化に対する要求は
ますます増大しており、それにともなって、これら電子
回路の高密度化が必要不可欠となって来ている。このよ
うな中にあって、電工回路を構成する回路基板の高密度
化はもっとも重要な技術課題とされ、低コストで、高信
頼性を有する多層配線基板が強く望まれている。
(Conventional structure and its problems) In recent years, the demand for electronic devices to be lighter, thinner, shorter, and smaller in size has been increasing, and with this, it has become essential to increase the density of these electronic circuits. Under these circumstances, increasing the density of circuit boards that make up electrical circuits is considered the most important technical issue, and low-cost, highly reliable multilayer wiring boards are strongly desired. ing.

多層配線基板については、従来から実に多くの製ifU
方法が提案され、実施されて来ているが、そのほどんど
は層間の回路導体層をスルーホールで接続するものであ
る。ところが昨今、層間の回路導体層をスルーホールに
よらず面接続タイプのいわり)るバイヤホール接続によ
る方法が広〈実施されて来ている。このようなパイヤホ
ール接続は、接続に要する回路導体層の占有面積が小さ
くてすむことから、実質的な回路の高密度化が図れる利
点があり、セラミック基板をベースとした多層配線基板
は全てバイヤホール接続によるものである。
Regarding multilayer wiring boards, there have been many ifU
Although methods have been proposed and implemented, most of them connect interlayer circuit conductor layers with through holes. However, in recent years, a method of connecting circuit conductor layers between layers using via holes instead of through holes has been widely used. This type of via hole connection has the advantage of effectively increasing the density of the circuit because the area occupied by the circuit conductor layer required for connection is small, and all multilayer wiring boards based on ceramic substrates use via holes. It depends on the connection.

その代表的な製造方法詮第1図(A)〜(C)に示した
。この多層配線基板は、第1図(A)に示すように、セ
ラミック絶縁基板1の表面にメタルグレーズ系の導電ペ
ーストを所望の配線回路状に印刷し、高温焼成すること
により内層回路導体層2を形成する工程、第1図(T3
)に示すように、内層回路導体層の一部が露出するよう
に、その表面にガラスを主成分とした絶縁ペーストを選
択的に塗布3− し、高温焼成することによりパイヤホール3を設けた絶
縁体層4を形成する工程、第1図(C)に示すように、
絶縁体層4の表面にメタルグレーズ系の導電ペーストを
所望の配線回路状に印刷すると同時に、絶縁体層4に設
けたバイヤホール3の中にも導電ペーストを充填して、
高温焼成することにより最外層の回路導体層5を形成す
るに程かl)成り、以下第1図(B)、(C)の工程を
順次くり返して配線回路を多層化するものである。
A typical manufacturing method thereof is shown in FIGS. 1(A) to 1(C). As shown in FIG. 1(A), this multilayer wiring board is manufactured by printing a metal glaze-based conductive paste in a desired wiring circuit shape on the surface of a ceramic insulating substrate 1, and baking it at a high temperature to form an inner circuit conductor layer 2. Figure 1 (T3
), an insulating paste containing glass as a main component is selectively applied to the surface of the inner circuit conductor layer so that a part of it is exposed, and then baked at a high temperature to form an insulator with pipe holes 3. The step of forming the body layer 4, as shown in FIG. 1(C),
A metal glaze type conductive paste is printed on the surface of the insulating layer 4 in the shape of a desired wiring circuit, and at the same time, the via holes 3 provided in the insulating layer 4 are also filled with the conductive paste.
By firing at a high temperature, the outermost circuit conductor layer 5 is formed (l), and the steps shown in FIGS. 1(B) and 1(C) are successively repeated to form a multilayer wiring circuit.

しかしながら、このような製造方法による多層配線基板
では、メタルグレーズ系の高価な材料を必要とし、また
導体層と絶縁体層の形成工程において、それぞれ800
〜850℃の高温で約1時間の焼成を必要とするため、
敬産化における工程編成が煩雑となるなどの不都合があ
った。
However, the multilayer wiring board manufactured by such a manufacturing method requires expensive materials such as metal glaze, and the process of forming the conductor layer and the insulator layer requires 800 microns each.
Because it requires baking at a high temperature of ~850°C for about 1 hour,
There were inconveniences such as the complicated process organization for sanitation.

この問題を解決する方法として、最外層の回路導体層を
銀の微粉末を樹脂に分散した導電ペーストを用いて形成
する方法が提案されている。しかし、この樹脂系の導電
ペーストを用いて形成した回路導体層では、絶縁体層に
設けたパイヤホール4− を通して内層回路導体層との電気的接続を確実に行なう
ことは出来るが、反面その表面層では銀の粉末が樹脂で
完全に被覆されているために、はんだづけ性が極めて悪
く、また表面を研磨して銀を露出てせた状態ではんだづ
けを行なってもいわゆる銀くわれが著しく発生すること
、さらには銀粉末を多層に含んだ導電ペーストでは回路
導体層と絶縁体層間の接着強度が低下するなどの問題が
あり、その改善が強く望まれていた。
As a method to solve this problem, a method has been proposed in which the outermost circuit conductor layer is formed using a conductive paste in which fine silver powder is dispersed in a resin. However, with the circuit conductor layer formed using this resin-based conductive paste, although it is possible to ensure electrical connection with the inner circuit conductor layer through the pie holes 4- provided in the insulator layer, on the other hand, the surface layer Since the silver powder is completely covered with resin, the solderability is extremely poor, and even if the surface is polished to expose the silver, so-called silver cracks will occur significantly. Furthermore, conductive pastes containing multiple layers of silver powder have problems such as reduced adhesive strength between circuit conductor layers and insulator layers, and there has been a strong desire to improve these problems.

(発明の目的) 本発明の目的は、最外層の回路導体層がはんだづけイノ
1にすぐれ、かつ絶縁体層との接着性にすぐれた多層配
線基板の製造方法を提供することである。
(Objective of the Invention) An object of the present invention is to provide a method for manufacturing a multilayer wiring board in which the outermost circuit conductor layer has excellent soldering properties and excellent adhesion to an insulating layer.

(発明の構成) 本発明は、絶縁基板の少くとも一生面に回路導体層と絶
縁体層を交互に形成し、絶縁体層に設けたパイヤホール
を通して層間の回路導体層を電気的に接続する多層配線
基板の製造方法で、最外層の回路導体層を、まず絶縁体
層に設けたバイヤホ5− −ルに導電性樹脂を充てんし、この導電性樹脂層の一部
に接するようにして絶縁性接着剤を所望の配線図形に塗
布し、その表面に金属粉末を固定させ、しかる後に無電
解めっきを行なって金属粉末層上に導電金属層を析出さ
せることにより形成するものであり、これにより、はん
だづけ性と接着性にすぐれた多層配線基板が実現できる
ものである。
(Structure of the Invention) The present invention provides a multilayer structure in which circuit conductor layers and insulator layers are alternately formed on at least one surface of an insulating substrate, and the circuit conductor layers between the layers are electrically connected through pie holes provided in the insulator layer. In a method of manufacturing a wiring board, the outermost circuit conductor layer is first filled with conductive resin in a via hole provided in an insulating layer, and then insulated so that it comes in contact with a part of the conductive resin layer. It is formed by applying adhesive to the desired wiring pattern, fixing metal powder to the surface, and then performing electroless plating to deposit a conductive metal layer on the metal powder layer. A multilayer wiring board with excellent solderability and adhesiveness can be realized.

(実施例の説明) 以下本発明の実施例について図面を参照しながら説明す
る。
(Description of Examples) Examples of the present invention will be described below with reference to the drawings.

第2図(A)〜(F)は、本発明の−・実施例に才目す
る多層配線基板の一連の製造工程を示したものであり、
6は絶縁基板、7は内層回路導体層、8は絶縁体層、9
はパイヤホール、10は導電性樹脂層、11は接着剤層
、12は金属粉末層、13は導電金属層、14は最外層
の回路導体層である。
FIGS. 2(A) to 2(F) show a series of manufacturing steps for a multilayer wiring board according to an embodiment of the present invention.
6 is an insulating substrate, 7 is an inner circuit conductor layer, 8 is an insulator layer, 9
10 is a conductive resin layer, 11 is an adhesive layer, 12 is a metal powder layer, 13 is a conductive metal layer, and 14 is an outermost circuit conductor layer.

次に、その製造方法を詳細に説明する。まず、第2図(
A)に示すように、絶縁基板6の主面−トに所望の内層
回路導体層7を形成する。絶縁基板66− としては紙−フェノール積層板やガラス−エポキシ積層
板などの合成樹脂基板、アルミナ磁器などのセラミック
基板が使用でき、合成樹脂基板の場合には、全面に電解
銅はくを接着したものをエツチング処理して不要部分の
銅はくを溶解除去するごとにより内層回路導体層7を形
成する。また一方、セラミック基板の場合には、銀や銀
−パラジウ11から成るメタルグレーズ系の導電ペース
トをスクリーン印刷法により所望の配線回路状に塗布し
、800〜850℃の空気中で高温焼成することにより
内層回路導体層7を形成する。
Next, the manufacturing method will be explained in detail. First, Figure 2 (
As shown in A), a desired inner circuit conductor layer 7 is formed on the main surface of the insulating substrate 6. As the insulating substrate 66, a synthetic resin substrate such as a paper-phenol laminate or a glass-epoxy laminate, or a ceramic substrate such as alumina porcelain can be used. In the case of a synthetic resin substrate, an electrolytic copper foil is bonded to the entire surface. The inner circuit conductor layer 7 is formed by etching the material and dissolving and removing unnecessary portions of the copper foil. On the other hand, in the case of a ceramic substrate, a metal glaze-based conductive paste made of silver or silver-palladium 11 is applied in the desired wiring circuit shape by screen printing, and then baked at a high temperature in air at 800 to 850°C. The inner circuit conductor layer 7 is formed by the following steps.

次に、第2図(B)に示すように、絶縁基板6の主面1
−に形成した内層回路導体層7の表面に内層回路導体層
7の一部が露出するようにパイヤホール9を設けた絶縁
体層8を形成する。本実施例では、絶縁体層8は使用す
る絶縁基板6の材質には無関係に感光性樹脂によって構
成し、例えばアクリル樹脂や、環化ゴム系ポリブタジェ
ン樹脂とアクリル樹脂の2層構造を有する感光性絶縁フ
ィルムを使用した。これらの感光性絶縁フィルムを、内
層回路導体層7を形成した絶縁基板6の全面にラミネー
トし、この表面にバイヤホールを形成するための所定の
マスクフィルムを密着させて、紫外線露光及び現像処理
を施こして、微細な径を有するパイヤホール9を形成し
、パイヤホール9を設けた絶縁体層8を形成した。
Next, as shown in FIG. 2(B), the main surface 1 of the insulating substrate 6 is
An insulator layer 8 is formed on the surface of the inner circuit conductor layer 7 formed on the inner circuit conductor layer 7 in which a pie hole 9 is provided so that a part of the inner circuit conductor layer 7 is exposed. In this embodiment, the insulating layer 8 is made of a photosensitive resin regardless of the material of the insulating substrate 6 used, such as an acrylic resin or a photosensitive resin having a two-layer structure of a cyclized rubber-based polybutadiene resin and an acrylic resin. Insulating film was used. These photosensitive insulating films are laminated on the entire surface of the insulating substrate 6 on which the inner circuit conductor layer 7 has been formed, a prescribed mask film for forming via holes is attached to this surface, and UV exposure and development treatment are carried out. By this process, a pie hole 9 having a fine diameter was formed, and an insulator layer 8 provided with the pie hole 9 was formed.

次いで、第2図(C)に示すように、銀や銅の微粉末を
エポキシ樹脂などに分散、混合したいわり)る樹脂系の
導電性樹脂10を、スクリーン印刷法やディスペンサー
を用いて絶縁体層8に設けたパイヤホール9の中に充て
んするとどもに、必要に応じてその周辺の一部にも塗布
し、この導電+11摺脂を加熱硬化する。
Next, as shown in FIG. 2(C), a conductive resin 10 made by dispersing and mixing fine silver or copper powder in an epoxy resin or the like is used as an insulator using a screen printing method or a dispenser. In addition to filling the pie hole 9 provided in the layer 8, if necessary, it is also applied to a part of the surrounding area, and the conductive +11 resin is heated and cured.

このようにして絶縁体層8に設けたパイヤホール9に導
電性樹脂10を充てんしてフタをし、内層回路導体層7
を外部から完全に遮断した後、第2図(D)に示すよう
に、絶縁性樹脂にカーボン粉末を分散、混合した接着剤
11を、スクリーン印刷法により最外層の絶縁体層8の
表面に塗布し、その一部が導電性樹脂層IOの一部に接
するようにして一/− 所望の配線図形を形成する。
The pie holes 9 thus formed in the insulator layer 8 are filled with conductive resin 10 and covered, and the inner circuit conductor layer 8 is
After completely shielding from the outside, as shown in FIG. 2(D), an adhesive 11 made by dispersing and mixing carbon powder in an insulating resin is applied to the surface of the outermost insulating layer 8 by screen printing. 1/- to form a desired wiring pattern so that a part of the conductive resin layer IO is in contact with a part of the conductive resin layer IO.

この接着剤1】が硬化しない状態で、第2図(E)に示
すように、その表面に例えば銅、鉄、ニッケル、銀など
の金属微粉末12を散布し、ローラーで圧着してから、
絶縁体層8の不要部分に付着した金属微粉末を除去し、
接着剤11を加熱硬化させる。
Before the adhesive 1 has hardened, fine metal powder 12 of copper, iron, nickel, silver, etc., for example, is sprinkled on its surface as shown in FIG. 2(E), and it is pressed with a roller.
Remove metal fine powder adhering to unnecessary parts of the insulator layer 8,
The adhesive 11 is heated and cured.

この工程において使用する金属粉末は、次工程の無電解
めっきの触媒核となる金属を用いることが必要であるが
、本実施例では、粒径が約10μmの樹枝状の電解銅粉
末を用い、これにりより表面状態が良好で、接着力にす
ぐれた回路導体層を形成することが出来た。
The metal powder used in this step must be a metal that will serve as the catalyst nucleus for the electroless plating in the next step, but in this example, dendritic electrolytic copper powder with a particle size of about 10 μm was used. This made it possible to form a circuit conductor layer with a good surface condition and excellent adhesive strength.

最後に、第2図(F)に示すように、接着剤11の表面
に固着した金属微粉末層12上に無電解銅めっきを施し
て金属鋼から成る導電金属層13を析出させ、最外層の
回路導体層14を形成する。
Finally, as shown in FIG. 2(F), electroless copper plating is performed on the metal fine powder layer 12 fixed to the surface of the adhesive 11 to deposit a conductive metal layer 13 made of metal steel, and the outermost layer is A circuit conductor layer 14 is formed.

なお本実施例では、絶縁基板の一方の主面にのみ回路導
体層を形成し、その表面に絶縁層と回路導体層を順次形
成した2層構造のものについて説明したが、本発明では
2層構造の多層配線基板に一〇− 8− のみ限定されるものではなく、絶縁基板の表裏にわたっ
て回路導体層を形成し、それぞれの回路導体層上にパイ
ヤホールを設けた絶縁体層を形成して回路導体層を多層
化するとともに、絶縁基板を貫通する孔を通して絶縁基
板の表裏に形成した回路導体層を接続した多層配線基板
にも適用されるものである。さらにはこのような多層配
線基板において、ベースとなる絶縁基板にセラミック基
板を使用し、その表面或は表裏両面に銀糸のメタルグレ
ーズ厚膜導体により回路導体層を構成し、これと、同一
面に酸化ルテニウム系の抵抗体層をスクリーン印刷法に
よって形成したものを絶縁樹脂で絶縁して回路導体層を
多層化したものであってもよく、本発明では−1;述し
たような抵抗体層を内蔵した多層回路基板が実現できる
ことも大きな特徴の一つであり、実際、このような抵抗
体を内蔵した多層回路基板も製作し、良好な結果を得て
いる。
In this example, a two-layer structure was described in which a circuit conductor layer was formed only on one main surface of an insulating substrate, and an insulating layer and a circuit conductor layer were sequentially formed on the surface of the insulating substrate. The circuit is not limited to a multilayer wiring board having a structure of The present invention is also applied to a multilayer wiring board in which conductor layers are multilayered and circuit conductor layers formed on the front and back sides of an insulating substrate are connected through holes penetrating the insulating substrate. Furthermore, in such a multilayer wiring board, a ceramic substrate is used as the base insulating substrate, and a circuit conductor layer is formed with a thick film conductor made of metal glaze made of silver thread on the front and back surfaces of the ceramic substrate, and a circuit conductor layer is formed on the same surface. A circuit conductor layer may be formed by forming a ruthenium oxide resistor layer by screen printing and insulating it with an insulating resin to form a multilayer circuit conductor layer. One of the major features is that it is possible to create multilayer circuit boards with built-in resistors, and we have actually manufactured multilayer circuit boards with built-in resistors, and have obtained good results.

(発明の効果) 以上の説明から明らかなように、本発明は、絶縁基板の
主面上に回路導体層と絶縁体層を交互に形成し、絶縁体
層に設けたパイヤホールを通して層間の回路導体層を接
続する多層配線基板の製造方法に関し、最外層の回路導
体層を、絶縁体層のバイヤホールにのみrめ導電性樹脂
を充てんして内層回路導体層を完全に被覆した後、その
導電性樹脂の一部に接するようにして接着剤を塗布し、
その表面に金属粉末製固着させてから無電解めっきを施
すことにより形成するものであり、このような方法によ
り最外層の回路導体層を形成することにより絶縁体層と
回路導体層との接着性が著しく強くなるとともに、導体
層を無電解めっき法により形成するため、はんだづけ性
が著しく改善されるなどの効果が得られる。
(Effects of the Invention) As is clear from the above description, the present invention provides circuit conductor layers and insulator layers that are alternately formed on the main surface of an insulating substrate, and circuit conductors between layers that are passed through pie holes provided in the insulator layer. Regarding the manufacturing method of a multilayer wiring board that connects layers, only the via holes of the outermost circuit conductor layer are filled with conductive resin to completely cover the inner circuit conductor layer, and then the conductive resin is Apply adhesive so that it touches a part of the adhesive resin,
It is formed by fixing metal powder on the surface and then applying electroless plating, and by forming the outermost circuit conductor layer using this method, the adhesiveness between the insulator layer and the circuit conductor layer is improved. In addition, since the conductor layer is formed by electroless plating, the solderability is significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)〜(C)は、従来例による多層配線基板の
一連の製造工程を示す図、第2図(A)〜(F)は、本
発明の一実施例における多層配線基板の一連の製造工程
を示す図である。 6 ・・・絶縁基板、 7 ・・・内層回路導体層、8
 ・・・絶縁体層、 9・・・パイヤホール、10・・
・導電性樹脂層、11・・・絶縁性接着剤層、12・・
・金属微粉末層、13・・・導電金属層、14・・・最
外層回路導体層。 特許出願人 松下電器産業株式会社 第1図 ( 第2図
FIGS. 1(A) to (C) are diagrams showing a series of manufacturing steps of a multilayer wiring board according to a conventional example, and FIGS. 2(A) to (F) are diagrams showing a series of manufacturing steps of a multilayer wiring board according to an embodiment of the present invention. It is a diagram showing a series of manufacturing steps. 6...Insulating substrate, 7...Inner circuit conductor layer, 8
...Insulator layer, 9...Piere hole, 10...
・Conductive resin layer, 11... Insulating adhesive layer, 12...
- Fine metal powder layer, 13... Conductive metal layer, 14... Outermost circuit conductor layer. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1 (Figure 2)

Claims (4)

【特許請求の範囲】[Claims] (1)絶縁基板の少くとも一十面上に回路導体層と絶縁
体層を交Ifに形成し、前記絶縁体層に設けたパイヤホ
ールを通して層間の回路導体層を電気的に接続する多層
配線基板の製造方法において、最外層の回路導体層が、
絶縁体層に設けたバイヤホールに導電性樹脂を充填し、
その導電性樹脂層の一部に接するようにして絶縁性接着
剤を所望の配線図形状に塗布し、その表面に全屈粉末を
固着させ、その金属粉末層]二に熱電解めっきを施すこ
とにより形成さオしることを特徴とする多層配線基板の
製造方法。
(1) A multilayer wiring board in which a circuit conductor layer and an insulator layer are formed at an intersection If on at least ten sides of an insulating substrate, and the circuit conductor layers between the layers are electrically connected through a pie hole provided in the insulator layer. In the manufacturing method, the outermost circuit conductor layer is
Fill the via holes in the insulator layer with conductive resin,
An insulating adhesive is applied in the desired wiring diagram shape so as to be in contact with a part of the conductive resin layer, a total bending powder is fixed on the surface, and the metal powder layer is subjected to thermal electrolytic plating. 1. A method for manufacturing a multilayer wiring board, characterized in that the multilayer wiring board is formed by:
(2) 前記絶縁基板に合成樹脂板を使用し、内層回路
導体層が銅はくをエツチングすることにより形成される
ことを特徴とする特許請求の範囲第(1)項記載の多層
回路基板の製造方法。
(2) The multilayer circuit board according to claim (1), wherein a synthetic resin board is used for the insulating board, and the inner circuit conductor layer is formed by etching a copper foil. Production method.
(3)前記絶縁基板にセラミック基板を使用し、 1− 内層回路導体層がメタルグ1ノーズ系の71%膜導体に
より形成され、かつ、最外層の絶縁体層が絶縁f1樹脂
により形成されることを特徴とする特許請求の範囲第(
1)項記載の多層回路基板の製造方法。
(3) A ceramic substrate is used as the insulating substrate, 1- The inner circuit conductor layer is formed of a 71% film conductor of metallurgy 1 nose type, and the outermost insulator layer is formed of an insulating f1 resin. Claim No. 1 characterized in (
1) The method for manufacturing a multilayer circuit board as described in item 1).
(4) 前記セラミック基板」二に形成された厚膜回路
導体層と同一面上に抵抗体層が形成されることを特徴と
する特許請求の範囲第(3)項記載の多層回路基板の製
造方法。
(4) Manufacturing a multilayer circuit board according to claim (3), wherein a resistor layer is formed on the same surface as the thick film circuit conductor layer formed on the ceramic substrate. Method.
JP1984484A 1984-02-08 1984-02-08 Method of producing multilayer circuit board Pending JPS60165793A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984484A JPS60165793A (en) 1984-02-08 1984-02-08 Method of producing multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984484A JPS60165793A (en) 1984-02-08 1984-02-08 Method of producing multilayer circuit board

Publications (1)

Publication Number Publication Date
JPS60165793A true JPS60165793A (en) 1985-08-28

Family

ID=12010565

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984484A Pending JPS60165793A (en) 1984-02-08 1984-02-08 Method of producing multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS60165793A (en)

Similar Documents

Publication Publication Date Title
JP2002043752A (en) Wiring board, multilayer wiring board, and their manufacturing method
JPH06120643A (en) Flexible wiring board and production thereof
US20040168314A1 (en) Process for manufacture of printed circuit boards with thick copper power circuitry and thin copper signal circuitry on the same layer
JPH11163525A (en) Manufacture of multilayer wiring board
JPS60165793A (en) Method of producing multilayer circuit board
JP2001160681A (en) Multilayer ceramic board and its manufacturing method
JP2003086947A (en) Printed wiring substrate and its manufacturing method
JPH0265194A (en) Manufacture of printed wiring board with thick film element
JPS60117796A (en) Multilayer circuit board and method of producing same
JPS60167495A (en) Method of producing multilayer circuit board
KR930000639B1 (en) Manufacturing method of high density multilayer printed circuit board
JP2537893B2 (en) Electronic circuit board manufacturing method
JP3872461B2 (en) Multilayer wiring board and manufacturing method thereof
JPS6231190A (en) Electronic circuit board and manufacture thereof
JPH0724335B2 (en) Manufacturing method of multilayer circuit board
JPS6293993A (en) Electronic circuit device and mounting of the same
JPS61147597A (en) Ceramic circuit board and manufacture thereof
JPS60165794A (en) Method of producing multilayer circuit board
JPS60183794A (en) Method of producing multilayer circuit board
JPH0763109B2 (en) Ceramic circuit board manufacturing method
JPH02164094A (en) Manufacture of printed wiring board
JPS6289344A (en) Manufacture of multilayer interconnection substrate
JPH05110259A (en) Multilayer printed wiring board and manufacture thereof
KR20040046626A (en) A manufacturing process of multi-layer printed circuit board
JPS60187047A (en) Manufacture of thick film circuit board