JPS58186996A - Method of producing multilayer circuit board - Google Patents

Method of producing multilayer circuit board

Info

Publication number
JPS58186996A
JPS58186996A JP7086182A JP7086182A JPS58186996A JP S58186996 A JPS58186996 A JP S58186996A JP 7086182 A JP7086182 A JP 7086182A JP 7086182 A JP7086182 A JP 7086182A JP S58186996 A JPS58186996 A JP S58186996A
Authority
JP
Japan
Prior art keywords
insulating layer
melting point
insulating
forming
paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7086182A
Other languages
Japanese (ja)
Other versions
JPH0380358B2 (en
Inventor
矢部 勝彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7086182A priority Critical patent/JPS58186996A/en
Publication of JPS58186996A publication Critical patent/JPS58186996A/en
Publication of JPH0380358B2 publication Critical patent/JPH0380358B2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は1G、  コンデンサー、抵抗等の能動素子並
びに受動素子を多数個実装する九めの多層回路基板の製
造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ninth method for manufacturing a multilayer circuit board on which a large number of active elements and passive elements such as 1G, capacitors, and resistors are mounted.

従来、この種の多層回路基板の多層の導体回路間を絶縁
するための絶縁層をスクリーン印刷によって形成する際
、下地として存在する回路用導体の影響を受け、バイア
ホール形状をスクリーン上に形成したパターン通シに印
刷形成する事が困難であった。また、絶縁層材料として
は、近年の高速演算用高密度多層回路基板の必要性から
低い比鋳電率、^い熱伝導性、大きい機械的*f等の物
理的特性が要求される為、ガラス粉末と、アル建す等の
無機酸化物粉末の混合物が使用されている。
Conventionally, when forming an insulating layer to insulate between the multilayer conductor circuits of this type of multilayer circuit board by screen printing, a via hole shape was formed on the screen due to the influence of the circuit conductor existing as the base. It was difficult to print the entire pattern. In addition, the recent need for high-density multilayer circuit boards for high-speed calculations requires insulating layer materials to have physical properties such as low specific electric current, high thermal conductivity, and large mechanical *f. A mixture of glass powder and inorganic oxide powder such as aluminum is used.

故に形成後の絶縁層は気孔を多く含んでいる0気孔が多
いとメッキ工程などでメッキ液が滲みこみ、金属が析出
して上下の導体層間を短絡させ、絶縁性を劣化させると
いうような欠点がある0本発明は上記欠点を除き、気孔
を低減することによプ絶縁性の劣化を防ぐと共に機械的
装置を大きくシ、シかもバイアホールを確保して上下層
導体との接続を確実に行うことができる多層回路基板の
製造方法を提供するものである0 本発明の多層回路基板の製造方法は、セラミック基板上
にIll導体パターンを形成する蕗l工程と、高融点の
ガラス粉末と無機酸化物粉末とを含んで構成される纂l
絶縁ペーストとパイ7ホール形成用パターンを有するス
クリーンとを用いて前記jlEl導体パターンを含むセ
ラミック基板上に纂l絶縁ペースト塗布層を形成し、前
記高融点ガラス粉末の軟化点と融点との間の温度で焼成
して纂l絶縁層を形成する纂2工鵬と、低融点ガラス粉
末を含む藤2絶縁ペーストで前記I11導電パーーンの
露出l並びに纂l絶縁層を櫃りて塗布し、前記低融点ガ
ラスの軟化点よシ少し高い温度で焼成して第2絶縁層を
形成する工程と、前記[1絶縁ペーストと前記第2工程
で用いたスクリーンとを用いて前記m2絶縁層の上に前
記ill絶縁層のパターンと整合したパターンを有する
纂3ペースト塗布層を形成し、前記wJ1絶縁ペースト
中の高融点ガラスの軟化点と融点との間の温度で焼成し
て第3絶縁層を形成する工程とを含んで構成される。
Therefore, the insulating layer after formation contains many pores.If there are many pores, the plating solution will seep in during the plating process, metal will precipitate, and this will cause a short circuit between the upper and lower conductor layers, deteriorating the insulation properties. The present invention eliminates the above drawbacks, prevents deterioration of insulation properties by reducing pores, enlarges mechanical equipment, secures via holes, and secures connections with upper and lower layer conductors. The method of manufacturing a multilayer circuit board of the present invention includes a process of forming an Ill conductor pattern on a ceramic substrate, and a process of forming an Ill conductor pattern on a ceramic substrate, and a process using a high melting point glass powder and an inorganic A collection consisting of oxide powder
A layer of insulating paste is formed on the ceramic substrate including the conductor pattern using an insulating paste and a screen having a pattern for forming holes, and a layer of insulating paste is formed between the softening point and the melting point of the high melting point glass powder. The exposed part of the I11 conductive pattern and the insulating layer are coated with a wire insulating paste containing low melting point glass powder, which is fired at a high temperature to form the insulating layer. a step of forming a second insulating layer by firing at a temperature slightly higher than the softening point of the melting point glass; forming a third paste coating layer having a pattern consistent with the pattern of the ill insulating layer, and firing at a temperature between the softening point and the melting point of the high melting point glass in the wJ1 insulating paste to form a third insulating layer; It consists of a process.

次に、本発明の実施例について図面を用いて説明する。Next, embodiments of the present invention will be described using the drawings.

m1図乃至W、6図は本発明の一実施例を説明するため
の主な製造工程における断面図である。
Figures m1 to W and 6 are cross-sectional views of main manufacturing steps for explaining an embodiment of the present invention.

まず、原材料として、アルミナ等で作られるセラミック
基板、 Au 、 A4/Pd頓貴金属を含む厚膜導体
形成用ペース)、800℃の軟化点と1000℃の融点
を有するallのガラス粉末とアルンナ粉末とを含む第
1絶縁ペースト、500℃の軟化点と850℃の融点を
有する纂2のガラス粉末を含む蕗2P3縁ペーストを用
意する。
First, as raw materials, a ceramic substrate made of alumina etc., a thick film conductor forming paste containing Au, A4/Pd (containing precious metals), all glass powder with a softening point of 800 degrees Celsius and a melting point of 1000 degrees Celsius, and Aluna powder. A first insulating paste containing a glass powder having a softening point of 500°C and a melting point of 850°C is prepared.

次に、I@1図に示すように、セラミック基板lの上に
厚膜形成用ペーストt11!用しスクリーン刷法によシ
萬1導体パターン2を形成する。この上にIIEIの絶
縁ペーストをスクリーン印刷法で印刷し、乾燥し、纂l
絶縁ペースト塗布層3を形成する。このとき、スクリー
ンには後の工程で形成される纂2導体パターンをwt1
4t3導体パー−ン2に接続させる九めのバイアホール
7を有しているものを用いる〇 次にs’l’12図に示すようにs jl 1絶縁ペ一
スト塗布層3を基板lと共に850℃で焼成してIEI
絶縁層4を形成する。この焼成でMl絶鍬層4には気孔
5が多数発生する。
Next, as shown in Figure I@1, a thick film forming paste t11! is placed on the ceramic substrate l! A conductor pattern 2 is formed using a screen printing method. On top of this, IIII insulation paste was printed using the screen printing method, dried, and assembled.
An insulating paste coating layer 3 is formed. At this time, the screen has a two-wire conductor pattern wt1 that will be formed in a later process.
4T3 Use the one having the ninth via hole 7 to be connected to the conductor pern 2〇Next, as shown in figure s'l'12, apply the sjl 1 insulating paste coating layer 3 together with the substrate l. IEI by firing at 850℃
An insulating layer 4 is formed. This firing generates a large number of pores 5 in the Ml-free layer 4.

次に、第3図に示すように、纂2φ絶縁ペーストを全表
面に塗布し、530℃で焼成してバイアホール7を埋め
九312絶縁層6を形成する。
Next, as shown in FIG. 3, a strand of 2φ insulating paste is applied to the entire surface and fired at 530° C. to fill the via hole 7 and form a 9312 insulating layer 6.

次に、第4図に示すように、jlE1図に示した属l絶
縁ペースト塗布層3を形成し九ときのスクリーンと第1
絶縁ペーストとを用い、纂l絶縁ペースト塗布層3と同
じパターンを有する藤3絶縁ペースト塗布層3′とバイ
アホール7とを形成する。
Next, as shown in FIG. 4, a layer 3 of insulation paste shown in FIG.
An insulating paste coating layer 3' having the same pattern as the insulating paste coating layer 3 and a via hole 7 are formed using the insulating paste.

5− 次に、jtEs図に示すように、累3絶縁ペースト塗布
NI3′を基板lと共に850℃で焼成し、第3絶縁層
9を形成する。このとき、第2絶縁層6は融点が850
℃であるから、この焼成時に溶融し、纂l及び第3絶縁
層4.9の気孔5.lO内に入り込む形で吸収されるの
で、バイアホール7中の[1導体パターン2上の第2絶
縁層6の大部分はなくなり、4体表面が露出する。
5- Next, as shown in the jtEs diagram, the third insulating paste coating NI3' is fired together with the substrate l at 850°C to form the third insulating layer 9. At this time, the second insulating layer 6 has a melting point of 850
℃, the pores 5. of the coil and the third insulating layer 4.9 melt during firing. Since it is absorbed by penetrating into lO, most of the second insulating layer 6 on the first conductor pattern 2 in the via hole 7 disappears, and the surface of the fourth body is exposed.

次に、IIL6図に示すように、厚膜導体形成用ペース
)t−J=Nいてスクリーン印刷、乾燥、焼成して纂2
4体パターン11を形成する。
Next, as shown in Figure IIL6, the thick film conductor forming paste (t-J=N) was screen printed, dried, and fired to form a finished product.
A four-body pattern 11 is formed.

以上の工程を必要回数繰返えせば多層回路基板を得るこ
とができる・この実施例で示したように、軟化点と融点
の異なる2種の絶縁ペーストを用いることによシ、パイ
7ホールがつまることなくパターン通9に印刷形成でき
、かつ気孔をも轟ぎ、水分等の吸収による絶縁劣化を防
いだ多層回路基板が得られる。
A multilayer circuit board can be obtained by repeating the above steps a necessary number of times. As shown in this example, by using two types of insulating pastes with different softening points and melting points, the pie 7 hole can be A multilayer circuit board can be obtained which can be printed on the pattern 9 without clogging, and which also eliminates pores and prevents insulation deterioration due to absorption of moisture and the like.

本発明は、以上説明したように2種の絶縁ペースト2檀
の焼成温度を用いて緻密な絶縁層を形成6− する事によル、上下層導体の接続を微細なバイアホール
を介して確保し、しかも絶縁特性の優れた多層回路基板
を得るという効果がある0
As explained above, the present invention uses two types of insulating pastes at different firing temperatures to form a dense insulating layer, thereby ensuring connection between upper and lower layer conductors through fine via holes. Moreover, it has the effect of obtaining a multilayer circuit board with excellent insulation properties.

【図面の簡単な説明】[Brief explanation of the drawing]

l導体パターン、3・・・纂1絶縁ペースト塗布層、3
′・・・II3絶縁ペースト塗布層、4・・・萬l絶縁
層、5・・・気孔、6・・・票2絶縁層、7・・・パイ
7ホール、8・・・纂2絶縁層、9・・・属3絶縁層、
10・・・気孔、11・・・fill!2導体パターン
。  11 第1凶 第2凶 隼 3 凶 第4図 第5Δ し□□
l Conductor pattern, 3...strand 1 Insulating paste coating layer, 3
'...II3 insulating paste coating layer, 4...11 insulating layer, 5...pores, 6...2 insulating layers, 7...7 pie holes, 8...2 insulating layers , 9... Genus 3 insulating layer,
10...stomata, 11...fill! 2 conductor pattern. 11 1st bad 2nd bad Hayabusa 3 bad 4th figure 5Δ shi □□

Claims (1)

【特許請求の範囲】[Claims] セラミック基板上に纂1導体パターンを形成するIII
工穐と、高融点のガラス粉末と無機酸化物粉末とを含ん
で構成されるall絶縁ペーストとノ(イアホール形成
用パターンを有するスクリーンとを用いて前記Ill導
体パターンを含むセラミック基板上に′sl絶縁ペース
ト塗布層を形成し、前記高融点ガラス粉末の軟化点と融
点との間の温度で焼成して1g1絶縁層を形成する11
2工徊と、低融点ガラス粉末を含むlI2絶縁ペースト
で前記Ill導電パターンの露出−並びKjll絶縁層
を覆って塗布し、前記低融点ガラスの軟化点よp少し高
一温度で焼成してlI2I2絶縁層形成する工程と、前
記纂l絶縁ペーストと前記lI2工揚で用い九スクリー
ンとを用いて前配凧2絶縁層の上に前記纂l絶縁層のパ
ターンと整合したパターンを有する累3ペースト塗布層
を形成し、前記511絶縁ペースト中の高融点ガラスの
軟化点と融点との間の温度で焼成して纂3の絶縁層を形
成する工程とを含むことを特徴とする多層回路基板の製
造方法。
Forming a single conductor pattern on a ceramic substrate III
The 'sl' is applied to the ceramic substrate containing the Ill conductor pattern using an all insulating paste comprising a glass powder with a high melting point and an inorganic oxide powder, and a screen having a pattern for forming earholes. 11. Forming an insulating paste coating layer and firing at a temperature between the softening point and melting point of the high melting point glass powder to form a 1g1 insulating layer.
After 2 steps, an lI2 insulating paste containing a low melting point glass powder is applied to cover the exposed-aligned insulating layer of the Ill conductive pattern, and is fired at a temperature slightly higher than the softening point of the low melting point glass to form an lI2I2. forming an insulating layer, and forming a third paste having a pattern matching the pattern of the first insulating layer on the second insulating layer of the front kite using the first insulating paste and nine screens used in the first insulating layer; A multilayer circuit board characterized by comprising the steps of: forming a coating layer, and firing at a temperature between the softening point and melting point of the high melting point glass in the 511 insulation paste to form an insulating layer. Production method.
JP7086182A 1982-04-27 1982-04-27 Method of producing multilayer circuit board Granted JPS58186996A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7086182A JPS58186996A (en) 1982-04-27 1982-04-27 Method of producing multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7086182A JPS58186996A (en) 1982-04-27 1982-04-27 Method of producing multilayer circuit board

Publications (2)

Publication Number Publication Date
JPS58186996A true JPS58186996A (en) 1983-11-01
JPH0380358B2 JPH0380358B2 (en) 1991-12-24

Family

ID=13443760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7086182A Granted JPS58186996A (en) 1982-04-27 1982-04-27 Method of producing multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS58186996A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5141372A (en) * 1989-07-04 1992-08-25 Conver-Osr Ozean-Service-Reparatur-Ingenieurtechnik Gmbh Coupling piece for releasably connecting containers
DE4042710C2 (en) * 1990-09-25 2002-11-28 Macgregor Conver Gmbh Coupling piece for connecting containers

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5486765A (en) * 1977-12-23 1979-07-10 Tokyo Shibaura Electric Co Multiilayer thick film circuit base board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5486765A (en) * 1977-12-23 1979-07-10 Tokyo Shibaura Electric Co Multiilayer thick film circuit base board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5141372A (en) * 1989-07-04 1992-08-25 Conver-Osr Ozean-Service-Reparatur-Ingenieurtechnik Gmbh Coupling piece for releasably connecting containers
DE4042710C2 (en) * 1990-09-25 2002-11-28 Macgregor Conver Gmbh Coupling piece for connecting containers

Also Published As

Publication number Publication date
JPH0380358B2 (en) 1991-12-24

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