JPS601869A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS601869A JPS601869A JP11051883A JP11051883A JPS601869A JP S601869 A JPS601869 A JP S601869A JP 11051883 A JP11051883 A JP 11051883A JP 11051883 A JP11051883 A JP 11051883A JP S601869 A JPS601869 A JP S601869A
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- layer
- aluminum
- contact
- diffused layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 title claims 2
- 238000010438 heat treatment Methods 0.000 claims abstract description 22
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 4
- 239000001257 hydrogen Substances 0.000 claims abstract description 4
- 230000007774 longterm Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005245 sintering Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- 239000007790 solid phase Substances 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 3
- 239000012298 atmosphere Substances 0.000 abstract description 3
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 5
- 229910052782 aluminium Inorganic materials 0.000 abstract 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910018125 Al-Si Inorganic materials 0.000 abstract 1
- 229910018520 Al—Si Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052736 halogen Inorganic materials 0.000 abstract 1
- 150000002367 halogens Chemical class 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 230000000087 stabilizing effect Effects 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 12
- 230000035515 penetration Effects 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 241001197925 Theila Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011988 family based association test Methods 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、ＭＯ８型ＦＦ１Ｔの製造に関する。特に高集
積度Ｌ８１において有効である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the manufacture of MO8 type FF1T. This is particularly effective in the highly integrated L81.
従来、ＭＯ８・ＦＦ、Ｔの製造において、Ａｔ配線層と
拡散層のオーミック・コンタクトは、Ａｔ配線層蓄積後
、長時間Ｈ１熱処理シンタリングにより形成された。し
かしながら、ＬＳＩの高集積化に伴い、コンタクトホー
ルが微小化した１μ惧口以下になり、かつ拡散層がα３
μ惧より浅い接合が必要となるＶＬ８工製造において、
長時間Ｈ２シンタリング（例えば ４５０℃ ２０分）
熱処理は、Ａｔ配線の浅い拡散層からシリコン基板への
つき抜けの問題があり、さらに配線にＡｔＥ］ｉを用い
ると微細コンタクトホールにおいて８１の固相成長によ
るコンタクト不良の問題が、■ＬＳＩの歩留り低下の原
因になるという欠点があった本発明は、かかる従来の欠
点を取り除き、Ａｔ配線の浅い拡散層におけるつき抜け
を回避し、微小コンタクトにおけるコンタクト不良を防
ぎ、しかも安定したゲートおよびフィールドにおける８
１０、・８１界面を与えるＭＯ８−ＦＩＴの製造方法を
提供することを目的とする。Conventionally, in the manufacture of MO8 FFs and Ts, the ohmic contact between the At wiring layer and the diffusion layer was formed by long-time H1 heat treatment sintering after accumulation of the At wiring layer. However, with the increasing integration of LSIs, contact holes have become smaller and smaller than 1μ, and diffusion layers have become smaller than α3.
In VL8 manufacturing, which requires a bond shallower than µm,
Long-term H2 sintering (e.g. 450℃ 20 minutes)
Heat treatment has the problem of penetration from the shallow diffusion layer of the At wiring to the silicon substrate, and furthermore, when AtE]i is used for the wiring, there is a problem of contact failure due to solid phase growth of 81 in fine contact holes, which reduces the yield of LSI. The present invention eliminates such conventional drawbacks, avoids penetration in the shallow diffusion layer of At wiring, prevents contact failure in minute contacts, and provides stable gate and field 8.
The present invention aims to provide a method for manufacturing MO8-FIT that provides a 10,·81 interface.
上記目的を達成するため、本発明による熱処理は、８１
０！と８１の界面を安定化させるための長時間Ｈ７熱処
理（例えば ４８０℃ ３０分）を、Ａｔ層蓄積前に行
ない、ＡｔまたはＡＡ−Ｓ１配線層と拡散層のオーミッ
ク−コンタクト形成の短時間熱処理（例えば４５０℃１
５秒〜３０秒）を、ｈＬｆｋ！Ｉｌａ層形成後に行なう
ことを特徴としている。In order to achieve the above object, the heat treatment according to the present invention
0! A long-time H7 heat treatment (e.g., 480°C for 30 minutes) to stabilize the interface between and 81 is performed before the At layer accumulation, and a short-time heat treatment (for example, 480°C for 30 minutes) to form an ohmic contact between the At or AA-S1 wiring layer and the diffusion layer is performed. For example, 450℃1
5 seconds to 30 seconds), hLfk! It is characterized by being carried out after the formation of the Ila layer.
以下、実施例にて説明する。Examples will be described below.
表１は、従来技術によるＭＯＳ−ＦＩＴの製造方法のフ
ロー・チャートであり、第２図のＭＯＳ・ＦＦ１Ｔ断面
図に示すごとくウェル・フィールド２１ゲート膜４・ゲ
ー）１１Ｕ極５・ソース・ドレイン拡散層３形成後、表
１■において第２フイールド６にコンタクトホールを形
成し、次にＡｔ配線ＪｖＩ７を形成後、長時間熱処理Ｈ
２シンタリングを行すっている。Ｈ２シンタリングは、
Ａｔと拡散層のオーミック・コンタクト形成とゲートお
よびフィールド領域の８１と８１０２の界面に存在する
Ｓ１＋やダングリング・ボンドを安定化する役目を果し
ている。しかしながら、Ｓｌと８１０゜界面の安定化に
は長時間熱処理が必要なことと、短時間熱処理を可能に
する装置が存在しなかったため、該Ｈ２シンタ廿はｌ長
時間熱処理（例えば、４５０℃３０分）を行なってきた
。このため、高集積度ＬＳＩに必要とされる浅い接合の
拡散層においてＡｔのつき抜けによるリーク不良が発生
する。また、微小コンタクトにおいてはＡｔ−８１の８
１による固相成長によりコンタクト不良が生じる。従っ
て、コンタクト・ホールの微小化・拡散接合深さの微小
化に制限を与え、ＬＳＩの高集積化を困難にしている。Table 1 is a flow chart of a method for manufacturing MOS-FIT according to the conventional technology, and as shown in the cross-sectional view of MOS/FF1T in Fig. 2, the well field 21 gate film 4 11U pole 5 source/drain diffusion After forming the layer 3, a contact hole is formed in the second field 6 in Table 1■, and then an At wiring JvI7 is formed, followed by long-term heat treatment H.
2. Sintering is performed. H2 sintering is
It serves to form an ohmic contact between At and the diffusion layer, and to stabilize S1+ and dangling bonds existing at the interface between 81 and 8102 in the gate and field regions. However, since long-term heat treatment was required to stabilize the 810° interface with Sl, and there was no equipment that could perform short-time heat treatment, the H2 sinter area had to undergo long-time heat treatment (e.g., 450°C, 30°C). minutes). For this reason, leakage defects occur due to penetration of At in the shallow junction diffusion layer required for highly integrated LSIs. In addition, for microcontacts, At-81's 8
Contact failure occurs due to solid phase growth due to No. 1. Therefore, this limits the miniaturization of contact holes and the depth of diffusion junctions, making it difficult to achieve high integration of LSIs.
表２は、本発明によるＭＯＳ・ＦＫＴの製造方法のフロ
ーチャートであり、■番目のイオン注入層のアニールま
では従来の方法と同じである。Table 2 is a flowchart of the method for manufacturing a MOS/FKT according to the present invention, and the steps up to the annealing of the ■th ion-implanted layer are the same as the conventional method.
本発明においては、Ｈ２雰囲気中での長時間熱処理をＡ
ｔ配線形成前に行なっている。表２では、第１図のＭＯ
Ｓ・ＦＩＤＴの断面図に示すごとくコンタクト・ホール
形成後に長時間熱処理を行なっているが、コンタクト・
ホール形成前でも良い。In the present invention, long-term heat treatment in an H2 atmosphere is
This is done before forming the t-wiring. In Table 2, the MO of Figure 1 is
As shown in the cross-sectional view of the S-FIDT, long-term heat treatment is performed after contact holes are formed, but the contact
It may be done even before the hole is formed.
従って、Ａｔの浅い拡散接合でのつき抜けはあり得ない
ため、高温長時間（例えば、４８０℃。６０分）のＨ６
熱処理を行なうことができ、’Ｓ ｉ Ｏ。Therefore, since it is impossible for At to penetrate through shallow diffusion bonding, H6
Heat treatment can be performed, 'S i O.
と８１との界面の８１＋やダングリングボンドを化学的
に安定化させるに充分な熱処理時間と温度が確保できる
。次に第２図のＭＯＳ・ＦＩＴの断面図に示すごと＜ｈ
ｔ配線層７を形成後、ノ・ロゲン・ランプ、グラファイ
ト・ヒータなどの瞬間アニール装置により、短時間熱処
理を行なう。この熱処理は、真空中・窒素雰囲気中・水
素雰囲気中のいずれでも可能である。熱処理（例えば、
４５０℃、１０秒）において、ＡＡ−８ｉの８１が固相
成長するには、時間が少なすぎるため、微小コンタクト
ホールにおいてもコンタクト不良は生じない。また、０
．３μ惧以下の浅い接合を持つ拡散層においてもＡｌの
つき抜けは生じない。さらに、短時間熱処理によるコン
タクト抵抗のウェーッ・内のばらつきは、長時間熱処理
に比べてずつと小さい。従って、本発明によれば、８１
０□と８１界面が安定して電気特性のばらつきが少ない
、しかも浅い接合を持つ拡散層と微小フンタクトホール
に制限を与えないＭＯＳ・’ＦＥＴの制造が可能になる
。A heat treatment time and temperature sufficient to chemically stabilize 81+ and dangling bonds at the interface between and 81 can be secured. Next, as shown in the cross-sectional view of the MOS/FIT in Figure 2,
After forming the t-wiring layer 7, heat treatment is performed for a short time using an instantaneous annealing device such as a nitrogen lamp or a graphite heater. This heat treatment can be performed in a vacuum, in a nitrogen atmosphere, or in a hydrogen atmosphere. Heat treatment (e.g.
450° C. for 10 seconds), the time is too short for 81 of AA-8i to grow in a solid phase, so no contact failure occurs even in minute contact holes. Also, 0
．． Even in a diffusion layer having a shallow junction of 3 μm or less, no penetration of Al occurs. Furthermore, the within-wafer variation in contact resistance due to short-time heat treatment is much smaller than that due to long-time heat treatment. Therefore, according to the invention, 81
It is possible to manufacture a MOS/'FET with a stable 0□ and 81 interface with little variation in electrical characteristics and without restrictions on the diffusion layer and microscopic holes with shallow junctions.
以上説明したように、本発明は、高集積！ＬＳ■を可能
にするＭＯＳ・ＦＦ１Ｔの製造方法を与える。As explained above, the present invention is highly integrated! A method for manufacturing MOS/FF1T that enables LS■ is provided.
く表−１〉 従来のＭＯＢ会ＦＥＴ製造フロー・チャー
ト
く表−２〉 本発明によるＭＯ８・ＦＦ１Ｔ製造フロー
・チャートTable 1〉 Conventional MOB FET manufacturing flow chart Table 2〉 MO8/FF1T manufacturing flow chart according to the present invention
第１図・・・・・・Ａｔ配線形成前のＭＯ８−ＦＩＴ断
面図
第２図・・・・・・Ａｔ配線形成後のＭＯ８・ＦＢＡＴ
断面図
１・・・・・・８１基板
２・・・・・・Ｓｉｎ、（ＬＯＣ！０８）３・・・・・
・ソース・ドレイン領域
４・・・・・・ゲート膜
５・・・・・・Ｐｏ１ｙ ８１ ゲート電極６・・・・
・・８１０゜
７・・・・・・Ａｔ配線
以 上
出願人 株式会社諏訪精工舎
代理人 弁理士 最上 務Figure 1: Cross-sectional view of MO8-FIT before At wiring formation Figure 2: MO8-FBAT after At wiring formation
Cross-sectional view 1...81 Substrate 2...Sin, (LOC!08)3...
・Source/drain region 4...Gate film 5...Poly 81 Gate electrode 6...
・・・810゜7・・・・・・At wiring or above Applicant Suwa Seikosha Co., Ltd. Agent Patent attorney Tsutomu Mogami
Claims (1)
において、Ａｔ配線層の形成以前に長時間高温水素熱処
理（４５０℃以上 １５分以上）を行ない、ｈ、Ｌ配線
層形成後に短時間Ｎ２またはＨ２熱処理シンタリングを
行なうことを特徴とする半導体装置の製造方法。In manufacturing LSIs consisting of MOS @FKT with AA wiring, long-term high-temperature hydrogen heat treatment (450°C or higher, 15 minutes or more) is performed before the formation of the At wiring layer, and short-time N2 or H2 heat treatment sintering is performed after the formation of the h and L wiring layers. A method for manufacturing a semiconductor device, characterized by performing a ring process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11051883A JPS601869A (en) | 1983-06-20 | 1983-06-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11051883A JPS601869A (en) | 1983-06-20 | 1983-06-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS601869A true JPS601869A (en) | 1985-01-08 |
Family
ID=14537822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11051883A Pending JPS601869A (en) | 1983-06-20 | 1983-06-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS601869A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62196870A (en) * | 1986-02-24 | 1987-08-31 | Seiko Epson Corp | Manufacture of semiconductor device |
| US6114236A (en) * | 1996-10-17 | 2000-09-05 | Nec Corporation | Process for production of semiconductor device having an insulating film of low dielectric constant |
| KR100486229B1 (en) * | 1998-02-02 | 2005-08-05 | 삼성전자주식회사 | Method for tisix silicide gate transistor forming using hydrogen anneal |
-
1983
- 1983-06-20 JP JP11051883A patent/JPS601869A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62196870A (en) * | 1986-02-24 | 1987-08-31 | Seiko Epson Corp | Manufacture of semiconductor device |
| US6114236A (en) * | 1996-10-17 | 2000-09-05 | Nec Corporation | Process for production of semiconductor device having an insulating film of low dielectric constant |
| KR100486229B1 (en) * | 1998-02-02 | 2005-08-05 | 삼성전자주식회사 | Method for tisix silicide gate transistor forming using hydrogen anneal |
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