JPH04116820A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of a leakage when a diffused layer is formed shallow and to prevent the resistance of the diffused layer form being made to rise by a method wherein ions of the constituent substance of a substrate are implanted in the substrate to form a region where crystal lattices are disordered, ions are implanted in a region deeper than this region through the substrate surface to form the diffused layer and with an activation of the diffused layer performed by a heat treatment, the region where crystal lattices are disordered, is made to recrystallize. CONSTITUTION:Si ions are implanted in an Si substrate 1 to form a region 7 brought into an amorphous state, then, BF2 ions, for example, are implanted in a region deeper than the region 7 through the surface of the substrate 1 to form a diffused layer 8. Then, a layer insulating film 9 consisting of an SiO2 film 9a and a BPSG film 9b is formed and thereafter, with an activation of the layer 8 performed by a heat treatment, the region 7 is made to recrystallize. At this time, a reflow of the film 9 is also performed.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, it is possible to make a diffusion layer that becomes a source/drain shallow (when forming it, it is possible to make it difficult to cause leakage due to defects that tend to gather at the edge of a field oxide film, The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can form a shallow and stable diffusion layer even if heat treatment is performed without increasing the resistance of the diffusion layer. a step of implanting ions to form a region in which the crystal lattice is disordered, a step of implanting ions into a region deeper from the substrate surface than the region in which the crystal lattice is disordered to form a diffusion layer; , activating the diffusion layer by heat-treating the substrate and recrystallizing the region where the crystal lattice is disturbed, or implanting ions into the semiconductor substrate and diffusing them. a step of forming a layer, then a step of implanting ions made of a constituent material of the substrate into a region shallower from the surface of the substrate than the diffusion layer to form a region in which the crystal lattice is disordered; The method is configured to include the steps of activating the diffusion layer by heat-treating and recrystallizing the region in which the crystal lattice is disturbed.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device having high reliability.

In recent years, the degree of integration of semiconductor devices has continued to increase year by year, but the size of the elements cannot be increased, so the size of the constituent elements must inevitably be reduced.

As the size of an element becomes smaller, the amount of charge that can be stored as a memory becomes smaller, for example when considering a memory device. For this reason, if a leak occurs in an element, for example, a MOSFET, when it is on standby, the stored charge as information is easily lost. To prevent this, for example,
(namic) RAM and the like perform an operation called refresh to retain information. However, if the leakage current is too large, a refresh failure may occur, where memory information cannot be retained even by a refresh operation.

This is already happening with devices that are currently being mass-produced. In particular, as device miniaturization progresses, MO
The junction depth of the source and drain of the SFET becomes shallow. In this case, the depletion layer formed by the PN junction invades into the inside of the junction, and this can become the biggest cause of leakage due to defects or contamination during the formation of the junction inside the junction. Note that even when the PN junction is deep, the depletion layer may invade into the inside of the junction. However, in the case where the PN junction is deep, because it is "deep", its influence does not appear at all.

In other words, it is important not to introduce contamination into the manufacturing process, but it is necessary to consider what would happen if contamination does occur, and in particular, there is a need for a semiconductor device manufacturing method that can perform gettering during junction formation. has been done.

[Conventional technology]

FIG. 5 is a diagram illustrating a conventional method of manufacturing a semiconductor device. The illustrated manufacturing method can be applied to a method of manufacturing MO3) transistors. In Figure 5, 31 is S
32 is a silicon oxide film made of Sing etc., 33 is a silicon nitride film made of 5isNa etc., 33a is a mask formed by patterning the silicon nitride film 33, and 34 is a silicon nitride film 33. 35 is a channel stopper, 36 is S
37 is a diffusion layer that becomes a source/drain diffusion layer, etc.; 38 is a film of Sin;
8a, an interlayer insulating film 39 consisting of a BPSG film 38b, etc.
40 is a contact hole formed in the interlayer insulating film 38;
is in contact with the diffusion layer 37 through the contact hole 39! It is a wiring layer consisting of etc.

Next, the manufacturing method will be explained.

First, using an n-type Si substrate 31 shown in FIG. 5(a),
As shown in FIG. 5(b), the substrate 3 is removed by thermal oxidation, for example.
After oxidizing 1 to form a silicon oxide film 32, as shown in FIG.
form.

Next, as shown in FIG. 5(d), the silicon nitride film 33 is selectively etched by RIE, for example, so that only the element region remains, and a mask 33a for forming a field oxide film is etched.
After forming an opening 34 in which the silicon oxide film 32 is exposed, for example, P is implanted into the substrate 31 through the opening 34 using a mask 33a by ion implantation of P.
is introduced to form the channel stopper 35.

Next, as shown in FIG. 5(e), the field oxide film 36 is formed by selectively oxidizing the substrate 31 by thermal oxidation using the mask 33a.

Next, as shown in FIG. 5(f), the mask 3a made of 5isN and the silicon oxide film 32 are removed by, for example, wet etching.

Next, as shown in FIG. 5(g), for example, BF8.10
BF2 is introduced into the substrate 31 by ion implantation of KeV, 1×10 s (J − ”) to form a diffusion layer 37 that becomes a source/drain diffusion layer.

Next, as shown in FIG. 5H, a null interlayer insulating film 38 is formed from the Sin film 38a and the BPSG film 38b by sequentially depositing Sing and BPSG on the entire surface by, for example, the CVD method. Then, for example, by RIE, the BPSG film 38 is
After selectively etching the interlayer insulating film 38 consisting of the film 38a and the film 38a to form a contact hole 39 in which the diffusion layer 37 is exposed, a layer A1 is etched to make contact with the diffusion layer 37 through the contact hole 39. By forming the wiring layer 40, a structure of the wiring layer 40 in which the diffusion layer 37 is contacted through the contact hole 39 as shown in FIG. 5(i) can be obtained.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above, in order to meet the recent demand for miniaturization, that is, the demand for shallower source/drain junction depths, the diffusion layer 37, which becomes the source/drain diffusion layer, is, for example, It was formed by ion implantation of BF at low energy of KeV,
If an attempt is made to form the diffusion layer 37 shallowly, there is a problem in that leakage is likely to occur due to defects that tend to gather at the edge portion of the field oxide film 36. If leakage is likely to occur in this way, the charge representing information stored in the capacitor of the memory element is easily lost, so more refresh operations have to be performed.

In addition, conventional techniques for forming a shallow diffusion layer include carbon (C) or argon (Ar) ions, or H'
One method is to inject (protons) into a Si substrate in advance to form an amorphous region on the substrate and form a diffusion layer within that region, but when carbon or Ar is injected into the Si substrate, There is a problem in that the resistance of the diffusion layer that becomes the source/drain becomes high, and in the case of using H, H quickly escapes when heat treatment is applied, making it difficult to form a shallow diffusion layer. was there.

Therefore, the present invention makes it possible to make it difficult to cause leakage due to defects that gather at the edge of the field oxide film when forming a shallow diffusion layer to serve as a source/drain, and to perform heat treatment without increasing the resistance of the diffusion layer. The object of the present invention is to provide a method for manufacturing a semiconductor device that can stably form a shallow diffusion layer even if the diffusion layer is mixed.

[Means to solve the problem]

In order to achieve the above object, a method for manufacturing a semiconductor device according to a first aspect of the invention includes a step of implanting ions made of a constituent material of the substrate into a semiconductor substrate to form a region in which the crystal lattice is disordered;
Next, a step of implanting ions into a region deeper from the surface of the substrate than the region where the crystal lattice is disturbed to form a diffusion layer, and then activating the diffusion layer by heat treating the substrate. , recrystallizing the region in which the crystal lattice is disturbed.

In order to achieve the above object, a method for manufacturing a semiconductor device according to a second aspect of the invention includes a step of implanting ions into a semiconductor substrate to form a diffusion layer, and then forming a region of the substrate shallower than the diffusion layer from the surface of the substrate. A step of implanting ions of a constituent material to form a region in which the crystal lattice is disordered, and then activating the diffusion layer by heat-treating the substrate and forming a region in which the crystal lattice is disordered. This includes a step of recrystallization.

Examples of the semiconductor substrate according to the present invention include Si, ions of the substrate constituent material include Si ions, and ions for forming the diffusion layer include BF and ions.

In the present invention, forming a region in which the crystal lattice is disordered may mean forming a region in which the crystal lattice is disordered, or may be in the case of forming an amorphous region.

[Effect]

In the present invention, as shown in FIG. 1, since the amorphous region 7 is formed in the diffusion layer 8, the second
As shown in the X part shown in FIG.
A crystal interface will exist. When heat treatment is applied in this state, recrystallization starts from the amorphous/crystal interface. At this time, since the amorphous/crystal interface is rough, impurities present in a shallow region from the surface of the substrate 1 can be gettered at the interface as indicated by arrow Y shown in FIG. 2(b). Therefore, defects can remain at the interface after heat treatment.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams for explaining an embodiment of the method for manufacturing a semiconductor device according to the present invention, FIG. 1 is a diagram for explaining the method for manufacturing a semiconductor device according to the embodiment, and FIGS. FIG. 2 is a diagram illustrating the effects of one embodiment. In these figures, ■ is a substrate made of Si, etc., for example, an n-type (100) 1Ω substrate, 2 is a silicon oxide film made of SiO□, etc., 3 is a silicon nitride film made of Si3N, etc., and 3a is a silicon nitride film. 3 is a mask formed by patterning, 4 is an opening formed in silicon nitride film 3, 5 is a channel stopper, and 6 is S
7 is an amorphous region formed on the substrate l, 8 is a diffusion layer that becomes a source/drain, 9 is a BPSG film 9b and a Sin,
10 is a contact hole formed in the interlayer insulating film 9, and 11 is a wiring layer made of A1 etc. which is in contact with the diffusion layer 8 through the interlayer insulating film 9.

Next, the manufacturing method will be explained.

First, the n-type (100) 1Ωl S shown in Figure 1(a)
Using the substrate 1, as shown in FIG. 1(b), after oxidizing the substrate 1 by, for example, thermal oxidation (CVD method may also be used) to form a silicon oxide film 2 having a thickness of, for example, 200, As shown in FIG. 1(c), Si is deposited on the silicon oxide film 2 by, for example, the CVD method.

A silicon nitride film 3 having a thickness of, for example, 1,500 wafers is formed by depositing N4.

Next, as shown in FIG. 1(d), the silicon nitride film 3 is selectively etched by RIE, for example, so that only the element region remains, thereby forming a mask 3a for forming a field oxide film, and After forming an opening 4 in which 2 is exposed, e.g. P, 40 KeV, 2XIQ"
P is introduced into the substrate 1 through the opening 4 using the mask 3a by ion implantation of cn-'' to form the channel stopper 5.

Next, as shown in FIG. 1(e), the substrate 1 is selectively oxidized by steam oxidation using the mask 3a through the opening 4 to form a field oxide film 6 having a thickness of, for example, 3000.

Next, as shown in FIG. 1(f), the mask 3a made of Si and N4 and the silicon oxide film 2 are removed by, for example, wet etching.

Next, as shown in FIG. 1(g), for example, Si, 20
Si ions are implanted into the substrate 1 by KeV, 5×10” ion implantation to form an amorphous region 7.

Next, as shown in FIG. 1(h), for example, BF2.10
A diffusion layer 8 is formed by implanting BP and ions into a region deeper from the surface of the substrate 1 than the region 7 which has been made amorphous by the ion implantation of KeV, IXIO "am-".

Next, as shown in FIG. 1(i), SiO□ and BPSG are sequentially deposited on the entire surface by, for example, the CVD method to form a SiO□ film 9a with a thickness of, for example, 2000, and a SiO□ film 9a with a thickness of, for example, 500.
After forming the glabellar insulating film 9 made of the BPSG film 9b, the diffusion layer 8 is activated by heat treatment at, for example, 850° C. for 50 minutes, and the amorphous region 7 is recrystallized. At this time, the glabellar insulating film 9 is also reflowed.

Then, the BPSG film 9b and Si
After selectively etching the glabella insulating film 9 consisting of O, film 9a to form a contact hole E0 in which the diffusion layer 8 is exposed, a layer of aluminum is etched so as to make contact with the diffusion layer 8 through the contact hole 10. By forming the wiring layer 11, the wiring layer 1 is contacted with the diffusion layer 8 through the contact hole lO as shown in FIG. 1(j).
1 structure can be obtained.

That is, in the above embodiment, Si ions made of the constituent material of the substrate 1 are implanted into the Si substrate 1 to form an amorphous region 7, and BF2 ions are implanted in a region deeper from the surface of the substrate 1 than the amorphous region 7. By injecting and heat-treating, the diffusion layer 8 is formed, and the amorphous region 7 is recrystallized. Since the amorphous region 7 is thus formed in the diffusion layer s, an amorphous/crystal interface exists in the diffusion layer 8 as shown in the X section shown in FIG. 2(a). When heat treatment is applied in this state, recrystallization starts from the amorphous/crystal interface. At this time, since the amorphous/crystal interface is rough, impurities present in a shallow region from the surface of the substrate can be gettered at the interface, as indicated by arrow Y shown in FIG. 2(b). Therefore, defects can remain at the interface after heat treatment.

Therefore, when the diffusion layer 8 is formed shallowly, impurities present in a shallow region from the surface of the substrate 1 can be captured in a place (amorphous/crystal interface) out of the reach of the depletion layer in the diffusion layer 8. As shown in Figure 3(b), compared to the conventional BF shown in a), when only ions were implanted,
It is possible to make it difficult to cause leakage (due to defects that tend to gather in the oxide portion of the field oxide film 6). Note that the junction depth is 0.13 μm in both cases, and the resistance value of the diffusion layer 8 is 3 in both cases.
00 Ω/hole, and there is no increase in the resistance of the diffusion layer 8 as in the case of conventional implantation of carbon or Ar into a Si substrate, and there is no increase in the resistance of the diffusion layer 8, unlike in the case of conventional implantation of carbon or Ar into a Si substrate. There is no dropout, and the diffusion layer 8 can be formed shallowly and stably.

In the above embodiment, the case where the diffusion layer 8 is formed after forming the amorphous region 7 has been described, but the present invention is not limited to this, and as shown in FIG.
As shown in a) and (b), the amorphous region 7 may be formed after the diffusion layer 8 is formed, and in this case as well, the diffusion layer 8 is heated by heat treatment as in the above embodiment. Activation and recrystallization of the amorphous region 7 are performed simultaneously.

〔Effect of the invention〕

According to the present invention, when forming a shallow diffusion layer to serve as a source/drain, it is possible to make it difficult to cause leakage due to defects that tend to accumulate at the edge of a field oxide film, and heat treatment can be performed without increasing the resistance of the diffusion layer. This has the effect that a shallow and stable diffusion layer can be formed even if the diffusion layer is mixed.

FIG. 1 is a diagram for explaining the manufacturing method of one embodiment, FIGS. 2 and 3 are diagrams for explaining the effects of one embodiment, FIG. 4 is a diagram for explaining the manufacturing method of another embodiment, and FIG. FIG. 5 is a diagram illustrating a conventional manufacturing method.

1...Substrate, 7...Amorphous region, 8...
...Diffusion layer.

[Brief explanation of drawings]

1 to 3 are diagrams for explaining one embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a diagram for explaining the effects of one embodiment. Supply voltage (V) (a) Supply voltage (V) (b) Figure 3 for explaining the effects of one embodiment Figure 4 for explaining the manufacturing method of another embodiment

Claims (2)

[Claims] (1) A step of implanting ions made of a constituent material of the substrate (1) into the semiconductor substrate (1) to form a region (7) in which the crystal lattice is disordered, and then a region in which the crystal lattice is disordered. Ions are implanted into a region deeper from the surface of the substrate (1) than in the diffusion layer (8).
), and then heat-treating the substrate (1) to activate the diffusion layer (8) and recrystallize the region (7) in which the crystal lattice is disturbed. A method for manufacturing a semiconductor device, comprising: (2) Ions are implanted into the semiconductor substrate (1) and the diffusion layer (8
), and then implanting ions made of a constituent material of the substrate (1) into a region shallower from the surface of the substrate (1) than the diffusion layer (8) to form a region in which the crystal lattice is disturbed ( 7), and then activating the diffusion layer (8) by heat-treating the substrate (1) and recrystallizing the region (7) in which the crystal lattice is disturbed. A method for manufacturing a semiconductor device, comprising: