JPS60182759A - 論理回路 - Google Patents

論理回路

Info

Publication number
JPS60182759A
JPS60182759A JP59037460A JP3746084A JPS60182759A JP S60182759 A JPS60182759 A JP S60182759A JP 59037460 A JP59037460 A JP 59037460A JP 3746084 A JP3746084 A JP 3746084A JP S60182759 A JPS60182759 A JP S60182759A
Authority
JP
Japan
Prior art keywords
voltage
fet
load
vbi
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59037460A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0428179B2 (cg-RX-API-DMAC7.html
Inventor
Katsuhiko Suyama
須山　勝彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59037460A priority Critical patent/JPS60182759A/ja
Priority to KR1019850001065A priority patent/KR890004454B1/ko
Priority to US06/705,321 priority patent/US4656611A/en
Priority to CA000475169A priority patent/CA1246694A/en
Priority to DE8585301311T priority patent/DE3580496D1/de
Priority to EP85301311A priority patent/EP0153860B1/en
Publication of JPS60182759A publication Critical patent/JPS60182759A/ja
Publication of JPH0428179B2 publication Critical patent/JPH0428179B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
    • H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Static Random-Access Memory (AREA)
JP59037460A 1984-02-29 1984-02-29 論理回路 Granted JPS60182759A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP59037460A JPS60182759A (ja) 1984-02-29 1984-02-29 論理回路
KR1019850001065A KR890004454B1 (ko) 1984-02-29 1985-02-21 논리회로
US06/705,321 US4656611A (en) 1984-02-29 1985-02-22 Logic circuit
CA000475169A CA1246694A (en) 1984-02-29 1985-02-26 Logic circuit
DE8585301311T DE3580496D1 (de) 1984-02-29 1985-02-27 Logische schaltung.
EP85301311A EP0153860B1 (en) 1984-02-29 1985-02-27 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59037460A JPS60182759A (ja) 1984-02-29 1984-02-29 論理回路

Publications (2)

Publication Number Publication Date
JPS60182759A true JPS60182759A (ja) 1985-09-18
JPH0428179B2 JPH0428179B2 (cg-RX-API-DMAC7.html) 1992-05-13

Family

ID=12498133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59037460A Granted JPS60182759A (ja) 1984-02-29 1984-02-29 論理回路

Country Status (6)

Country Link
US (1) US4656611A (cg-RX-API-DMAC7.html)
EP (1) EP0153860B1 (cg-RX-API-DMAC7.html)
JP (1) JPS60182759A (cg-RX-API-DMAC7.html)
KR (1) KR890004454B1 (cg-RX-API-DMAC7.html)
CA (1) CA1246694A (cg-RX-API-DMAC7.html)
DE (1) DE3580496D1 (cg-RX-API-DMAC7.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3569859D1 (en) * 1985-12-24 1989-06-01 Fujitsu Ltd Logic circuit
US6127857A (en) * 1997-07-02 2000-10-03 Canon Kabushiki Kaisha Output buffer or voltage hold for analog of multilevel processing

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5080734A (cg-RX-API-DMAC7.html) * 1973-11-14 1975-07-01

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2657561B1 (de) * 1976-12-18 1978-04-13 Ibm Deutschland Nachlade-Referenzschaltungsanordnung fuer einen Halbleiterspeicher
US4355377A (en) * 1980-06-30 1982-10-19 Inmos Corporation Asynchronously equillibrated and pre-charged static ram

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5080734A (cg-RX-API-DMAC7.html) * 1973-11-14 1975-07-01

Also Published As

Publication number Publication date
JPH0428179B2 (cg-RX-API-DMAC7.html) 1992-05-13
DE3580496D1 (de) 1990-12-20
KR890004454B1 (ko) 1989-11-04
CA1246694A (en) 1988-12-13
EP0153860A2 (en) 1985-09-04
US4656611A (en) 1987-04-07
KR850006789A (ko) 1985-10-16
EP0153860A3 (en) 1987-09-30
EP0153860B1 (en) 1990-11-14

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