JPS60181837A - Processing system for execution instruction - Google Patents

Abstract

PURPOSE:To execute an instruction following an execution instruction and successively after a subject instruction by using two instruction reading registers to store a series of instructions including the execution instruction to one of both registers and the subject instruction of the execution instruction to the other register. CONSTITUTION:In the 1st flow showing execution of an execution instruction, a series of instructions read out of a memory are stored to the 1st instruction reading register 16 and then extracted by a selector 2. In the 2nd flow showing the execution of a subject instruction, an exclusive OR is obtained by an exclusive OR circuit 14 between the 1st and 2nd operands to obtain the subject instruction. This subject instruction is extracted by the selector 2. In the 3rd flow showing execution of an instruction following the execution instruction, the selector 2 selects the register 16 again and extracts an instruction following the execution instruction out of the register 16. These instructions extracted by the selector 2 are sent to a pipeline and executed.

Description

[Detailed description of the invention] A1 Technical field of invention The present invention relates to an execute instruction processing method, and particularly to an execute instruction processing method.

The present invention relates to an execute instruction processing method in an information processing device using pipeline control.

B. Conventional technology and its problems An information processing device using a pipeline control method.

In order to execute instructions consecutively, the instructions are read from the JQ device before the instruction is executed, and the read instructions are stored in an instruction read register, which are sequentially retrieved to execute a series of instructions. are doing.

In a pleasure processing device using a pipeline control method, when executing a series of instructions as shown in Figure 1, if there is an execute instruction among the instructions and this instruction is executed, the series of instructions will be executed. It deviates from the instruction root and moves to the instruction specified by the operand of the execute instruction, that is, the subject (SUBJECT) instruction. After executing this subject instruction, it returns to the instruction next to the execute instruction and returns to the original instruction. An instruction execution process that returns to a series of instruction routes may be adopted.

According to the conventional method for processing execute instructions, only one instruction read register is provided to store the instruction, so when the execute instruction is executed, the subject instruction is read from the storage device. When the instruction was read and stored in the instruction read register, the contents of the instruction read register were rewritten, and some or all of the previously stored instructions after Excue 1 and the next instruction were lost. . Therefore, when executing the instruction following the execute instruction, this instruction must be read from the storage device to the instruction read register again, so the instruction following the execute instruction must be executed in succession to the subject instruction. Therefore, the pipeline was stopped while the secondary instruction was read out again.

The above 1R will be explained in detail based on FIG. FIG. 2 is a timing chart showing, using a block diagram, the execution state of the command to EXQ 1, its subject command, and the next command after the EXQ L-1 command. In the figure, the passage of time is shown from left to right.
■, Do r, IB, D.

A, T, B, E, and W represent each stage of instruction execution.

A case will be described in which an execute command of the format shown in FIG. 3 is processed. This execute instruction does not indicate an operation code. Department and.

Part 11 indicating the first operand and +2 indicating the second operand. This instruction executes the instruction stored at the address specified by the second operand after modifying it with the contents of the first operand.

In FIG. 2, the first flow (the top flow in the diagram) shows execution of an execute instruction. A series of a plurality of instructions read from the storage device are taken out from the instruction read register 1 in which they are stored, by the selector 2, and sent to the vibe line. Excue 1 ~ When an instruction is fetched.

A register is selected from the register stack 3 according to the contents of parts 12 and 13 (designating a register) of the second operand of this execute instruction, and the contents of the selected register are stored in registers 4 and 5, respectively. On the other hand, the 14th part of the second operand of the Excue 1 instruction is:
It is sent to register 6 and stored. The contents of registers 4, 5, and 6 are sent to address 3+ arithmetic unit 7, and these contents are added to obtain the second operand address of the subject instruction.

On the other hand, the 15th part of the first operand of the execute instruction (
(specifying a register) is sent as register 8゜9, ]0, selects a register from register stack J1, sets the first operand of the resoject instruction, and sends register 8゜9, ]0.
Store in.

In Figure 2, the second flow (the flow in the center of the diagram)
indicates the execution of the Zabrzek I instruction. In the first fj:l-, data is read from the storage device 13 based on the second operand address determined by the arithmetic unit 7, and the contents of the address (second operand of the subject instruction) are read.
) is stored in the instruction read register 1. the result,
The contents of the instruction read register 1 are rewritten, and some or all of the instructions following the previously stored execute instruction are lost.

The first of the subject instructions stored in register 12
The exclusive OR circuit 14 performs exclusive OR on the operand and the second operand of the subject instruction stored in the instruction read register 1. The output of the exclusive OR circuit 14 is.

Configure a subject instruction. This subject instruction is taken out by the selector 2, sent to the pipeline, and executed as an instruction word.

In FIG. 2, the third flow (the bottom flow in the diagram) shows execution of the instruction following the Excue 1 instruction. The address of the execute instruction is stored in the register 15, and the arithmetic unit 7 adds, for example, 8 high 1- to this address to calculate the address of the next instruction after the execute instruction.

The contents of the 9-instruction read register 1, which reads the contents of the address from the storage device 13 and stores them in the instruction read register 1, are taken out by the selector 2 and sent to the pipeline for execution.

In the third flow, stage f, IT failure] B
This period is used to calculate the next instruction C address of the Excue 1 instruction and to prevent the next instruction stored at that address from being read out from the storage device 13 again. During this period, the pipeline is It will stop. Therefore, the conventional execute instruction processing method 2 has the disadvantage that it is not possible to execute the instruction following the execute instruction immediately after the subject instruction.

Purpose and structure of C9 invention The object of the present invention is to improve the above-mentioned drawbacks.

The object of the present invention is to provide an Efski, -1-instruction processing method that enables the execution of an instruction following the Efski, 1-) instruction following a subject instruction.

The present invention provides a first instruction read register for storing a plurality of series of instructions read from a memory section, and a first instruction read register for storing a plurality of series of instructions read from a memory section in an execu-1 to instruction processing method in an information processing apparatus using pipeline control. an arithmetic unit that calculates the address of the subject instruction of the execute instruction from the operand of the execute instruction when there is an execute instruction in a series of instructions taken out from the register; and a calculation unit that reads the address of the subject instruction of the execute instruction from the memory unit using the calculated address. The present invention is characterized by comprising a second instruction read register that stores a subject instruction that has been executed, and a selector section that selects the first and second instruction read registers.

D0 Embodiment of the Invention FIG. 4 is a diagram showing an embodiment of the execute command processing method of the present invention. Similar to FIG. 2, the block diagram is shown in the form of a time chart.

The difference from the conventional method shown in FIG. 2 is that it has two instruction read registers, and a series of instructions read from the storage device is stored in one instruction read register, and the subject instruction read from the storage device is stored in one of the instruction read registers. The second operand of is stored in the other instruction read register. In the figure.

Elements that are the same as in FIG. 2 are designated by the same numbers.

Similar to the description of the execute command processing method shown in FIG. 2, this embodiment will be described with reference to the case where the execute command has a format as shown in FIG. 3.

In a first flow showing execution of an execute instruction, a series of instructions read from a storage device is
It is stored in the instruction read register 16. These instructions are taken out by the selector 2 and sent to the pipeline. When an execute instruction is fetched, a register is selected from register stack 3 according to the contents of parts 12 and 13 (specifying the register) of the second operand of this execute instruction, and the contents of the selected register are transferred to register 4. and 5 respectively.

On the other hand, 14 parts of the second operand of the execute instruction are sent to register 6 and stored therein. Register 4.5.6
The contents of are sent to the arithmetic unit 7 for address calculation, and these contents are added to obtain the second operand address of the subject instruction.

On the other hand, the 15th part of the first operand of the execute instruction (
(specifying a register) is sent as register 8.9.10, selects a register from register stack 11, stores the first operand of the subject 1 instruction, and stores it in register 12.

In the second flow showing the flow of execution of the subject instruction, in the first flow, reading is performed from the storage device 13 based on the second operand address determined by the arithmetic unit 7, (second operand) is stored in the second instruction read register 17. This content and the first operand of the subdirect instruction stored in the register 12 are added to the exclusive OR circuit 1.
In step 4, exclusive OR is performed to obtain the subject instruction. This subject instruction is taken out by the selector 2, sent to the pipeline, and executed as an instruction word.

In the third flow indicating execution of the next instruction after the execute instruction, the selector 2 selects the instruction read register 16.
is selected again and the instruction following the execute instruction is retrieved from this instruction read register. This retrieval occurs in the next stage following the first stage D of execution of the subject instruction. The next instruction taken out by selector 2 is sent to the pipeline and executed.

In the above embodiment, a case has been described in which the Excue 1 instruction is an instruction that executes an instruction with τ stored at an address specified by the second operand with modification by the contents of the first operand. It is clear that the contents stored in the second instruction read register 17 can be changed depending on the format of the Excue 1 instruction.

Effects of E9 invention According to the execute command processing method of the present invention.

It has two instruction read registers, one instruction read register stores a series of multiple instructions including an execute instruction, and the other instruction read register stores a subject instruction of the instruction to execute 1. When the subject instruction is stored, the instruction is stored in the one instruction read register and the instruction is not lost. Therefore, when executing the instruction following the execute instruction, the one instruction read register is selected. According to each.

It becomes possible to execute the next instruction after the execute instruction following the subject instruction. Therefore, instructions can be processed without stopping the pipeline.

[Brief explanation of drawings]

Fig. 1 is a diagram for explaining a series of instructions, Fig. 2 is a diagram for explaining the conventional execute command processing method, Fig. 3 is a diagram showing the format of Execute 1 to instructions, Fig. 4 FIG. 1 is a diagram for explaining one embodiment of the present invention. In the figure, 2 is a selector and 3 is a register stack. 4.5.6 is a register, 7 is an address calculation WL
8, 9.10 is a register, 11 is a register stack, 1
2 is a register, 13 is a storage device, 14 is an exclusive OR circuit, 15 is a register, 16 is a first instruction read register, and 17 is a second instruction read register. -3m

Claims (1)

[Claims] In an execute instruction processing method in an information processing device using pipeline control, a first instruction read register for storing a plurality of series of instructions read from a memory section; an arithmetic unit that calculates an address of a subject instruction of an execute instruction from an operand of the execute instruction when an execute instruction is included in a series of instructions taken out from the read register; An execute instruction comprising: a second instruction read register that stores a subject instruction read from the memory section according to the calculated address; and a selector section that selects the first and second instruction read registers. Processing method.