JPH01156824A - microprocessor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data processing technology and a technology that is particularly effective when applied to an instruction system in a program control system. The present invention relates to techniques that are effective for use in microprocessors that have instructions.

[Conventional technology]

Conventionally, microprocessors have arithmetic operations such as addition, subtraction, multiplication, division, and comparison, as well as logical product (AND) instructions.
Various logical operation instructions such as logical OR (OR) and exclusive OR (XOR) are provided. For example, published by Hitachi, Ltd., September 1982, "Hitachi Microcombi, SEMICON-DUCTERDA'I'A Bo"
OK, 8/16 bit micro combination, -ta J p91
4-I)919. It is described in pages 945 to 952, etc.

[Problem that the invention seeks to solve]

In the instruction system of conventional microprocessors, the type of operation is specified by an instruction (operation code). In other words, an instruction was prepared for each valley operation, and the type of operation was fixed in the program and could not be changed like data. Therefore, the program is OM (read-only memory).
When stored in FP3, it was impossible to change the operation. For example, in fields such as computer graphics, logical operations are applied to data in bit fields to create so-called fill-in or watermarks. When performing drawing processing such as, it will be easier to develop the program if the type of calculation can be dynamically determined while looking at the screen.

However, in conventional microprocessors, where the instructions are determined by the type of operation, in order to change the content of the operation process, the operation instructions in the program must be rewritten.
The problem was that the program lacked flexibility.

In addition, in order to determine the type of the next instruction or operation based on the result obtained by executing a certain instruction, it is necessary to list the instructions or operations that may be executed next in the program. .

That is, it is necessary to create a program that selects one of the instructions listed above based on the result obtained by executing the certain instruction.

Therefore, not only is there no flexibility in the program, but there is also the process of selecting instructions, etc. ! This limits high-speed operation when executing a series of instructions.

SUMMARY OF THE INVENTION An object of the present invention is to provide an instruction format for arithmetic instructions that allows programs in a microcomputer system to be flexible and allows for easy development of programs for, for example, graphic processing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A typical overview of the inventions disclosed in this application is as follows.

In other words, an instruction that gives the type of operation as one of the operands, that is, an instruction that adds operand information that specifies the sugar of the operation outside or inside the operation specification part that contains the common operation code called operation (broad sense). This allows the desired operation to be executed.

[Effect]

According to the above means, the contents of an operand that specifies the type of operation are set based on the execution result of a certain instruction, and the next instruction can perform an operation according to the contents of the operand. The type can be changed dynamically.

Therefore, it is possible to achieve the above-mentioned purpose of making the program flexible and making it easier to develop a program for, for example, graphic processing.

Hereinafter, an embodiment will be described in which the present invention is applied to an instruction related to handling data from arbitrary bits to arbitrary bits in a memory called a bit field (hereinafter referred to as a bit field instruction).

〔Example〕

As shown in Figures 1 and 2, the bit field instruction is executed by giving three values as operands: a base address BA, an offset Off from this base address, and a field width WD indicating the field length (number of bits). Specify the desired field in memory and perform AND or OR on the data in that field.
It performs logical operation processing such as OkL). Note that such bit field instructions are already available in microprocessors such as Motorola's M068020. This bit field instruction is given a base address BA, an offset off, and a field width WD by the operand after the operation code.

In this embodiment, the operation type is also specified by the operand. As a specific method for specifying an operation using operands, for example, in the embodiment shown in FIG. 9(5), a register immediate addressing method having a register number is used. That is, a code indicating the type of operation is stored in advance in a predetermined register R8, and the register number containing the code and the addressing mode are stored in the operands. In the embodiment shown in FIG. 9), information to determine the type of operation based on the contents of register kL5 is added to the operation code. When executing the instructions shown in FIG. 9, (5) or FIG. 9 (b), the code indicating the type of operation is read out as data from the memory using a MOVE instruction, etc., and stored in a predetermined register R5. I'll put it in.

Also, in the same 41, pace address BA, 7th, 7th Qff
and field width WD are also configured to execute instructions using values stored in respective predetermined registers.

The command shown in FIG. 9(5) or FIG. 9(B) is, for example,
Bit fields to be accessed and accessed by bit field instructions (
This is an inter-bit field operation instruction that performs a logic between data on the source side) and data on another bit field (on the testing side) and puts it into a bit field on the destination side. To execute this instruction, registers are required to store the pace address RAS, offset Qffs, and field width WDsi that specify the bit field on the source side, and the base address BAd that specifies the pit field on the destination side.
, offset Qffd, and field width WDdl, and a register to store a code specifying the type of operation are required. However, the above two
Since the field widths WD are necessarily the same in instructions that take two bit field logics, the registers can be shared.

Table 1 shows an example of the relationship between the registers conveniently used in the inter-bit field operation instructions and the data stored therein.

In the figure, BA indicates a base address, and Qff indicates an offset.

Further, Table 2 shows a list of the types of operations specified by the register R5.

In Table 2, the operation indicated by 'l'rue sets all bits of the bit field on the four side of the destination to ``1'', and the operation indicated by False sets all the bits of the bit field on the four side of the destination string to ``1''. It means an operation to set a bit to 0''. Also, the operation indicated by N0l-1)est inverts the data of all the bits in the destination bit field and puts it into the original bit field. The operation indicated by Dest returns the data in the destination bit field to the original bit field, and the operation indicated by NOl inverts the data of all bits in the source bit field and affects the destination. The operation indicated by 5rc means the operation of putting data in the source bit field into the destination bit field.

Furthermore, the operation indicated by AND is an operation that takes the logical product of the data in the bit fields on the source side and the destination side and puts it into the bit field on the destination side. The operation indicated by XOR is an operation that takes the logical sum of the data in the bit fields on the source side and the destination side and puts it into the bit field on the destination side. The operation indicated by NotAnd is an operation that takes the exclusive OR of the data in
The operation indicated by pJo tQr is an operation that takes the logical product of the inverted value of the data in the bit field on the test side, the source side, and the data in the to field and stores it in the bit field on the destination side. Testinesi.

The operation of logically ORing the inverted value of the data in the destination side bit field with the data in the source side bit field and putting it into the destination side bit field is called An.
The operation indicated by dNot is an operation i, QrNot, which takes the AND of the data in the bit field on the destination side and the inverted value of the data in the source side bit field and puts it into the bit field on the destination side. NotAndNot indicates the operation of logically ORing the data in the bit field on the destination side and the inverted value of the data in the source bit field on the indicated operation line and putting it into the bit field on the destination side. The operation performed is called NotOrNo, which takes the logical product of the inverted value of the data in the destination bit field and the inverted data value in the source bit field and stores it in the destination bit field.
The operation indicated by t is an operation that takes the logical sum of the inverted value of the data in the bit field on the destination side and the inverted value of the data in the pit field on the source side and stores it in the bit field on the destination side. , N01XO
The operation indicated by f performs an exclusive OR operation between the inverted value of the data in the bit field on the destination side and the data in the source side bit field, and stores the result in the bit field on the destination side. means.

The above various operations can be identified, for example, by the lower four bits of register R5.

When using the inter-bit field operation instructions mentioned above, the type of operation is given as one of the operands, so you can perform the operation during program execution by simply changing the data in memory or changing the data loaded from memory. The type of can be changed dynamically. However, before executing the inter-bit field operation instruction in this embodiment,
It is necessary to store in advance a base address and offset given as operands, and a code indicating the type of operation in predetermined registers (R0 to Rs).

Table 3 shows the above bit field operation instructions (BVMA).
An example of a program for displaying graphics using the program (abbreviated as P) is shown.

Table 3 LOOP MOVE (RIO)+, ROM0V
E (R11) +, R11 M0VE (R12) +, R2 MOVE (R13) +, R3 MOVE (R14) +, R4 MOVE (R15) 10, I (5 B, VMAP SUB LINE, -1 BNE LOOP The above program is , HVMA does not change the contents of registers RO to R5 by post-increment for each line.
The content of the processing is to repeatedly execute an inter-bit field calculation instruction indicated by P. For example, MOVE(
R1O)+, RO is an instruction to update the contents of register RO and store it in register RO. Also 80B LIN
E, -1 is an instruction to subtract 1 from the total number of lines.

Therefore, if the above program is repeatedly executed while changing the type of operation stored in register R5 every - time, the result of bit field processing with different operation contents for each line will be displayed as an image on the display screen. will be done.

In the above program, the type of operation is changed by changing the contents of the register 5 for each line, but the present invention is not limited to this embodiment. For example, the result obtained by a program executed before the above program can be stored in register R5, and the result can be executed during execution of the above program without updating the contents of register R5. This makes it possible to dynamically change the aI types of operations during program execution.

FIG. 7 shows a flowchart of the inter-bit field operation instruction BVMAP. In step S1,
The contents of registers RO, R1 and R2 are used to fetch the source side bit field. In step S2, the destination bit field is fetched using the contents of registers R2, R3, and R4. In step S3, an operation is performed using the contents of register 5. In step S4, the termination condition is determined,
If the termination conditions match, the instruction is terminated, and if they do not match, the process returns to step 1 above. The number of data pits that can be etched seven at a time is determined by the length of the data bus of the microprocessor. Therefore, all t-7 etch of the bit field,
In order to perform calculations based on this, steps 81-
It may be necessary to repeat S3 multiple times.

Note that in the above embodiment, 2 bit field instructions are used.
The explanation has been given as an example of instructions related to operations between data in two bit fields, but there are other bit field instructions suitable for graphic processing, such as operations on bit fields defined by base address, offset, and field width. On the other hand, an instruction that repeatedly stores a bit pattern in an arbitrary register can be considered. This command allows you to draw any area on the screen with any pattern (
A single glaze that fills in the basic shapes that make up the pattern
The D crushing process can be easily performed.

- FIG. 3 shows an example of the hardware configuration of a microprocessor that operates according to the instruction system having the bit field instructions of the above embodiment.

The microprocessor of this embodiment is equipped with a control section using a four-microphone program control system. That is, an LSI chip 1 constituting a microprocessor is provided with a micro ROM (read only memory) 2 in which a micro program is stored. The micro ROM 2 is accessed by the micro address generation circuit 5,
Sequentially outputs the microinstructions that make up the microprogram.

The microaddress generation circuit 5 is supplied with a signal obtained by decoding the code of the microinstruction fetched into the instruction register 3 by the instruction decoder 4.

The microaddress generation circuit 5 forms a corresponding microaddress based on this signal and supplies it to the microROM 2. As a result, the first instruction in a series of microinstructions that execute that microinstruction is read. This microinstruction code forms control signals for the execution unit 6, etc., which includes various registers, data buffers, arithmetic and logic units, and the like. This execution unit 6 includes general-purpose registers RO to R15 used in the above embodiment.

When reading the second and subsequent microinstructions in a series of microinstructions corresponding to a macroinstruction, the code of the next address field of the microinstruction read immediately before is supplied to the microROM 2. This is performed based on the next address within and the address from the microaddress generation circuit 5. In this way, the execution unit 6 is controlled by the control signal formed by reading out the series of microinstructions, and the macroinstructions are executed.

In this embodiment, although not particularly limited, a buffer storage method is adopted, and a cache memory 7 is provided in the microprocessor LSI, and frequently accessed program data among the data in the external memory 8 is stored in the cache memory 7. registered within. This speeds up program import.

In the above embodiment, the explanation has been given of the application to a bit field instruction passed through graphic processing as an example, but the invention can be applied to other arithmetic instructions.

In addition, in the above embodiment, a of the operation specified by the operand is
! Although the class is limited to logical operations such as AND (AND) and OR (OR), the operation code is the same for the instructions that perform the operation, and the operation a[g14 is specified by the operand. You may also do so.

FIG. 4 shows an internal block diagram of the execution unit 6 shown in FIG.

In the execution unit shown in Fig. 4, the circuit symbol CBS is a friend register for loading extension data such as offset values and field widths, and DUfL is a data output register for loading data to be stored in memory. The input register, DIR, is the data input register, ALN, which doubles the data read from memory.
is an aligner that aligns input and output data, and this aligner ALN is connected to an external data bus via a data I10 interface (not shown).

Also, the circuit symbol B8F is a barrel shifter for extracting arbitrary 32 bits from 64-bit data input 32 bits at a time, and this barrel shifter BSF can directly input a constant such as 0. It is configured as follows. BCNT is a barrel shifter counter that specifies the extraction position for barrel shifter BSF, B8F
This is a register that latches the output of the OH barrel shifter BSF. Further, FB is a register that latches the output of the function block FB, which functions to mask and output the upper 27 bits when inputting data.

Furthermore, the circuit symbol AU is an address calculation unit for calculating an effective address, and this address calculation unit (AU) is configured so that a constant such as 0 can be directly input. AUO is a register that latches the output of the address operation unit (AU), 8F'T is a shifter that shifts data before being operated on by the address operation unit AU, and AOT is the register AUOO value containing the operation result, which will be described later. Tempo 2 reregister DTEO~
Latch circuit, AU, which is temporarily held when transferring to DTE3
Similarly, R is an address output register that temporarily holds the address value of register AUO when outputting it to the outside, and this register AO'kL is connected to an external address bus via an address I10 interface (not shown). be done.

On the other hand, the circuit symbol ALU is an arithmetic and logic unit that performs basic arithmetic and logical operations such as addition and subtraction, and ALtJO is a register that doubles the operation results of the arithmetic and logic unit ALU. DTEO to DTE3 are a group of registers R, which are not visible from the outside (not open to the user) and hold temporary values.
R1,...R1, is a group of general-purpose registers open to the user, including the various registers and latch circuits mentioned above,
Arithmetic units, etc. are 4fi%OpaxECB, HA, BB, B
They are connected to each other via Cf and are operated sequentially by control signals supplied from a control section consisting of a micro ROM, and the corresponding macro instructions are executed.

According to the present invention, the arithmetic logic unit ALU, etc. can be controlled by the contents of a general-purpose register, for example, the contents of a register ratio of 5.

FIG. 5 shows the relationship between the arithmetic and logic units (ALU, etc.) shown in FIG. 4 and the register R5 for controlling them.

The contents of general-purpose register ratio 5 are not particularly limited, but are stored in another register INPR, and this register INP
Control signals 11 to 15 are output from R. Register I
Although the NF register is omitted in FIG. 4, it is the same type of register as the above-mentioned temporary register i) '1' EO, etc., and is provided in the execution unit. Control signal engineer 1
is a signal for selecting either data on the BB bus or all zero (0) data. The control signal engineer 2 is
This is a signal that controls the operation of the inverter circuit INV, and is a signal that selects whether to invert the input signal and output it, or output it without inverting it. The control signal 3 is a signal for selecting the arithmetic function of the arithmetic logic unit (ALU).

Arithmetic logic: “-=y ALU is !li&(AND)
, logical sum (0) or exclusive logical sum (xon), one of the functions is selected by the control signal I3. The control signal 15 is a signal for selecting whether to send the data stored in the register ALUO to the BC, or to feed it back to the input side of the ALU.

The control signal 4 is a hole signal for selecting the data fed back to the input side or -10,000 of all cello (0). The data selected by the control signal 11 is inputted to one side of the arithmetic logic unit ALU via the inverter circuit INV, and the data selected by the control signal 4 is inputted to the other side of the arithmetic and logic unit ALU. .

The operation of the ALU can be divided into two stages. Example 4 Table 5 For example, when performing each calculation listed in Table 2 above, the operating state of the first stage is shown in Figure 6 (5), and the operating state of the second stage is shown in Figure 6. Postal).

Table 4 above is a table for explaining in further detail the operating state shown in Fig. 6 (5) above, and Table 5 is a table for explaining in further detail the operating state shown in (5) in Fig. 6 above. This is a table for For example, the first operation l→dest shown in Table 2
When executing , first, in FIG. 6(5), the control listed in the first position of Table 4 is performed. That is, all zeros (0) are selected by the control signal 11, and this is not inverted by the inverter circuit IND, but is used as one input data of the ALU. In addition, the input data of the other side of the ALU (arithmetic logic unit) is all zero (
0). Since the arithmetic function of this arithmetic logic unit (ALU) is logically summed (about 0) by the control signal engineer 3, the result of the arithmetic operation is all zeros (0). Next, the sixth
In Figure (B), the control described in the first column of Table 5 is performed. That is, all zeros (0) are selected by the control signal I1, and this is the inverter circuit INV.
The data is inverted and made all one (1), which is used as input data for one of the arithmetic and logic units ()ALU. The other input data of the ALU (arithmetic logic unit) is the result of the above operation (all zeros). Since the arithmetic function of the ALU (arithmetic logic unit) is logically summed (OR) by the control (*-1'+I3), the result of the operation is all one (1).This data is sent to the destination bit By storing in the field, the above-mentioned operation 1→aest is completed.

Also, the 10th operation dest, AND, s r
When executing c-+aest, first
), the control listed at No. 10 in Table 4 is performed. That is, the data on BB (in this case, the value of the source bit field) sr
c is selected and is not inverted by the inverter circuit IND, but is used as input data for one of the arithmetic and logic unit ( ) ALU. In addition, the input data of the other input to the performance unit ALU is set to all zeros (0).

Since the arithmetic function of the ALU is logically summed (0) by the control signal engineer 3, the result of the arithmetic operation is taken as the value (src) of the source side bit field.

Next, in FIG. 6(B), the control listed in the 10th position of Table 5 is performed.

In other words, data on BBBUS (
In this case, the value of the destination bit field)
dest is selected, inverted by the inverter circuit INV (dest), and used as one input data of the arithmetic unit ALU. The other input data of the arithmetic logic unit (ALU) is the above-described calculation result (src). The arithmetic function of the arithmetic logic unit and ALU is ANDed by the control signal 3, so the result of the arithmetic operation is de
At, AND, arc. By storing the data in the destination bit field, the above operations dest, AND, src→aest
execution ends.

In the above embodiment, the arithmetic and logic unit (ALU) etc. are directly controlled by the contents of the register 5, but the application of the present invention is not limited to the above embodiment. In other words, depending on the contents of general-purpose register R5,
) ALU etc. may be controlled indirectly.

For example, by supplying the contents of the register R5 to the instruction decoder 4 shown in FIG. 3, the control signals 1 to 5 can be obtained from the microcontroller OM2. In the above embodiment, the control signal 1 is used as a selection signal for selecting data on the BB bus, but is not limited thereto. For example, a supply source for supplying data on the BB bus can also be controlled by this control signal equipment 1.

Note that the value src of the source side bit field or the value d e st of the destination side bit field is sent onto the BB path from the output latch register B8FO of the barrel shifter BSF.

FIG. 8 shows an execution procedure for explaining step S1 in the flowchart shown in FIG. 7 in more detail. Step 81 is composed of steps 801 to 812. Note that among the general-purpose register groups 0 to R1 shown in FIG.
The registers marked with Y indicate the registers used for storing the source/base address, testing address, offset direct address, and bit field width, respectively. This R
a, Rb, RX, Ryas general register. ~R
Any register number of Is can be designated and used for each purpose.

In a first step 801, the value in the register Rx, that is, the address indicating the location where the offset value is stored, is input to 0 via the bus BA or BB and by the constant input function.
are respectively input to the address calculation unit AU, and the addition result is stored in the register AUO. In the second step 802, the address value (offset value address) stored in the register AUO in step 801 is transferred to the register AOR. At the same time, a request command is given to the I10 interface to fetch data on the external data bus. As a result, the address value in register Rx is output onto the external address bus via the I10 interface, the external memory is accessed, and its contents are output onto the data bus. Then, the data read from the memory, ie, the offset value Qff, is shifted and etched by the I10 interface.

In the third step 803, it is confirmed whether the fetched data is determined based on the signal output from the 110 interface. This allows the data to
Input register DIRK taken! 0 is included. At the same time, in step 803, the value of the register Ra, that is, the source pace address BAD is set to the bus BA or BB.
0 is input to the address calculation unit (All) via the constant input function and the addition result is stored in the register AUO.

Then, in a fourth step 804, the register AU
The OO value (source pace address) is transferred to register AOR, and then transferred to temporary register D via bus BC.
Transferred to TEO.

Note that in relation to other processing, when the operation result of the address operation unit (AU) is transferred from register AUO to AOR, it is also automatically transferred to register AOT. Here, the transfer to register AOT has no special meaning. In parallel, 0 is input to the address operation unit (AU) by the constant input function, and the data input register D is input via the bus BB.
'4 (offset value) of IR is sign-extended and input, and the operation result is stored in register AUO.

Furthermore, from register R7, the function block FB
The held value, that is, the bit field width WB, is supplied via the bus BA, the upper 27 bits excluding the lower 5 bits are masked in the 7-anchor block FB, and the result is stored in the register FBO. Extracting only the lower five bits of the bit field width is equivalent to finding the remainder when the bit field width is divided by the number "32" when expressed mathematically. Hereinafter, the lower five bits of this bit field width will be referred to as a fraction WD. The reason why the fraction WD· is obtained here is to use it for determining boundary crossing in step 809 later.

Next, in step 806, the register UOO value, ie, the offset value Off, is transferred to the temporary register DTEl via the bus BC. In addition to this, for address calculation unit AU, the value of register AUO (offset value) and the value of temporary register DTEo, that is, the source
A value obtained by shifting the pace address BAD by 3 bits to the higher order side by a shifter SF 'f' is supplied, and the result of the addition is stored in the register ALIO. Shifting the source pace address BAD by 3 bits to the upper side expands the pace address BAD, which was designed to be able to specify the memory space by dividing it into bytes, so that it can specify the location in the memory space in bits. It's for a reason. Therefore, what is stored in register AUO at this time is the distance expressed in the number of bits from address 0 of the desired bit field. This distance is denoted as L.

In the sixth step 806, the value obtained by shifting the register AUOO value, that is, the pace address by 3 bits to the upper side, and the offset value Qff is added to the register AOT.
Transfer to. On the other hand, the source pace address BAD is input from the temporary register DTEO to the address calculation unit AU via the bus BA, and the offset value Off transferred from the temporary register DTE1 via the bus BB is input to the address calculation unit AU by the shifter S F T. A value shifted 3 bits to the side is input and added, and a value obtained by masking the lower 2 bits of the addition result is stored in register ALIO. At the same time, the value WD* in register FBO, that is, the lower five bits of the bit field width, is transferred to temporary register DTE3 via bus BC.

In the above case, the value obtained by shifting the offset value by 3 bits to the lower order side is added to the pace address by the address operation (Ninear) AU. This is to obtain the execution address. In addition, the address calculation unit,
The lower two bits of the addition result in U are masked by
This is to obtain the address of a 32-bit word that includes the entire target bit field or its leading part.

In the seventh step 807, the word address in the register ADO obtained as described above is transferred to the address output register AOR and output to the outside via the I10 interface, and is also output to the I10 interface. A command is issued to request 7 ft of data on the external data bus. This initiates a 7-etch from memory of the word containing the beginning of the desired bit field. In parallel with this, register A
The address held in UO is transferred to temporary register DTE2 via bus BC.

The value indicating the bit position from address 0 of the bit field obtained in step S05 is stored in lft-177 link block l''B from register AOT to bus B.
A and the result is stored in register FBO. As a result, the word address (
If the offset is 31 or less, it matches the pace address) and the start position Qff of the bit field (this is also one offset value, hereinafter referred to as a secondary offset) is held in the register FBO.

Subsequently, in step 808, the value Qff* (secondary offset) in the register BO is transferred to the tempo 2 re-register D'l'E2 via the bus BC. Along with this, En J! For logical unit ALU, bus B
A and BBt - through temporary register DTEa
The value WD (lower 5 bits of the bit field width) and the value Qff in the register FBO are supplied and added, and the result is stored in the register ALUOK. Along with this, the constant 1 is sent from the control unit side to the register CBS.
33" is set. The number "33" is the number of bits in one word, "32", plus "1". Also, I10
Based on the signal from the interface, it is confirmed whether the fetched data, that is, the content of the requested field is sufficient. If the data is confirmed, it means that the data has been taken into the data input register DIR.

In the next step 809, h, the value shifted and etched by the I10 interface is stored in the data input register DI.
The data is transferred from R to the tempo 2 reregister DTE2 via bus BC. In parallel with this, the arithmetic logic unit ALU
Then, the value "33" of the register CBS is subtracted from the value of the register ALUO (Off fist+WD*), and the result is stored in the register AL[JO. Here, if the result of this subtraction is "positive", it means that the bit field spans two words, and if it is "negative", it means that it is contained within one word.

Further, in step 809, instructions are given for the shift direction and shift amount of the bit shift processing to be performed by the barrel shifter 138F in the next step.

Specifically, a rightward shift instruction is given to the barrel shift counter BCN 'i', and the data in the register FBO (D i Of f
Umbrella is shifted by barrel shift 7/counter BCN
supplied to T.

Then, in step 810, the barrel system BSF
The contents of the temporary register DTE2O value, that is, the bit field 7 etched from memory, are transferred to bus B.
88F, and 0 is input by the foot-mounted human power function to execute a shift according to the instructions of the barrel shift counter BCNT, and the result is sent to the register 88F.
Stored in O. As a result, the contents of the 7-etched 9-bit field are stored in the 32-bit register BSFO as shown in FIG. 8, with the contents of the 9-bit field shifted toward the left end, and filled in sequentially from the upper bit side of the register.

In parallel with this, in step 810, the direction of the shift operation to be performed by barrel shifter 88F in the next step and the shift amount are specified. That is,
A rightward shift instruction is given to the barrel shifter counter BCNT, and the bit field l1WD in the temporary register DTEa is supplied as the shift amount via δBAt-.

Then, in step 811, the value of the register 88FO and "0" are input to the barrel shifter BSF,
A shift operation according to the specified direction and shift amount is executed, and the result is stored in register BF30. Register B
When the contents of the bit field contained in SFO are shifted to the right by the field @WD], 7 is stored in the 32-bit register BS)0 as shown in Figure 11.
The contents of the edited bit field are stored closer to the right end, that is, in a desired state in which the contents of the register are filled sequentially from the lower side.

In this way, the contents of the bit field obtained are
In the next step S12, the data is stored from register BSFO to one of the general-purpose registers via bus B (4-).

Further, in step 809, if the result of subtracting the sum of Qff value and WD value and foot value "33" is "positive" and it is determined that the bit field has passed the boundary, step 812 By returning to step 80B and repeating the above procedure, all contents of the bit field spanning multiple words are read.

FIG. 10 illustrates the relationship between the offset value Off and the bit field width WD in the microflow described above, and the secondary value Qff and the fraction WD*.

In addition, in the execution procedure of the unrestricted bit field instruction according to the micro 70- in FIG. This is done based on whether the result of subtracting is ``positive'' or ``negative.''

Originally, boundary crossing should be determined from the primary offset Off and the bit field @WD, and it is also possible to write such a microclaw. However, the bit field 4WD is set to the primary offset Off.
By adding the base address BAD and dividing it into 32-bit increments, it is determined whether or not boundary passing occurs.
It is clear from Figure 7 that exactly the same result can be obtained by adding the bit field fraction WD fist to the f umbrella and determining whether or not the boundary has passed based on whether it exceeds the number ``32''. It is.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the base address, offset, field width, and type of operation of the bit field are given as operands, but they may be given as effective address parts instead of operands.

Furthermore, the arithmetic instruction according to the present invention, in which the type of operation is determined by the operand, may be provided in place of the conventional fixed arithmetic operation, or may be provided in combination.

In the above explanation, the invention made by the present inventor was mainly applied to the instruction format of a microprocessor, which is the field of application that formed the background of the invention. It can be used as a general instruction format for program control type data processing systems.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, the program can be made flexible and, for example, a program for graphic processing can be easily developed.

[Brief explanation of the drawing]

1 and 2 are explanatory diagrams showing an example of the structure of a bit field in an inter-bit field operation instruction to which the present invention is applicable, and FIG. 3 is a structure of a microprocessor that executes a bit field instruction according to the present invention. A block diagram showing an example; FIG. 4 is a block diagram showing the internal configuration of the execution unit shown in FIG. 3; FIGS. AUU. 7 is a 70-chart showing an execution sequence of an inter-bit field operation instruction to which the present invention is applied; FIG. 8 is an execution sequence for explaining step S1 in FIG. 7 in more detail; and FIG. ), (B) are examples of instruction formats to which the present invention is applied, and FIGS. 10 and 11 are explanatory diagrams of operations during the execution sequence shown in FIG. 8. DOR...Data output register, DIR
...Data input register, ALN...Aligner, BaF...Barrel shifter, BCNT...Barrel shifter counter, FB...Function block, AU...Address calculation unit, SFT...
Shifter, AUO...Latch circuit, AO function...Address output register, ALU...Arithmetic logic name 31V1 Male 5r\J KA61F (A) 7U6γ No. 71 Yoji 1 concatenation 11 Orthographic (method)

Claims (1)

[Claims] 1. A first step comprising: an instruction decoding means, an instruction execution means, and an information holding means, and storing information obtained by executing the first instruction in the information holding means; A microprocessor comprising a second step in which the instruction execution means is controlled based on the information when executing the second instruction. 2. The microprocessor according to claim 1, wherein the instruction execution means includes a logic operation unit, and the operation function of the logic operation unit is controlled based on the information. 3. The microprocessor according to claim 2, wherein the information holding means is a general-purpose register. 4. It includes an instruction decoding means and an instruction execution means, and the operation code of the instruction decoded by the instruction decoding means includes at least one of the instruction execution means based on the information stored in the rewritable information holding means. A microprocessor characterized in that it includes information for controlling a part. 5. The microprocessor according to claim 4, wherein address information for specifying an address in the information holding means at which the information is stored is included in the operation code. 6. The microprocessor according to claim 4, wherein address information for specifying an address in the information holding means at which the information is stored is included in an operand area. 7. The microprocessor according to claim 4, wherein the rewritable information holding means is a register within the microprocessor. 8. Claim 7, wherein the instruction execution means includes a logic operation unit, and the operation function of the logic operation unit is controlled based on the contents of the register.
Microprocessor as described in Section. 9. The microprocessor according to claim 8, wherein the type of operation of the logical operation unit is selected based on the contents of the register. 10. The microprocessor according to claim 9, wherein the instruction decoded by the instruction decoding means is an instruction related to handling data in an area from an arbitrary bit to an arbitrary bit in the memory. .