JPS60177677A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60177677A
JPS60177677A JP3298784A JP3298784A JPS60177677A JP S60177677 A JPS60177677 A JP S60177677A JP 3298784 A JP3298784 A JP 3298784A JP 3298784 A JP3298784 A JP 3298784A JP S60177677 A JPS60177677 A JP S60177677A
Authority
JP
Japan
Prior art keywords
diffusion layer
layer
offset
conductive type
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3298784A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP3298784A priority Critical patent/JPS60177677A/en
Publication of JPS60177677A publication Critical patent/JPS60177677A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To prevent MOSFET characteristics from fluctuating even under high temperature and high bias voltage conditions, by burying an offset diffusion resistance layer into a semiconductor substrate at a drain diffusion region. CONSTITUTION:A field oxide film 12, a gate oxide film 13 and a gate electrode 14 are formed over an Si substrate 11 of a first conductive type, while a source diffusion layer 15, a drain diffusion layer 16 and a buried offset diffusion layer 17 each consisting of a second conductive type diffusion layer are formed. On the layer 7 a diffusion layer 18 consisting of the first conductive type is formed. In this way, voltage application to the offset portion can be done in the bulk, and stable current characteristics are attained, without changing the resistance value in spite of an effect of an increasing interface level at the surface layer owing to high temperature and high bias voltage.

Description

【発明の詳細な説明】 〔技術分野〕 本発明はオフセ、）・ゲー）ＭＯ８型ＦＥＴのドレイン
披散層構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a drain diffusion layer structure of an MO8 type FET.

ｒ従来技術〕 従来、オフセット・ゲート型高耐圧ＭＯＢ　ＦＦ１Ｔは
第１図の如き断面構造となっているのが通例である。す
なわち、第１の導電型からなる半導体基根１の表面には
、フィールド酸化膜２、ゲート酸化膜３、ゲート電極４
が形成されると共に、ソース拡散領域５、ドレイン拡散
領域６とオフセット・ゲート部７が第２の導電、型から
成る拡散層として形成されて成る。rPrior Art] Conventionally, an offset gate type high voltage MOB FF1T usually has a cross-sectional structure as shown in FIG. That is, on the surface of the semiconductor base 1 of the first conductivity type, a field oxide film 2, a gate oxide film 3, and a gate electrode 4 are formed.
At the same time, a source diffusion region 5, a drain diffusion region 6, and an offset gate portion 7 are formed as a diffusion layer of a second conductive type.

しかし、上記従来技術によると、オフ上９ト・ゲート部
に電圧が分配されて印加されるため１例えば高電圧を印
加しながら高温（２５０°Ｃ程度）に該ＭＯ８型ＦＫＴ
ｆ晒すと、核ＭＯＥＩ型ＦＥＴのソースとドレイン間の
電流より８が徐々に増加するという特性変動が発生する
欠点がある。However, according to the above-mentioned conventional technology, since the voltage is distributed and applied to the OFF top gate part, for example, the MO8 type FKT is heated to a high temperature (about 250°C) while applying a high voltage.
When exposed to f, there is a drawback that characteristic fluctuation occurs in that 8 gradually increases from the current between the source and drain of the nuclear MOEI type FET.

〔目的〕〔the purpose〕

本発明はかかる従来技術の欠点をなくし、高温、高電圧
バイアス下セも高耐圧ＭＯ８ＦＥＴの特性変動のないＭ
Ｏ８型ＦＫＴを提供することを目的とする。The present invention eliminates the drawbacks of the prior art, and eliminates the characteristic fluctuation of the high voltage MO8FET even under high temperature and high voltage bias.
The purpose is to provide O8 type FKT.

〔概要〕〔overview〕

上記−目的を達成するだめの本発明の基本的な構成け、
半導体装置に関し、ＭＯ８型トランジスタの少なくとも
ドレイン拡散層領域に於て、オフセット拡散抵抗層が半
導体基板内に埋め込まれて成ることを特徴とする。The basic structure of the present invention to achieve the above-mentioned object,
The semiconductor device is characterized in that an offset diffused resistance layer is embedded in the semiconductor substrate at least in the drain diffusion layer region of the MO8 transistor.

〔実施例〕〔Example〕

以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.

ｔａ２図は本発明の一実施例を示すＭＯＥＩ型ＦＥＴの
断面図である。すなわち、第１の導電型力１ら成るＳｉ
基板１１の表面には、フィールド酸化膜Ｒ、ゲート酸化
膜１３、ゲート電極１４が形成さね、ると共にソース拡
散層１５、ドレイン拡散層１６と埋め込みオフセット拡
散層１７が第２の導電型の拡散層で形成され、埋め退入
オフセット拡散層１７上にけ、第１の導電、型から成る
拡散層１８が形成されて成る。Figure ta2 is a cross-sectional view of a MOEI type FET showing one embodiment of the present invention. That is, Si consisting of the first conductivity type force 1
A field oxide film R, a gate oxide film 13, and a gate electrode 14 are formed on the surface of the substrate 11, and a source diffusion layer 15, a drain diffusion layer 16, and a buried offset diffusion layer 17 are formed as second conductivity type diffusion layers. A first conductive type diffusion layer 18 is formed on the buried offset diffusion layer 17.

〔効果〕〔effect〕

上記の如く、オフセット拡散抵抗層を坤め込んで形成す
ることにより、オフセ、）部への電圧印加がバルク内で
行なわれ１表面層の界面準位の高温、高電圧バイアスに
よる増加の影響により抵抗値が変化することなく、安定
な電流特性が得られる効果がある。As described above, by embedding and forming the offset diffused resistance layer, voltage is applied to the offset portion () within the bulk, and due to the influence of increase in the interface state of the surface layer due to high temperature and high voltage bias. This has the effect of providing stable current characteristics without changing the resistance value.

〔応用〕〔application〕

本発明はゲート下に埋め退入拡散抵抗層が形成されても
良く、ソースとドレイン両領斌に埋め込みオフセット拡
散抵抗層が形成されても良く、その効果は同じである。In the present invention, a buried offset diffused resistance layer may be formed under the gate, or a buried offset diffused resistance layer may be formed in both the source and drain regions, and the effect is the same.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来技術によるオフセット・ゲート型ＭＯ８Ｆ
ＩＣＴの断面図、第２図は本発明の一実施例を示す埋め
通入オフセット・ゲート型ＭＯ８Ｆｉｌ：Ｔの断面図で
ある。 １．１１・・・・・・ｓｉ基板 ２・１２・・・・・・フィールｌ’　酸化Ｍ５、１３　
、、、、、、ゲート酸化膜 ４、１４　、、、、、、ゲート電極 ５．１５・・・・・・ソース領域 −６，１６・・・・・・ドレイン領域 ７・・・・・・オフセット拡散層Figure 1 shows an offset gate type MO8F using conventional technology.
FIG. 2 is a cross-sectional view of a buried through offset gate type MO8Fil:T showing one embodiment of the present invention. 1.11... Si substrate 2, 12... Field l' oxidation M5, 13
, , , , Gate oxide film 4, 14 , , Gate electrode 5.15... Source region -6, 16... Drain region 7... offset diffusion layer

Claims (1)

【特許請求の範囲】[Claims] ＭＯＢ型トランジスタの少なくともドレイン拡散層領域
に於て、オフセット拡散抵抗層が半導体基板内に埋め込
まれて成ることを特徴とする半導体装置。A semiconductor device characterized in that an offset diffused resistance layer is embedded in a semiconductor substrate in at least a drain diffusion layer region of a MOB type transistor.
JP3298784A 1984-02-23 1984-02-23 Semiconductor device Pending JPS60177677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3298784A JPS60177677A (en) 1984-02-23 1984-02-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3298784A JPS60177677A (en) 1984-02-23 1984-02-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60177677A true JPS60177677A (en) 1985-09-11

Family

ID=12374222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3298784A Pending JPS60177677A (en) 1984-02-23 1984-02-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60177677A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0197501A2 (en) * 1985-04-12 1986-10-15 General Electric Company Extended drain concept for reduced hot electron effect
JPH02106973A (en) * 1988-10-17 1990-04-19 Nec Corp Semiconductor device
EP0414226A2 (en) * 1989-08-24 1991-02-27 Nec Corporation MOS field-effect transistor with sidewall spacers
US5170232A (en) * 1989-08-24 1992-12-08 Nec Corporation MOS field-effect transistor with sidewall spacers
US5567965A (en) * 1994-05-16 1996-10-22 Samsung Electronics Co., Ltd. High-voltage transistor with LDD regions
WO2003017349A3 (en) * 2001-08-17 2003-11-27 Ihp Gmbh Dmos transistor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS509388A (en) * 1973-05-22 1975-01-30
JPS55108773A (en) * 1979-02-14 1980-08-21 Nec Corp Insulating gate type field effect transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS509388A (en) * 1973-05-22 1975-01-30
JPS55108773A (en) * 1979-02-14 1980-08-21 Nec Corp Insulating gate type field effect transistor

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0197501A2 (en) * 1985-04-12 1986-10-15 General Electric Company Extended drain concept for reduced hot electron effect
JPH02106973A (en) * 1988-10-17 1990-04-19 Nec Corp Semiconductor device
EP0414226A2 (en) * 1989-08-24 1991-02-27 Nec Corporation MOS field-effect transistor with sidewall spacers
US5170232A (en) * 1989-08-24 1992-12-08 Nec Corporation MOS field-effect transistor with sidewall spacers
US5567965A (en) * 1994-05-16 1996-10-22 Samsung Electronics Co., Ltd. High-voltage transistor with LDD regions
US5879995A (en) * 1994-05-16 1999-03-09 Samsung Electronics Co., Ltd. High-voltage transistor and manufacturing method therefor
WO2003017349A3 (en) * 2001-08-17 2003-11-27 Ihp Gmbh Dmos transistor
US7304348B2 (en) 2001-08-17 2007-12-04 Ihp Gmbh - Innovations For High Performance Microelectronics/Institut Fur Innovative Mikroelektronik DMOS transistor

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