JPH0278274A - Insulated gate field effect transistor - Google Patents

Abstract

PURPOSE:To obtain a MOSIC which includes a dynamic circuit and is stable even if a reverse bias is not applied to a substrate by a method wherein the thickness of a first conductivity type semiconductor formed on an insulator film is made thinner than that of a depletion layer which is formed on the surface when the FET is ON. CONSTITUTION:A MOSFET is composed of a gate electrode of a conductor 108, a gate insulator film of a silicon oxide 107, a substrate of a P-type silicon 104, a source 105 and a drain 106 of N-type silicon. Here, the thickness of a part of the P-type silicon 104 extending over the silicon oxide film 102 is set thinner than that of a depletion layer which is formed on the surface when the FET is ON. Therefore, the effect of a gate voltage reaches up to the silicon oxide film 102 through the intermediary of the P-type silicon 104. By this setup, even if noised are applied between a source and a drain which are electronically floated and a small forward bias is applied between an electrode and the substrate, minority carriers are not injected into a substrate and consequently malfunction hard to occur.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect transistor (hereinafter referred to as MO3FET) suitable for application to large-scale integrated circuits.

[Conventional technology]

Usually, an integrated circuit (
In the MO8IC (hereinafter referred to as MO8IC), a reverse bias is applied to the substrate when it includes a dynamic circuit. The reason for this is to prevent malfunctions due to noise added to the electrically floating electrodes. In MO3IC, there is a PN junction between the source electrode or drain electrode of the MOSFET and the substrate.
Normally, forward bias is not applied to the junction to insulate the electrodes from the substrate. However, when those electrodes are electrically floating, the voltages on those electrodes are affected by ambient voltage changes through capacitive coupling. Therefore, if sufficient reverse bias is not applied between those electrodes and the substrate (near OV), there is a possibility that forward bias is applied between those electrodes and the substrate. In this case, current flows through the PN junction and minority carriers are injected into the substrate. These minority carriers diffuse within the substrate and give noise to the surrounding electrodes.In order to prevent this from happening in normal dynamic MO3ICs, the voltage changes of the electrically floating electrodes caused by capacitive coupling are sufficiently suppressed. A large voltage reverse bias is applied to the substrate.

[Problem to be solved by the invention]

However, applying a reverse bias to the substrate degrades the performance of the SIC. Furthermore, in order to apply a reverse bias to the substrate of the MO5IC, the voltage must be supplied to the substrate. If that voltage is supplied from outside the MO5IC, the number of external power supplies will increase, and the MO5
ICs become difficult to use.

On the other hand, if the voltage is generated inside the MO5IC,
A circuit for this is required, making the design of the MO3IC difficult. Moreover, when a reverse bias is applied to the substrate, the depletion layer formed at the PN junction formed in the substrate becomes thicker.
The amount of charge generated inside the depletion layer by heat and radiation increases. Therefore, MO5I with reverse bias applied to the substrate
In C, the PN junction leakage current increases and the characteristics deteriorate.

As described above, in the conventional MO5IC, when a dynamic circuit is included, it is necessary to apply a reverse bias to the substrate, but as a result, there is a problem that the performance deteriorates.

An object of the present invention is to overcome the above-mentioned difficulties, and to provide a MOSFET in which the PN junction between the source electrode or drain electrode and the substrate is not forward biased even if it is affected by changes in ambient voltage through capacitive coupling. The goal is to provide a structure for

[Means to solve the problem]

In order to achieve the above object, the present invention includes a first conductivity type semiconductor substrate, an insulating film formed to have an opening on one main surface of the semiconductor substrate, and an insulating film that is in contact with the semiconductor substrate through the opening. , an insulation including a first conductivity type semiconductor, a portion of which extends over the insulator film, and a second conductivity type semiconductor formed on the insulator film so as to be in contact with the first conductivity type semiconductor. In the gate field effect transistor, the thickness of the first conductivity type semiconductor on the insulator film is made thinner than the thickness of a depletion layer formed on the surface of the insulated gate field effect transistor when the transistor is conductive.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1(a) is a plan view showing the structure of an N-type channel MO5FET which is an embodiment of the present invention, and FIG. 1(b)
is a sectional view taken along line AA' in FIG. 1(a). In the figure, 101 is a P-type silicon substrate, 10
2,103, 107.109.110. is a silicon oxide film, 104 is a thin P-type silicon that is in contact with the P-type silicon substrate 101 and extends to the upper silicon oxide film 102, 105, 106 is N-type silicon, 108, 111,
112. is a conductor, 113 and 114 are contact holes, 1
Reference numeral 15 indicates an opening in the silicon oxide film 102, respectively. The P-type silicon 104 passes through the opening 115
It is in contact with the mold silicon substrate 101 and a portion thereof extends over the silicon oxide film 102 .

N-type silicon 105 and 106 are formed on silicon oxide film 102 in contact with P-type silicon 104. In addition,
In the plan view of FIG. 1(a), some lines are omitted to avoid obscurity.

The above MO5FET has a conductor 108 as a gate electrode, a silicon oxide film 107 as a gate insulator film, and a P-type silicon 10
4 is used as a substrate, and N-type silicon 105 and 106 are used as source/drain electrodes.

Also, the thickness of the portion of the P-type silicon 104 of the MO5FET that extends over the silicon oxide film 102 is determined by the MOSFET.
The thickness is set to be thinner than the thickness of the depletion layer formed on the surface of the ET when it is conductive. Therefore, in the MO5FET of the present invention,
The influence of the gate voltage reaches the silicon oxide film 102 through the P-type silicon 104. P-type silicon substrate 101 is Ov, this MOSFET is in a cut-off state, and N-type silicon 105 is used as one source/drain electrode.
Let us consider a case where, while electrically floating, the electrode is affected by changes in the surrounding voltage through capacitive coupling, resulting in a slightly negative voltage. In this case, P-type silicon 10
4. A slight forward bias is applied to the PN junction between the N-type silicon 105. However, in the case of this MOSFET, P
The P-type silicon 104 near the N junction has become a depletion layer due to the influence of the gate voltage.

Therefore, when the forward bias is small, electrons are hardly injected from the N-type silicon 105 to the P-type silicon 104.

〔Effect of the invention〕

As explained above, according to the MOSFET of the present invention,
Noise is added to the electrically floating source and drain electrodes,
Even if some forward bias is applied between the electrode and the substrate, minority carriers are not injected into the substrate, making it difficult to malfunction. Therefore, MO5ICt! contains a stable dynamic circuit without applying reverse bias to the board! :W has an effect that can be achieved.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view showing the structure of an embodiment of the semiconductor device of the present invention, and FIG. 1(b) is a sectional view taken along the line AA' in FIG. 1(a). 101...P-type silicon substrate 102...Silicon oxide film 104...P-type silicon 105, 106
...N-type silicon 115...opening

Claims (1)

[Claims] (1) a first conductivity type semiconductor substrate, an insulating film formed to have an opening on one principal surface of the semiconductor substrate, and a part of which contacts the semiconductor substrate through the opening; An insulated gate field effect transistor comprising a first conductivity type semiconductor extending on an insulator film and a second conductivity type semiconductor formed on the insulator film so as to be in contact with the first conductivity type semiconductor. An insulated gate field effect transistor characterized in that the thickness of a first conductivity type semiconductor on an insulator film is made thinner than the thickness of a depletion layer formed on the surface of the insulated gate field effect transistor when the insulated gate field effect transistor is turned on.