JPS60176554U - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS60176554U JPS60176554U JP1984064695U JP6469584U JPS60176554U JP S60176554 U JPS60176554 U JP S60176554U JP 1984064695 U JP1984064695 U JP 1984064695U JP 6469584 U JP6469584 U JP 6469584U JP S60176554 U JPS60176554 U JP S60176554U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- electrode film
- types
- semiconductor device
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/4557—Plural coating layers
- H01L2224/45572—Two-layer stack coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図a ”−cは従来のGTOの一例を系す図で、a
は平面図、b、 cはaのA−A、B−B切断線での断
面図、第2図azdは本考案の一実施例GTOの一例を
示す図でaは平面図、axdはaのC−C5D−D、E
−E切断線での断面図、第3図は第2図のGTOに用い
られる複合電極材の断面斜視図、第4図は本考案の一実
施例製法の要部を示す図、第5図a、 b及び第6図a
、 bは本考案の実施例の半導体装置の概略を示す図、
第7図は本考案の一実施例ρTOと従来のGTOの順素
子電圧と最大可制御電流との関連を示す図である。 1・・・半導体基体、4・・・pゲート、5・・・nエ
ミッタ、6・・・ゲート電極膜、7・・・カソード電極
膜、62・・・ゲート用銅細線、72・・・カソード用
銅細線。 4 10−7−
は平面図、b、 cはaのA−A、B−B切断線での断
面図、第2図azdは本考案の一実施例GTOの一例を
示す図でaは平面図、axdはaのC−C5D−D、E
−E切断線での断面図、第3図は第2図のGTOに用い
られる複合電極材の断面斜視図、第4図は本考案の一実
施例製法の要部を示す図、第5図a、 b及び第6図a
、 bは本考案の実施例の半導体装置の概略を示す図、
第7図は本考案の一実施例ρTOと従来のGTOの順素
子電圧と最大可制御電流との関連を示す図である。 1・・・半導体基体、4・・・pゲート、5・・・nエ
ミッタ、6・・・ゲート電極膜、7・・・カソード電極
膜、62・・・ゲート用銅細線、72・・・カソード用
銅細線。 4 10−7−
Claims (1)
- 【実用新案登録請求の範囲】 1 少なくとも1つの主表面を有し、この主表面に互い
に導電型が異なる2種類の半導体領域が少なくとも一部
で一方が他方の少な(とも一部と入り組むように隣接し
て露出している半導体基体と、半導体基体の上記2種類
の半導体領域の主表面露出部にそれぞれ上記半導体領域
と略同形状に形成されている電極膜と、上記電極膜の少
なくとも一方に導電的に接着され、上記電極膜と略同寸
法の電極部分′と、上記電極部分と一体である外部引出
部分とからなる導電部材とを具備することを特徴とする
半導体装置。 2 実用新案登録請求の範囲第1項において、上記電極
膜は上記半導体基体と直接低抵抗接着されるものであり
、上記導電部材は電極膜と導電的に接着され電極膜の半
導体基体と平行な方向での電気抵抗を減少させるもので
あることを特徴とする半導体装置。 3 実用新案登録請求の範囲第1項において、上記2種
類の半導体領域の一方は、他方にとり囲まれた複数の互
いに略平行な短冊状に露出していることを特徴とする半
導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984064695U JPS60176554U (ja) | 1984-05-04 | 1984-05-04 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984064695U JPS60176554U (ja) | 1984-05-04 | 1984-05-04 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60176554U true JPS60176554U (ja) | 1985-11-22 |
Family
ID=30596019
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984064695U Pending JPS60176554U (ja) | 1984-05-04 | 1984-05-04 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60176554U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2015129415A1 (ja) * | 2014-02-27 | 2017-03-30 | シャープ株式会社 | 半導体装置 |
-
1984
- 1984-05-04 JP JP1984064695U patent/JPS60176554U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2015129415A1 (ja) * | 2014-02-27 | 2017-03-30 | シャープ株式会社 | 半導体装置 |
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