JPS60176554U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS60176554U
JPS60176554U JP1984064695U JP6469584U JPS60176554U JP S60176554 U JPS60176554 U JP S60176554U JP 1984064695 U JP1984064695 U JP 1984064695U JP 6469584 U JP6469584 U JP 6469584U JP S60176554 U JPS60176554 U JP S60176554U
Authority
JP
Japan
Prior art keywords
semiconductor
electrode film
types
semiconductor device
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984064695U
Other languages
English (en)
Inventor
保敏 栗原
皆川　忠
八野　耕明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1984064695U priority Critical patent/JPS60176554U/ja
Publication of JPS60176554U publication Critical patent/JPS60176554U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/521—Structures or relative sizes of bond wires
    • H10W72/522—Multilayered bond wires, e.g. having a coating concentric around a core
    • H10W72/523—Multilayered bond wires, e.g. having a coating concentric around a core characterised by the structures of the outermost layers, e.g. multilayered coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図ａ　”−ｃは従来のＧＴＯの一例を系す図で、ａ
は平面図、ｂ、　ｃはａのＡ−Ａ、Ｂ−Ｂ切断線での断
面図、第２図ａｚｄは本考案の一実施例ＧＴＯの一例を
示す図でａは平面図、ａｘｄはａのＣ−Ｃ５Ｄ−Ｄ、Ｅ
−Ｅ切断線での断面図、第３図は第２図のＧＴＯに用い
られる複合電極材の断面斜視図、第４図は本考案の一実
施例製法の要部を示す図、第５図ａ、　ｂ及び第６図ａ
、　ｂは本考案の実施例の半導体装置の概略を示す図、
第７図は本考案の一実施例ρＴＯと従来のＧＴＯの順素
子電圧と最大可制御電流との関連を示す図である。 １・・・半導体基体、４・・・ｐゲート、５・・・ｎエ
ミッタ、６・・・ゲート電極膜、７・・・カソード電極
膜、６２・・・ゲート用銅細線、７２・・・カソード用
銅細線。 ４ １０−７−

Claims (1)

  1. 【実用新案登録請求の範囲】 １　少なくとも１つの主表面を有し、この主表面に互い
    に導電型が異なる２種類の半導体領域が少なくとも一部
    で一方が他方の少な（とも一部と入り組むように隣接し
    て露出している半導体基体と、半導体基体の上記２種類
    の半導体領域の主表面露出部にそれぞれ上記半導体領域
    と略同形状に形成されている電極膜と、上記電極膜の少
    なくとも一方に導電的に接着され、上記電極膜と略同寸
    法の電極部分′と、上記電極部分と一体である外部引出
    部分とからなる導電部材とを具備することを特徴とする
    半導体装置。 ２　実用新案登録請求の範囲第１項において、上記電極
    膜は上記半導体基体と直接低抵抗接着されるものであり
    、上記導電部材は電極膜と導電的に接着され電極膜の半
    導体基体と平行な方向での電気抵抗を減少させるもので
    あることを特徴とする半導体装置。 ３　実用新案登録請求の範囲第１項において、上記２種
    類の半導体領域の一方は、他方にとり囲まれた複数の互
    いに略平行な短冊状に露出していることを特徴とする半
    導体装置。
JP1984064695U 1984-05-04 1984-05-04 半導体装置 Pending JPS60176554U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984064695U JPS60176554U (ja) 1984-05-04 1984-05-04 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984064695U JPS60176554U (ja) 1984-05-04 1984-05-04 半導体装置

Publications (1)

Publication Number Publication Date
JPS60176554U true JPS60176554U (ja) 1985-11-22

Family

ID=30596019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984064695U Pending JPS60176554U (ja) 1984-05-04 1984-05-04 半導体装置

Country Status (1)

Country Link
JP (1) JPS60176554U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2015129415A1 (ja) * 2014-02-27 2017-03-30 シャープ株式会社 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2015129415A1 (ja) * 2014-02-27 2017-03-30 シャープ株式会社 半導体装置

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