JPS60176162A - チヤネル制御方式 - Google Patents

チヤネル制御方式

Info

Publication number
JPS60176162A
JPS60176162A JP3306884A JP3306884A JPS60176162A JP S60176162 A JPS60176162 A JP S60176162A JP 3306884 A JP3306884 A JP 3306884A JP 3306884 A JP3306884 A JP 3306884A JP S60176162 A JPS60176162 A JP S60176162A
Authority
JP
Japan
Prior art keywords
register
channel
control unit
control information
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3306884A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0149978B2 (cs
Inventor
Seiichi Shimizu
誠一 清水
Teruo Aizawa
相沢　照夫
Satoshi Sugiura
聡 杉浦
Hirokazu Kondo
浩和 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3306884A priority Critical patent/JPS60176162A/ja
Publication of JPS60176162A publication Critical patent/JPS60176162A/ja
Publication of JPH0149978B2 publication Critical patent/JPH0149978B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP3306884A 1984-02-23 1984-02-23 チヤネル制御方式 Granted JPS60176162A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3306884A JPS60176162A (ja) 1984-02-23 1984-02-23 チヤネル制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3306884A JPS60176162A (ja) 1984-02-23 1984-02-23 チヤネル制御方式

Publications (2)

Publication Number Publication Date
JPS60176162A true JPS60176162A (ja) 1985-09-10
JPH0149978B2 JPH0149978B2 (cs) 1989-10-26

Family

ID=12376408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3306884A Granted JPS60176162A (ja) 1984-02-23 1984-02-23 チヤネル制御方式

Country Status (1)

Country Link
JP (1) JPS60176162A (cs)

Also Published As

Publication number Publication date
JPH0149978B2 (cs) 1989-10-26

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