JPS60173862A - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JPS60173862A
JPS60173862A JP59029714A JP2971484A JPS60173862A JP S60173862 A JPS60173862 A JP S60173862A JP 59029714 A JP59029714 A JP 59029714A JP 2971484 A JP2971484 A JP 2971484A JP S60173862 A JPS60173862 A JP S60173862A
Authority
JP
Japan
Prior art keywords
substrate
frame
sealing resin
resin
cracks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59029714A
Other languages
English (en)
Inventor
Toru Tamaki
玉城　叡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59029714A priority Critical patent/JPS60173862A/ja
Publication of JPS60173862A publication Critical patent/JPS60173862A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔技術分野〕 本発明は集積回路装置に関し、特に基板上に複数個の半
導体ベレヅトヲ搭載して樹脂で封止した混成集積回路装
置に関するものである。
〔従来技術〕
従来、この種の装置は、纂１図（５）、（Ｂ）に示すよ
うに％　Ｐ）Ｔ定の導体記載が施された基＆ｌ上に複数
の半導体ベンツ）２−１乃至２−４を搭載し、ホンティ
ングワイヤ３で結線した後、被数個のベレット２−１乃
至２−４ｔその中に包含するようなただ一つの開口を有
する半枠４を貼りつけ、その枠４内に封止樹脂５ヶ注入
する構造でめった。
このように、半枠４の開口幅がかなり太きいものであっ
た。
一般に、封止樹脂５の材料はエポキシ系が用いられてお
り、エポキシ系は熱硬化による収縮が太きい。−万、基
板ｌの材料としてはセラミックが使用されているが、セ
ラミ、ツクはエポキシと比較して熱膨張係数が非常に小
さい。このため、従来の構造の混成集積回路装置におい
ては、内部応力が高くなり、基板１が反ったり熱衝撃に
よるクラックが生じたりするなどの欠点がある。その欠
点は枠４の開口幅が太さい程著しい。
〔発明の目的〕
本発明の目的、基板反りやクラック発生ケ防止した集積
回路装置を提供することにろる。
〔発明の構成〕
本発明は、枠に中仕切ｔつけたことを％徽とする。この
中仕切により枠の単−区の開口幅が小さくなり、この結
果、封止樹脂の熱硬化時の収縮や封止樹脂と基板との熱
膨張係数差による装置の内部応力を低減することができ
る。よって、本発明によれば基板の反りが小さく、耐熱
衝撃性の高い装置が得られるというオ０点がある。
〔実施例〕
次に、図面を用いて本発明の実施例について詳細に説明
する。
第２図（Ａ）　、　（Ｂ）は本発明の一実施例であって
、ｌは基板、２−１乃至２−４は半導体ペレット、３は
ボンディングワイヤ、４は多遮枠、５は封止樹脂、６−
１．６−２は枠４の中仕切である。このように、枠４が
中仕切６−１．６−２で区切られており、したがって、
単−区の囲口幅が小さくなっている。したがって、封止
樹脂５の加熱状綿や封止樹脂５と基板ｌとの熱膨張係数
差による内部応力を太幅に低減できる。この結果、従来
問題となっていた基板ｌの反りやクラック発生が防止さ
れる。
なお、本発明は上記実施例に限られないことは熱論でろ
る。
第１図匹）は従来の混成集積回路装置の断■図、第１図
（Ｂ）ばその平面透視図である。第２図（Ａ）は本発明
の一失施例奮示す〜丁面図であり、第２図（ＢＪはその
平面透視図でりる゛。
■・・・・・・基板、２−１乃至２−４・・・・・・半
導体ペレット、３・・・・・・ボンティングワイヤ、４
・・囮・枠、５・・・・・・封止樹脂、６−１．６−２
・・・・・・粋の中仕切。

Claims (1)

    【特許請求の範囲】
  1. 基板上に搭載された半導体ペレッ）ｋ封止する樹脂の広
    がりを止めるだめの枠に中仕切さを設けたことを特徴と
    する集積回路装置。
JP59029714A 1984-02-20 1984-02-20 集積回路装置 Pending JPS60173862A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59029714A JPS60173862A (ja) 1984-02-20 1984-02-20 集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59029714A JPS60173862A (ja) 1984-02-20 1984-02-20 集積回路装置

Publications (1)

Publication Number Publication Date
JPS60173862A true JPS60173862A (ja) 1985-09-07

Family

ID=12283773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59029714A Pending JPS60173862A (ja) 1984-02-20 1984-02-20 集積回路装置

Country Status (1)

Country Link
JP (1) JPS60173862A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0720232A4 (en) * 1993-09-14 1996-11-13 Toshiba Kk MANY CHIP MODULE

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0720232A4 (en) * 1993-09-14 1996-11-13 Toshiba Kk MANY CHIP MODULE

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