JPS60173832A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60173832A
JPS60173832A JP2974784A JP2974784A JPS60173832A JP S60173832 A JPS60173832 A JP S60173832A JP 2974784 A JP2974784 A JP 2974784A JP 2974784 A JP2974784 A JP 2974784A JP S60173832 A JPS60173832 A JP S60173832A
Authority
JP
Japan
Prior art keywords
insulating film
size
etching
opening
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2974784A
Other languages
Japanese (ja)
Inventor
Takashi Maruyama
隆司 丸山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2974784A priority Critical patent/JPS60173832A/en
Publication of JPS60173832A publication Critical patent/JPS60173832A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To make the size of the bottom of a contact hole smaller than that of an opening in a resist film formed prior to anisotropic dry etching by shaping the opening, size thereof is reduced along the depth direction, to an insulating film through anisotropic dry etching. CONSTITUTION:A resist film 5 with an opening 6a in size conformed to the size (a) of the upper section of a contact hole is formed on an insulating film 4, and an opening 6a section in the insulating film 4 is anisotropic dry-etched as using the resist film 5 as a mask while controlling the temperature of the resist film 5. The temperature of the resist 5 is elevated to a temperature such as approximately 250 deg.C at the same time as etching is started, and the insulating film 4 is etched until the depth of the hole formed reaches to one terminal 2 in a transistor while the temperature is lowered in succession in parallel with the progress of etching so that the temperature reaches to approximately 150 deg.C when the depth of etching is brought to approximately half the thickness of the insulating film 4. A desired funnel shape in which the size of a bottom is represented by (c) is obtained in the form of the hole shaped through etching, and a desired contact hole 1b is acquired when removing the resist film 5.

Description

【発明の詳細な説明】 (al 発明の技術分野 本発明は、半導体装置の製造方法に係り、特に、絶縁膜
の深さ方向に沿って寸法が小さくなる朝顔型のコンタク
トボールを形成する方法に関す。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of forming a contact ball of a morning glory shape whose dimensions become smaller along the depth direction of an insulating film. about.

(b) 技術の背景 半導体装置における半導体基板の表面に形成されたトラ
ンジスタの電極は、通常、該トランジスタ上の絶縁膜に
貫通して設けたコンタクトホール内の導体領域を介して
該絶縁膜上に導出されている。
(b) Background of the Technology In a semiconductor device, an electrode of a transistor formed on the surface of a semiconductor substrate is usually formed on an insulating film on the transistor through a conductive region in a contact hole provided through the insulating film on the transistor. It has been derived.

前記導体領域の形成は、例えばアルミニウムなどを用い
、前記絶縁膜上に前記電極ないし配線を形成する導体膜
の被着と一緒に、例えば蒸着法やスパッタ法などの表面
被着法によって行われることが多い。そこで、該導体が
確実に被着して断線事故などが発生しないようにするた
めには、コンタク1〜ポールの形状が問題になり、該導
体の絶縁膜表面から該コンタクトホール内面を経てトラ
ンジスタ表面に至る間の被着状態に無理のない、所謂カ
バレージのよい形状が望まれている。
The formation of the conductor region is performed by a surface deposition method such as a vapor deposition method or a sputtering method, using aluminum or the like, for example, together with the deposition of a conductor film for forming the electrode or wiring on the insulating film. There are many. Therefore, in order to ensure that the conductor adheres securely and to prevent disconnection accidents, the shape of the contact 1 to pole becomes an issue. What is desired is a shape with good coverage, which allows for a reasonable adhesion state during the process.

(C1従来技術と問題点 第1図はコンタクトホールの望ましい形状を示した図、
第2図はコンタクトホールの従来の形成方法の−・実施
例を示した図(a)〜(dlで、1.1aはコンタクト
ボール、2はトランジスタの一端子、3は半導体基板、
4は絶縁膜、5はレジスト膜、6は開孔、7.8はエッ
チ領域をそれぞれ示す。
(C1 Prior art and problems Figure 1 is a diagram showing a desirable shape of a contact hole.
FIG. 2 is a diagram (a) to (dl) showing an example of a conventional method for forming a contact hole, in which 1.1a is a contact ball, 2 is one terminal of a transistor, 3 is a semiconductor substrate,
4 is an insulating film, 5 is a resist film, 6 is an opening, and 7.8 is an etched region.

第1図図示において、コンタクトホール1は、表面にト
ランジスタの一端子2を形成した半導体基板3の上に被
着した例えば二酸化シリコンの絶縁膜4のトランジスタ
の一端子2と接する位置に形成されている。そして、コ
ンタクトボールlの形状は、前記カバレージをよくする
ため、図示のように、絶縁膜4の表面からコンタクトホ
ール1内面の底部に至る間が滑らかに小さくなる朝顔型
であることが望まれており、然も、その大きさはμmオ
ーダであるが、半導体集積回路装置の高集積化に伴うト
ランジスタの小型化のために、より小さくすることが望
まれている。
In FIG. 1, a contact hole 1 is formed at a position where an insulating film 4 made of silicon dioxide, for example, is deposited on a semiconductor substrate 3 on which a terminal 2 of a transistor is formed, and is in contact with one terminal 2 of a transistor. There is. In order to improve the coverage, it is desirable that the shape of the contact ball l be a morning glory shape in which the distance from the surface of the insulating film 4 to the bottom of the inner surface of the contact hole 1 is smoothly narrowed, as shown in the figure. Although its size is on the order of μm, it is desired to make it even smaller in order to reduce the size of transistors as semiconductor integrated circuit devices become more highly integrated.

一般に、基体にμmオーダの孔を穿つ場合には、該基体
上に開孔を有する例えばレジストなどの膜を形成し、該
膜をマスクにしてエッチする方法が行われる。コンタク
トホールを形成する場合もこの方法が用いられるが、朝
顔型の形状を目指す際には、工夫を加えて第2図図示の
方法で行っている。
Generally, when making holes on the order of μm in a substrate, a method is used in which a film such as a resist having openings is formed on the substrate, and etching is performed using the film as a mask. This method is also used when forming contact holes, but when aiming for a morning glory-shaped shape, the method shown in FIG. 2 is used with some modification.

即ら、予め図(a)図示のように1、絶縁膜4上にコン
タクトポールルの底部の大きさに合わせた大きさの開孔
6を有するレジスト膜5を形成し、これをマスクにして
等方性のウェットエツチングまたは等方性のドライエツ
チングにより図1b)図示のエッチ領域7をエッチする
。等方性であるためエッチ領域7のホトレジスト5に接
する部分の大きさは開孔6より大きくなる。続いて異方
性ドライエツチングにより図(C1図示のエッチ領域8
をエッチして、開孔6と同じ大きさでトランジスタの一
端子2に達する孔を穿ちホトレジスト膜5を除去して、
図((1)図示のコンタクトホール1aを形成している
That is, as shown in FIG. 1A, a resist film 5 having an opening 6 of a size matching the size of the bottom of the contact pole is formed on the insulating film 4 in advance, and this is used as a mask. Etch the etch region 7 shown in FIG. 1b) by isotropic wet etching or isotropic dry etching. Since it is isotropic, the size of the portion of the etch region 7 in contact with the photoresist 5 is larger than that of the opening 6. Then, by anisotropic dry etching, the etched area 8 shown in Figure (C1) is etched.
A hole having the same size as the opening 6 and reaching one terminal 2 of the transistor is made by etching, and the photoresist film 5 is removed.
(1) The contact hole 1a shown in the figure is formed.

このコンタクトホール1aは、マクロに見れば絶縁膜4
表面との境の角が落とされて第1図図示のコンタクトボ
ール1に近いが、ミクロに見ると、前記エツチングの特
性からエッチ領域7と絶縁膜4表面との境にはやはり角
が出来て、前記カバレージの点で充分であるとは云い難
い問題がある。
From a macroscopic perspective, this contact hole 1a corresponds to the insulating film 4.
Although the corner at the boundary with the surface is rounded and is similar to the contact ball 1 shown in FIG. 1, when viewed microscopically, due to the characteristics of the etching, there is still a corner at the boundary between the etched region 7 and the surface of the insulating film 4. However, there is a problem in that the coverage is not sufficient.

また、その大きさは、底部の大きさが開孔6の大きさと
なり、開孔6形成の技術的制約から小型化に限りがある
Furthermore, the size of the bottom portion is the same as the size of the aperture 6, and there is a limit to miniaturization due to technical constraints in forming the aperture 6.

(dl 発明の目的 本発明の目的は上記従来の問題に鑑み、絶縁膜に設ける
コンタクトホールを形成するに際して、該コンタクトボ
ールの内面と該絶縁膜表面との間を滑らかな朝顔型にし
、且つ該コンタクトポール底部の大きさを、エツチング
に先立って設けるレジスト膜開孔の大きさより小さくす
ることが可能な半導体装置の製造方法を提供するにある
(dl) Purpose of the Invention In view of the above-mentioned conventional problems, an object of the present invention is to form a smooth morning-glory shape between the inner surface of the contact ball and the surface of the insulating film when forming a contact hole in an insulating film, and to It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the size of the bottom of a contact pole can be made smaller than the size of a resist film opening formed prior to etching.

(e) 発明の構成 上記目的は、半導体基体上に絶縁11りを形成し、開花
部を有するレジスト膜を該絶縁股上に形成し、該開口部
において露出した絶縁膜を、該開花部にだれが生ずるよ
うに該レジスト膜の温度を制御しながら、異方性ドライ
エツチングすることにより、該絶縁膜に該絶縁膜の深さ
方向に沿って寸法が小さくなる開孔を形成することを特
徴とする半導体装置の製造方法によって達成される。
(e) Structure of the Invention The above object is to form an insulating film on a semiconductor substrate, form a resist film having a flowering portion on the insulation crotch, and extend the insulating film exposed at the opening into the flowering portion. The resist film is characterized by forming openings in the insulating film whose dimensions become smaller along the depth direction of the insulating film by performing anisotropic dry etching while controlling the temperature of the resist film so that This is achieved by a method of manufacturing a semiconductor device.

前記絶縁膜に形成される開孔は、その内面と該絶縁膜表
面との間が滑らかな朝顔型にするごとにより、所望の形
状を有するコンタクトホールとなり、該コンタクトボー
ル底部の大きさは前記レジスト膜開孔の初期の大きさよ
り小さくなる。
The opening formed in the insulating film is formed into a morning glory shape with a smooth surface between the inner surface and the surface of the insulating film, resulting in a contact hole having a desired shape, and the size of the bottom of the contact ball is equal to that of the resist. The initial size of the membrane pores becomes smaller.

(fl 発明の実施例 以下本発明の実施例を図により説明する。全図を通じ同
一符号は同一対象物を示す。
(fl Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same reference numerals indicate the same objects throughout the drawings.

第3図はコンタクトホールの本発明による形成方法の一
実施例を示した図(a)〜tel、第4図はその際のレ
ジスト膜開孔の寸法変化を示した図、第5図はその際に
使用するエツチング装置の一構成を示した図で、ibは
コンタクトボール、6aは開孔、)(8、fl bはエ
ッチ領域、10はウェハ、11はチャンバ、12は」二
部電極、13は下部電極、14は電源、15は熱交換器
、16はコントローラ、a、b、cは寸法をそれぞれ示
す。
FIG. 3 is a diagram (a) to tel showing an example of the method for forming a contact hole according to the present invention, FIG. 4 is a diagram showing the dimensional change of the resist film opening at that time, and FIG. In this figure, ib is a contact ball, 6a is an opening, ) (8, fl b is an etching region, 10 is a wafer, 11 is a chamber, 12 is a two-part electrode, 13 is a lower electrode, 14 is a power source, 15 is a heat exchanger, 16 is a controller, and a, b, and c indicate dimensions, respectively.

第3図図示のコンタクトホール形成方法は、予め図ff
l+図示のように1、絶縁膜4上にコンタクトボールの
上部の大きさく寸法a)に合わせた大きさの開孔6aを
有するレジスト膜5を形成し、これをマスクにして絶縁
膜4の開孔6a部を異方性ドライエッチングするが、同
時にレジスト膜5の温度を制御するところに特徴がある
The contact hole forming method shown in FIG.
1. As shown in the figure, 1. Form a resist film 5 on the insulating film 4 with an opening 6a having a size matching the size a) of the upper part of the contact ball, and use this as a mask to open the insulating film 4. Although the hole 6a portion is anisotropically dry etched, the feature is that the temperature of the resist film 5 is controlled at the same time.

即ち、エツチング開始と共にレジスト5の温度を例えば
約250℃程度に上げ、以後エツチングの深さが例えば
絶縁膜4の厚さの約1/2のところで該温度が例えば約
150℃程度になるように、エツチングの進行に並行さ
せて該温度を逐次下げながら、形成される孔の深さがト
ランジスタの一端子2に達するまで絶縁膜4をエッチす
る。
That is, at the start of etching, the temperature of the resist 5 is raised to, for example, about 250°C, and thereafter, when the etching depth is about 1/2 of the thickness of the insulating film 4, the temperature is raised to, for example, about 150°C. The insulating film 4 is etched while gradually lowering the temperature in parallel with the progress of etching until the depth of the hole to be formed reaches one terminal 2 of the transistor.

かくすることにより、最初は図(a)図示のようにエッ
チ領域8aの大きさ寸法が開孔6aの大きさ寸法である
aであるが、レジスト膜5はその温度が高いため開孔6
aの内側にだれて、開孔6aの大きさは時間の経過と共
に小さくなるので、エツチングの途中においては、図(
C1図示のようにエッチ領域8bの大きさ寸法がaより
小さなりとなる。一方、レジスト膜5のだれの速度は温
度が下がるに従い遅くなり、前記の約150℃程度で略
ゼロになるので、上記のエツチング過程における開孔6
aの大きさ寸法は第4図図示のように変化して、寸法C
で変化が停止する。従って、エツチングにより形成され
る孔形状は第3図(d)図示のように底部の大きさ寸法
がCである所望の朝顔型になり、レジスト膜5を除去す
れば、図(e1図示のように所望のコンタクトホール1
bが得られる。
As a result, initially the size of the etched region 8a is a, which is the size of the opening 6a, as shown in FIG.
The size of the opening 6a decreases over time as it sag inside the hole 6a, so during etching,
As shown in C1, the size of the etched region 8b is smaller than a. On the other hand, the rate of sagging of the resist film 5 slows down as the temperature decreases, and reaches approximately zero at about 150°C, so the openings 6 in the etching process described above decrease.
The size of a changes as shown in Fig. 4, and becomes the dimension C.
The change stops at . Therefore, the hole shape formed by etching becomes the desired morning glory shape with the bottom size C as shown in FIG. 3(d), and if the resist film 5 is removed, the desired contact hole 1
b is obtained.

具体的には上記の方法により、例えば、厚さ約1μmの
レジスト膜5の寸法aを約1.2μmφにすることによ
り、厚さ約1μmの絶縁膜4に、第1図図示の形状に極
めて近く然も寸法Cが約0.6μmφのコンタクトホー
ルを形成することが可能である。ちなみに、第2図図示
の方法で寸法Cを約0.6μmφにする場合にはレジス
ト膜5の開孔6の大きさ寸法を約0.6μmφにする必
要があり、高度の技術を必要とするので、本発明の方法
はトランジスタの小型化に、延いては半導体集積回路装
置の高集積化に寄与するところも大である。
Specifically, by using the above method, for example, by setting the dimension a of the resist film 5 having a thickness of approximately 1 μm to approximately 1.2 μmφ, the insulating film 4 having a thickness of approximately 1 μm is formed into the shape shown in FIG. It is possible to form a contact hole with a dimension C of about 0.6 μmφ in the near future. By the way, in order to make the dimension C about 0.6 μmφ by the method shown in FIG. 2, the size of the opening 6 in the resist film 5 needs to be about 0.6 μmφ, which requires advanced technology. Therefore, the method of the present invention greatly contributes to miniaturization of transistors and, by extension, to higher integration of semiconductor integrated circuit devices.

なお、前記250℃ないし150℃なる温度値は、レジ
スト膜5の挙動が上述の如くなるように選定された値で
あり、レジストが変わる場合には、その特性に合わせて
適宜定めればよい。
Note that the temperature value of 250° C. to 150° C. is selected so that the behavior of the resist film 5 is as described above, and when the resist is changed, it may be appropriately determined according to its characteristics.

また、上記のエツチングを行うには、例えば第5図に構
成を示す平行平板形ドライエツチング装置を用いればよ
い。チャンバ11内に設けられた上部電極12、下部電
極工3に電源14から高周波を印加して、異方性ドライ
エツチングを行うのは通常の通りであるが、下部電極1
3の中に熱交換器を備え、温度コントローラ16によっ
て下部電極13の温度を制御出来るようにしである。そ
して下部電極13に載置された第3図(al状態のウェ
ハ1oのレジスト膜5の上記温度制御は、ウェハ10本
体を介して下部電極13の温度制御によって可能である
Further, in order to carry out the above-mentioned etching, a parallel plate type dry etching apparatus, the configuration of which is shown in FIG. 5, may be used, for example. As usual, anisotropic dry etching is performed by applying high frequency from the power source 14 to the upper electrode 12 and the lower electrode 3 provided in the chamber 11.
3 is equipped with a heat exchanger, and the temperature of the lower electrode 13 can be controlled by a temperature controller 16. The above-mentioned temperature control of the resist film 5 of the wafer 1o (FIG. 3) placed on the lower electrode 13 (FIG. 3 (al) state) is possible by controlling the temperature of the lower electrode 13 via the wafer 10 body.

(g) 発明の効果 以上に説明したように、本発明による構成によれば、絶
縁膜に設けるコンタクトホールを形成するに際して、該
コンタクトホールの内面と該絶縁膜表面との間を滑らか
な朝顔型にし、且つ該コンタクトホール底部の大きさを
、エツチングに先立って設けるレジスト膜開孔の大きさ
より小さくすることが可能な半導体装置の製造方法を提
供することが出来て、カバレージのよいコンタクトホー
ルの提供と共に、トランジスタの小型化、延いては半導
体集積回路装置の高集積化を可能にさせる効果がある。
(g) Effects of the Invention As explained above, according to the structure of the present invention, when forming a contact hole provided in an insulating film, a smooth morning-glory shape is formed between the inner surface of the contact hole and the surface of the insulating film. Provided is a method for manufacturing a semiconductor device in which the size of the bottom of the contact hole can be made smaller than the size of an opening in a resist film formed prior to etching, and a contact hole with good coverage can be provided. At the same time, it has the effect of making it possible to reduce the size of transistors and, by extension, to increase the degree of integration of semiconductor integrated circuit devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はコンタクトホールの望ましい形状を示した図、
第2図はコンタクトボールの従来の形成方法の一実施例
を示した図(a)〜(d)、第3図はコンタクトホール
の本発明による形成方法の一実施例を示した図(a)〜
(81、第4図はその際のレジスト膜開孔の寸法変化を
示した図、第5図はその際に使用するエツチング装置の
一構成を示した図である。 図面において、1.1a、1bはコンタクトホール、2
はトランジスタの一端子、3は半導体基板、4は絶縁膜
、5はレジスト膜、6.6aは開孔、7.8.8a、 
8bはエッチ領域、10はウェハ、11はチャンバ、工
2は上部電極、13は下部電極、14は電源、15は熱
交換器、16はコントローラ、a、b、cは寸法をそれ
ぞれ示す。 □吋Ili″I 手S咀
Figure 1 is a diagram showing the desirable shape of the contact hole.
FIG. 2 is a diagram (a) to (d) showing an example of a conventional method for forming a contact ball, and FIG. 3 is a diagram (a) showing an example of a method for forming a contact hole according to the present invention. ~
(81, Fig. 4 is a diagram showing the dimensional change of the resist film opening at that time, and Fig. 5 is a diagram showing one configuration of the etching apparatus used at that time. In the drawings, 1.1a, 1b is a contact hole, 2
is one terminal of a transistor, 3 is a semiconductor substrate, 4 is an insulating film, 5 is a resist film, 6.6a is an opening, 7.8.8a,
8b is an etching region, 10 is a wafer, 11 is a chamber, 2 is an upper electrode, 13 is a lower electrode, 14 is a power source, 15 is a heat exchanger, 16 is a controller, and a, b, and c indicate dimensions, respectively. □吋Ili″I 手S Tsui

Claims (1)

【特許請求の範囲】[Claims] 半導体基体上に絶縁膜を形成し、開孔部を有するレジス
ト膜を該絶縁膜上に形成し、該開口部において露出した
絶縁膜を、該開孔部にだれが生ずるように該レジスト膜
の温度を制御しながら、異方性ドライエツチングするこ
とにより、該絶縁膜に該絶縁膜の深さ方向に沿って寸法
が小さくなる開孔を形成することを1芋徴とする半導体
装置の製造方法。
An insulating film is formed on a semiconductor substrate, a resist film having an opening is formed on the insulating film, and the insulating film exposed at the opening is formed in the resist film so that a droop is formed in the opening. A method for manufacturing a semiconductor device, the main feature of which is to form openings in the insulating film whose dimensions become smaller along the depth direction of the insulating film by anisotropic dry etching while controlling the temperature. .
JP2974784A 1984-02-20 1984-02-20 Manufacture of semiconductor device Pending JPS60173832A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2974784A JPS60173832A (en) 1984-02-20 1984-02-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2974784A JPS60173832A (en) 1984-02-20 1984-02-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60173832A true JPS60173832A (en) 1985-09-07

Family

ID=12284688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2974784A Pending JPS60173832A (en) 1984-02-20 1984-02-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60173832A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030050845A (en) * 2001-12-19 2003-06-25 주식회사 하이닉스반도체 Method for forming the semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030050845A (en) * 2001-12-19 2003-06-25 주식회사 하이닉스반도체 Method for forming the semiconductor device

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