JPS60172810A - Balanced/unbalanced converting circuit - Google Patents

Balanced/unbalanced converting circuit

Info

Publication number
JPS60172810A
JPS60172810A JP2439784A JP2439784A JPS60172810A JP S60172810 A JPS60172810 A JP S60172810A JP 2439784 A JP2439784 A JP 2439784A JP 2439784 A JP2439784 A JP 2439784A JP S60172810 A JPS60172810 A JP S60172810A
Authority
JP
Japan
Prior art keywords
transistor
emitter
resistor
current
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2439784A
Other languages
Japanese (ja)
Other versions
JPH0323012B2 (en
Inventor
Toshio Hayashi
林 敏夫
Tadakatsu Kimura
木村 忠勝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2439784A priority Critical patent/JPS60172810A/en
Publication of JPS60172810A publication Critical patent/JPS60172810A/en
Publication of JPH0323012B2 publication Critical patent/JPH0323012B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/32Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns

Landscapes

  • Networks Using Active Elements (AREA)
  • Interface Circuits In Exchanges (AREA)

Abstract

PURPOSE:To improve converting accuracy even if a characteristic of a transistor (TR) has a difference and to decrease the number of components by constituting the circuit with a TR operated as an emitter follower, flowing the same current to the TR of the same conduction type and cancelling the difference between the base and emitter between the TRs. CONSTITUTION:A voltage nearly equal to a potential drop component V2 of a resistor 5 is applied across a resistor R2 via TRs Q3, Q4 constituting the emitter follower, the voltage is converted into a collector current of the TRQ4, the current is converted again into a voltage by a resistor R1 and outputted via the emitter follower comprising a TRQ2. On the other hand, the potential drop V1 of the resistor 4 is outputted via a TRQ1, a resistor R1 and the TRQ2. Since each emitter current of the TRs Q2, Q3 is equal to that of a constant current source IB, a base-emitter voltage VBE of both the TRs is made equal. The emitter current of the TRs Q4, Q1 is made nearly equal by setting sufficiently to a small value of the constant current IS, the relation of VBE1=VBE2 is attained. Moreover, the resistors R1, R2 are made equal. Then the balanced inputs V1, V2 are converted into an unbalanced signal V3.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はライン回路におけるライン電流検出回路を高精
度で、かつ、少ない素子数で構成するための平衡/不平
衡変換回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a balanced/unbalanced conversion circuit for configuring a line current detection circuit in a line circuit with high precision and a small number of elements.

(従来技術) 従来のライン回路の給電部とライン電流検出部を第1図
(a)に示す。給電部は給電制御回路1.パワートラン
ジスタ2.3.抵抗4,5および局電源6とから構成さ
れ、上記パワートランジスタ2゜3のコレクタ電流は平
衡線路7,8を経由して、端末機器9に接続されていた
。給電制御回路1の具体例としては第1図(b)に示す
ものがあるが、その動作はここでは直接関係ないので省
略する。
(Prior Art) A power supply section and a line current detection section of a conventional line circuit are shown in FIG. 1(a). The power supply section is a power supply control circuit 1. Power transistor 2.3. It consists of resistors 4, 5 and a local power source 6, and the collector current of the power transistor 2.3 is connected to a terminal device 9 via balanced lines 7, 8. A specific example of the power supply control circuit 1 is shown in FIG. 1(b), but its operation is not directly relevant here and will therefore be omitted.

一方、ライン電流検出部は平衡/不平衡変換回路10 
、コンパレータll、参照電圧12.検出出力端子13
および抵抗4,5からなり、その動作は給電制御回路1
の中の抵抗1’4 、15 (第1図(b))を光分高
抵抗に設it しておくことによシ線路7,8に流れる
電流はほとんどパワートランジスタ2 、3 f:通っ
て抵抗4,5に流れるため線路電流は抵抗4,5の電位
降下として検出できる。
On the other hand, the line current detection section is a balanced/unbalanced conversion circuit 10.
, comparator ll, reference voltage 12. Detection output terminal 13
and resistors 4 and 5, the operation of which is performed by the power supply control circuit 1.
By setting the resistors 1'4 and 15 (Fig. 1(b)) in the power transistors 1'4 and 15 (Fig. 1(b)) to have a high resistance, almost all the current flowing to the lines 7 and 8 passes through the power transistors 2 and 3f. Since the line current flows through the resistors 4 and 5, it can be detected as a potential drop across the resistors 4 and 5.

そして抵抗4.5の電位降下分は平衡/不平衡変換回路
ioによシ両者の41電圧に変換され、コンパレータ1
1で参照電圧12と比較され、2値信号としてOUT端
子13に出力され、端末機器9側のオン/オフフックが
検出されることになる。
The potential drop across resistor 4.5 is converted to voltage 41 for both by balanced/unbalanced conversion circuit io, and comparator 1
1 and is compared with the reference voltage 12 and output as a binary signal to the OUT terminal 13 to detect on/off hook on the terminal device 9 side.

平衡/不平衡変換回路lOの具体例としては第1図(c
)に示すような差動増11]器16 、17 、18を
3個使用したものがある。その動作は抵抗4゜5の電位
降下を差動増巾器16.17で検出し、それらの出力を
差動増巾器18で加算して不平衡信号として出力するも
のである。
A specific example of the balanced/unbalanced conversion circuit IO is shown in Figure 1 (c
There is one using three differential amplifiers 16, 17, and 18 as shown in FIG. Its operation is such that the potential drop across the resistor 4.5 is detected by differential amplifiers 16 and 17, and their outputs are added together by differential amplifier 18 and output as an unbalanced signal.

ところで、このような平に/不平衡変換回路では、各差
動増巾器を構成する素子数が多いこと、又、局電源6が
一般に一48Vと大きいため、消費電力も大きくなる等
々の問題があった。
By the way, such a flat/unbalanced conversion circuit has problems such as the large number of elements constituting each differential amplifier, and the fact that the local power supply 6 is generally as large as -48V, resulting in high power consumption. was there.

(発明の目的) 本発明は上記の欠点を除去するために提案されたもので
あり、その目的とするところは、npnトランジスタと
pnp トランジスタの特性に差があっても、平翫/不
平衡変換の精度が高く、かつ、少ない素子数で平衡/不
平衡変換回路を実現することにある。
(Objective of the Invention) The present invention has been proposed to eliminate the above-mentioned drawbacks, and its purpose is to achieve flat/unbalanced conversion even if there is a difference in characteristics between an npn transistor and a pnp transistor. The object of the present invention is to realize a balanced/unbalanced conversion circuit with high precision and a small number of elements.

(発明の第14成) 上記の目的を達成するため、本発明は電子化された平衡
/不平衡変換回路において、平価信号の一方の信号V1
を第1のトランジスタQ1のベースに印加し、この第1
のトランジスタQlのコレクタを定電位点に接続し、第
1の抵抗R,の両端を前記第1のトランジスタQlのエ
ミッタと、前記第1のトランジスタQlと相補の導電型
の第2のトランジスタQ2のベースとにそれぞれ接続し
、定電流源工3を前記第2のトランジスタQ、のエミッ
タに接続し、前記平侠1信号の他方の信号v2を前記第
2のトランジスタQ2ト同4 電型の第3のトランジス
タQ3のベースに印加し、この第3のトランジスタQ3
のエミツタケ前記第2のトランジスタQ2のコレクタと
、前ml第1のトランジスタQ1と同等電型の第4のト
ランジスタQ4のベースとに接続し、この第4のトラン
ジスタQ4のエミッタを第2の抵抗を介し前記第3のト
ランジスタQ3のコレクタと共に他の定電位点に接続し
、前記第4のトランジスタQ4のコレクタを前記詑2の
トランジスタQ2のベースに接続し、仁の第2のトラン
ジスタQ2のエミッタより出力信号を)4y、、!7出
してなることを重機とする平衡/不平衡変換回路を発明
の要旨とするものである。
(Fourteenth aspect of the invention) In order to achieve the above object, the present invention provides an electronic balanced/unbalanced conversion circuit in which one of the equalized signals V1
is applied to the base of the first transistor Q1, and this first
The collector of the transistor Ql is connected to a constant potential point, and both ends of the first resistor R are connected to the emitter of the first transistor Ql, and to the emitter of the second transistor Q2 of a conductivity type complementary to the first transistor Ql. A constant current source 3 is connected to the emitter of the second transistor Q, and the other signal v2 of the second transistor Q is connected to the second transistor Q2 and the second transistor Q of the same voltage type. 3 to the base of the third transistor Q3, and this third transistor Q3
The emitter of the fourth transistor Q4 is connected to the collector of the second transistor Q2 and the base of a fourth transistor Q4 of the same electric type as the first transistor Q1, and the emitter of the fourth transistor Q4 is connected to the second resistor. The collector of the fourth transistor Q4 is connected to the base of the second transistor Q2, and the collector of the fourth transistor Q4 is connected to the base of the third transistor Q2 through the emitter of the second transistor Q2. Output signal) 4y,,! The gist of the invention is a balanced/unbalanced conversion circuit for heavy machinery.

次に本発明の実施例を添付図面について説明する。なお
実施例は一つの例示であって、本発明の411神を逸脱
しない範1(Nで、イ事々の変更あるいは改良全行いう
ろことは言うまでもない。
Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiment is merely an illustration, and it goes without saying that all modifications and improvements may be made without departing from the scope of the present invention.

しかして、本発明は構成素子を少なくするためエミッタ
ホロワ−として動作するトランジスタを中心に構成し、
同一導電型のトランジスタには、同一1W、’fAFを
?+If、l−、トランジスタI!Ilノヘース−エs
ツタ間電圧V□の差異が互いにキャンセルしあうように
して高精度化を図っている。
Therefore, in order to reduce the number of constituent elements, the present invention is mainly composed of transistors that operate as emitter followers.
Is the same 1W and 'fAF for transistors of the same conductivity type? +If, l-, transistor I! Ilnohes-S
High precision is achieved by canceling out the differences in the voltage V□ between the vines.

第2図に本発明の一実施例を示す。その構成はnpn 
トランジスタQl 1.、Qiと、pnI) )ランジ
スタQ2゜Q、と定電流源工、、工8と、抵抗R11R
2とからなる。
FIG. 2 shows an embodiment of the present invention. Its composition is npn
Transistor Ql 1. , Qi, pnI) ) Transistor Q2゜Q, constant current source, , 8, and resistor R11R
It consists of 2.

なお、第2図における平衡/不平衡変換回路10は第1
図(a)における平衡/不平衡変換回路10に置き換わ
るものであシ、他の構成は第1図(a)に示したのと同
様である。
Note that the balanced/unbalanced conversion circuit 10 in FIG.
This circuit replaces the balanced/unbalanced conversion circuit 10 shown in FIG. 1(a), and the other configuration is the same as that shown in FIG. 1(a).

その動作は抵抗5の電位降下分V2は端子t+jを介し
エミッタホロワを構成するトランジスタQ3 +Q4を
経て、抵抗R2の両端にほぼ等しい電圧が印加され、ト
ランジスタQ4のコレクタ電流に変換され、抵抗R8で
再び電圧に変換され、トランジスタQ2のエミッタホロ
ワ−を経て出力される。一方、抵抗4の電位降下分■1
は端子g、hを介しトランジスタQ4+抵抗R,,)ラ
ンジスタQ2を経て出力される。
The operation is such that the potential drop V2 across the resistor 5 passes through the terminal t+j and the transistor Q3+Q4 that constitutes the emitter follower, and a substantially equal voltage is applied across the resistor R2, which is converted into the collector current of the transistor Q4, and then again through the resistor R8. It is converted into a voltage and output via the emitter follower of transistor Q2. On the other hand, the potential drop of resistor 4 ■1
is outputted via terminals g and h through transistor Q4 + resistor R, . . . ) transistor Q2.

これを式で示すと、 vs=v+ IVBIII−R+((”2”l■ngs
l lVB[c41)/Rz ) + I vBE21
 −− (1)となる。但し、Vゆ1はトランジスタQ
1のベース・エミッタ間電圧であシ、また、各トランジ
スタのベース電流は小さいとして無視した。ことでトラ
ンジスタQ2のコレクタとトランジスタQ3のエミッタ
が接続されているため、トランジスタQ2のエミッタ電
流とトランジスタQ3のエミッタ電流はともに定電流源
工8のそれ、と等しくなる。そのため■BFi3=■麗
2とおけるO また、トランジスタQ4のコレクタ1■、流はトランジ
スタQ1に流れていることから定′1L流工8のイ1η
を充分小さく設定することによシトランジスタQ4とト
ランジスタQ1のエミッタ電流はほぼ等じくなり、従っ
てVBl夏”” VB+!+4とおける0また抵抗R1
とR2は等しくなるように設ML しておく。しかして
、これらの結果を(1)式に代入するとv3=vl −
■2 (lvB+a+l 1vn1.141) (lv
Bg、l−1VB1!!21)=■1−V2 ・・・・
(2)となシ、平衡人力V、 、 V2が不平衡信号V
、に変換されることがわかる。なお、定電流工8はスタ
ートアップ用のものであシ、■2=0のときトランジス
タQ4のコしクタ電流が0となるが、定電流IBによシ
トランジスタQ2のベース電流が供給されるようにする
ためのものである。
To express this in a formula, vs=v+ IVBIII-R+(("2"l■ngs
l lVB[c41)/Rz ) + I vBE21
--(1). However, Vyu1 is transistor Q
The base-emitter voltage was 1, and the base current of each transistor was ignored as it was small. Since the collector of the transistor Q2 and the emitter of the transistor Q3 are connected, the emitter current of the transistor Q2 and the emitter current of the transistor Q3 are both equal to that of the constant current source 8. Therefore, ■ BFi3 = ■ Rei 2 O Also, since the collector 1 of transistor Q4, the current flows to transistor Q1, the constant '1L flow 8's I1η
By setting sufficiently small, the emitter currents of transistor Q4 and transistor Q1 become almost equal, so that VB+! +4 and 0 and resistance R1
ML is set so that and R2 are equal. Therefore, by substituting these results into equation (1), v3=vl −
■2 (lvB+a+l 1vn1.141) (lv
Bg,l-1VB1! ! 21)=■1-V2...
(2) Tonashi, balanced human power V, , V2 is unbalanced signal V
It can be seen that it is converted to . Note that the constant current generator 8 is for startup purposes, and when 2 = 0, the collector current of the transistor Q4 becomes 0, but the constant current IB supplies the base current of the transistor Q2. It is for the purpose of

ここで(1)式から(2)式を導ひくために用いた仮定
はいずれも集積回路では実現容易なものはかシであシ、
即ち、同一導電型のトランジスタ間のベース・エミッタ
間電圧vBl!のバラツキは数mV程度と小さく、又抵
抗の比精度も1チ程度は得られるため、(2)式の近似
式はかなり精度が高い。
None of the assumptions used to derive equation (2) from equation (1) are easy to implement in integrated circuits.
That is, the base-emitter voltage vBl! between transistors of the same conductivity type. The variation in is as small as about several mV, and the resistor's specific accuracy can be obtained on the order of 1 inch, so the approximate expression (2) is quite accurate.

なお、本実施例はバイポーラトランジスタの場合につい
て述べたが、F刊Tを適用した場合も全く同様の効果が
期待できるのは説明するまでもない。
Although this embodiment has been described in the case of a bipolar transistor, it is needless to say that the same effect can be expected even when F-T is applied.

(発明の効果) 以上説明したように、本発明の平衡/不平衡変換回路は
構成素子数が少なく経済的であシ、具体的には第1図(
c)で示した従来の回路では差動増幅器の個々に20程
度の素子が必要であるとすると全体で60程度の素子で
あったものが、本発明によれば電流源を構成する素子も
含めて10程度の素子で得られ、その効果は大きい。又
、同一導電型トランジスタのベース・エミッタ間電圧V
ngのバラツキさえ小さく押えられれは、入神トランジ
スタ間のトランジスタ’F−性差は精度に効かないため
非常に高iif度に、平衡/不平餉変換ができるという
利点がある。
(Effects of the Invention) As explained above, the balanced/unbalanced conversion circuit of the present invention has a small number of components and is economical.
In the conventional circuit shown in c), if each differential amplifier requires about 20 elements, the total number of elements is about 60, but according to the present invention, the number of elements including the elements constituting the current source is reduced. This can be achieved with about 10 elements, and the effect is great. In addition, the base-emitter voltage V of transistors of the same conductivity type
If even the variation in ng is kept small, there is an advantage that balanced/unbalanced conversion can be performed with a very high degree of IIF, since the difference in transistor 'F' between input transistors has no effect on accuracy.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は従来のライン回路の電流供給部とライン
電流検出部の回路構成図、第1図(b)は給電制御回路
の具体的回路図、第1図(c)は平衡/不平衡変換回路
の具体的回路図、第2図は本発明による平衡/不平衡変
換回路の実施例を示す具体的回路図である。 1・・給電制御回路、2,3・・パワートランジスタ、
4.5・・・抵抗、7,8・・千に線路、9・・端末機
器、1o 、 to’・・・平衡/′不平衡変換回路、
11・・コンパレータ、12・・・参照電圧、13・・
出力端子、14.15・・抵抗、16.17.18・・
・差動増巾器、Q4 + Q4 ・’・npnトランジ
スタ、Q2 + Q3 ・= pnpトランジスタs 
IB + ■8・・定電流源、R□、R2・・・抵抗 第 ] 図 (a)
FIG. 1(a) is a circuit diagram of the current supply section and line current detection section of a conventional line circuit, FIG. 1(b) is a specific circuit diagram of the power supply control circuit, and FIG. 1(c) is a balanced/ Specific circuit diagram of unbalanced conversion circuit. FIG. 2 is a specific circuit diagram showing an embodiment of the balanced/unbalanced conversion circuit according to the present invention. 1...Power supply control circuit, 2, 3...Power transistor,
4.5...Resistance, 7, 8...Line, 9...Terminal equipment, 1o, to'...Balanced/'unbalanced conversion circuit,
11... Comparator, 12... Reference voltage, 13...
Output terminal, 14.15...Resistance, 16.17.18...
・Differential amplifier, Q4 + Q4 ・'・npn transistor, Q2 + Q3 ・= pnp transistor s
IB + ■8...Constant current source, R□, R2...Resistor] Figure (a)

Claims (1)

【特許請求の範囲】[Claims] 電子化された平に/不平衡変換回路において、平衡信号
の一方の信号V1を第1のトランジスタQ1ノヘースに
印加し、この第1のトランジスタQ、のコレクタを定電
位点に接続し1.第1の抵抗只□の両端を前記第1のト
ランジスタQ+のエミッタと、前記第1のトランジスタ
Q+と相補の導電型の第2のトランジスタQ2のベース
とにそれぞれ接続し、定’4流源工、を前記第2のトラ
ンジスタQ2のエミッタ・ に接続し、前記平衡信号の
他方の信号■2を前記第2のトランジスタQ2と同導電
型の第3のトランジスタQ+1のベースに印加し、この
第3のトランジスタQ、のエミッタを前記第2のトラン
ジスタQ2のコレクタと、前記第1のトランジスタQ、
と同導電型め第4のトランジスタQ4のベースとに接続
し、この第4のトランジスタQ4のエミッタを第2の抵
抗を介し前記第3のトランジスタQ3のコレクタ電流に
他の定電位点に接続し、前記第4のトランジスタQ4の
コレクタを前記第2のトランジスタQ2のベースに接続
し、この第2のトランジスタQ、のエミッタよシ出力信
号を取シ出してなることを重機とする平衡/不平衡変換
回路。
In the electronic flat/unbalanced conversion circuit, one of the balanced signals V1 is applied to the base of the first transistor Q1, and the collector of the first transistor Q is connected to a constant potential point.1. Both ends of the first resistor are connected to the emitter of the first transistor Q+ and the base of a second transistor Q2 of a conductivity type complementary to the first transistor Q+, and , is connected to the emitter of the second transistor Q2, and the other signal 2 of the balanced signals is applied to the base of a third transistor Q+1 having the same conductivity type as the second transistor Q2. The emitter of the transistor Q, and the collector of the second transistor Q2, and the first transistor Q,
and the base of a fourth transistor Q4 of the same conductivity type, and the emitter of this fourth transistor Q4 is connected to the collector current of the third transistor Q3 via a second resistor to another constant potential point. , the collector of the fourth transistor Q4 is connected to the base of the second transistor Q2, and the output signal is taken out from the emitter of the second transistor Q. conversion circuit.
JP2439784A 1984-02-14 1984-02-14 Balanced/unbalanced converting circuit Granted JPS60172810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2439784A JPS60172810A (en) 1984-02-14 1984-02-14 Balanced/unbalanced converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2439784A JPS60172810A (en) 1984-02-14 1984-02-14 Balanced/unbalanced converting circuit

Publications (2)

Publication Number Publication Date
JPS60172810A true JPS60172810A (en) 1985-09-06
JPH0323012B2 JPH0323012B2 (en) 1991-03-28

Family

ID=12137026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2439784A Granted JPS60172810A (en) 1984-02-14 1984-02-14 Balanced/unbalanced converting circuit

Country Status (1)

Country Link
JP (1) JPS60172810A (en)

Also Published As

Publication number Publication date
JPH0323012B2 (en) 1991-03-28

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