JP2855726B2 - Reference voltage generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generation circuit used for, for example, an integrated circuit that operates at a low voltage.

[Summary of the Invention]

The present invention relates to a reference voltage generation circuit used for, for example, an integrated circuit that operates at a low voltage, and an operation amplification circuit configured to output an offset voltage proportional to a thermal voltage, and an offset voltage from the operation amplification circuit being reduced. A bipolar transistor supplied to a base, a collector of the bipolar transistor is connected to one end of the DC power supply, and an emitter of the bipolar transistor is connected to the DC power supply via a series circuit of first and second resistors. Connected to the other end, the connection point of the first and second resistors is connected to the non-inverting input terminal of the operational amplifier circuit, and the base of the bipolar transistor is connected to the series circuit of the third and fourth resistors. Connected to the emitter of the bipolar transistor and to the inverting input terminal of the operational amplifier circuit. By deriving the output terminal 3 and the fourth resistor connection points, in which to be able to generate a stable reference voltage below the DC power supply relatively low e.g. 1V.

[Conventional technology]

Conventionally, a so-called bandgap regulator as shown in FIG. 3 has been proposed as a reference voltage generating circuit used for an integrated circuit operating at a low voltage. In this FIG.
(1) indicates a power supply terminal to which a DC voltage is supplied. This power supply terminal (1) is connected via a resistor (2) to a connection point between the collector and the base of a diode-connected npn transistor (3). The emitter of this transistor (3) is connected to the junction between the collector and the base of a diode-connected npn transistor (4), and the emitter of this transistor (4) is grounded.

The connection point between the resistor (2) and the collector of the transistor (3) is connected to the base of the npn transistor (5), and the collector of the transistor (5) is connected to the collector of the diode-connected pnp transistor (6). The transistor (6) is connected to the connection point of the base, and the emitter of the transistor (6) is connected to the power supply terminal (1) via the resistor (7).
Further, the emitter of the transistor (5) is connected to the collector and base connection points of a pnp transistor (9) having a multi-emitter configuration whose diode area is twice as large as that of a normal emitter through a resistor (8). The emitter of this transistor (9) is grounded. The junction between the collector and base of the transistor (9) is connected to the base of an npn transistor (10) having a multi-emitter configuration in which a diode and a current mirror circuit constituting the current mirror circuit have an area of 20 times that of a normal emitter. , The emitter of the transistor (10) is grounded via a resistor (11), and the collector of the transistor (10) is connected via a resistor (12) to a transistor (5) and an npn transistor (13). ), And the collector of this transistor (13) is connected to the collector and base connection of the transistor (6). The collector of the transistor (10) is connected to the base of the transistor (13) via the capacitor (14).
The bases of the double-emitter type npn transistors (15) and (16) are connected to the respective bases, and the respective emitters of the transistors (15) and (16) are grounded.
The collector of this transistor (16) is connected via a resistor (17) to the emitter of a diode-connected npn transistor (18), and the junction of the collector and base of this transistor (18) is connected to a pnp transistor (19). And the connection point between the collector and the base of the transistor (18) is connected to the base of each of the transistor (13) and the npn transistors (20) and (21).
The emitter of this transistor (19) is connected to a resistor (22)
To the power supply terminal (1), and the base of the transistor (19) is connected to the connection point between the base and the collector of the transistor (6). Also this transistor (21)
Is connected to the collector and base of a diode-connected npn transistor (24) via a resistor (23), and the emitter of this transistor (24) is grounded via a resistor (25). The collector of the transistor (21) is connected to the power supply terminal (1).

The collector of the transistor (15) is connected to the emitter of the transistor (20) via the resistor (26), the collector of the transistor (20) is connected to the power supply terminal (1), and the emitter of the transistor (20) is connected. And resistors (26)
The output terminal (27) is derived from the connection point with.

FIG. 3 is configured as described above, and it is assumed that the currents flowing through the respective emitters of the transistors (9) and (10) are equal, and the transistors (9) and (10) constitute a current mirror circuit. Therefore, when the respective base-emitter voltages are V _BE9 and V _BE10 , V _BE9 = V _BE10 + I ₁₀ × R ₁₁ ‥‥ (1) Here I ₁₀ is the resistance of the transistor emitter current of (10), R ₁₁ is the resistor (11).

Generally, the relationship between the base-emitter voltage V _BE of a transistor and the emitter current I is Here, _IS is the saturation current of the transistor, q is the charge of electrons, k is the Boltzmann constant, and T is the absolute temperature. From this equation Is led. From this, equation (1) becomes Becomes Here I ₉ and I ₁₀ are respective emitter currents of the respective transistors (9) and (10), I _S9 and I ₁₀ are the respective saturation currents of the respective Toranjita (9) and (10). From this equation, the current I ₁₀ flowing through the emitter of the transistor (10)
Is It is. Here, the emitter currents of the transistors (9) and (10) are I ₉ = I ₁₀ and the saturation currents I _S9 and I _S10 are proportional to the area of the emitters of the transistors (9) and (10), respectively. The ratio n of the saturation current of 9) and (10) is It is.

Therefore , And the expression (5) than I ₁₀ is proportional to the absolute temperature. Next determine the output voltage V _out of the output terminal (27) derived from the emitter of the transistor (20), which is _{V out = V BE15 + I 10} × R 12 + V BE13 -V BE20 ‥‥ (6). Here V _BE13, V _BE15 and V _BE20 are each transistor (13), the resistance value of (15) and the base-emitter voltage of each of the (20), R ₁₂ is a resistor (12). Here, since the transistor (10) forms a current mirror circuit with the transistor (9), the base voltage of the transistor (10) is equal to the collector voltage of the transistor (10). It is equal to the base voltage of (10), so the base-emitter voltage of each of the transistors (20) and (13)
Equal to the V _BE20 and V _BE13, become Therefore _{V out = V BE15 + I 10} × R 12 ‥‥ (8). Substituting equation (5) into equation (8) gives Becomes The equation (9) is the temperature coefficient of V _BE15 of the first term on the right side of the generally a negative coefficient at -2 mV / ° C., the resistor because the second term is a positive factor in V _T l _{n n} (11) and (12) of each of the resistance values R ₁₁ and each of R ₁₂ 's values and the transistor (9) and (10) temperature dependency is lost set so can by selecting the emitter area ratio n of the respective.

And so on.

Here determined per Examples of the output voltage V _out (5) a _{I 10 = V T l n n} / R 11 from formula, It is. Here when the R ₁₁ and R ₁₂ and each 6Keiomega and _{60kΩ I 10 = 26mV × l n} 10 / 6kΩ = 26mV × 2.3 / 6kΩ = 10μA Thus _{V out = V BE15 + R 12} × I 10 = 0.7V + 60kΩ × 10μA = 0.7V + 0.6V = 1.3V.

[Problems to be solved by the invention]

In such a conventional band gap regulator, there is a disadvantage that the DC voltage supplied to the power supply terminal (1) is relatively high. That is 0.6～0.7V, require 0.6～0.7V the collector (or base)-emitter V _BE6 of the transistor (6) as the base-emitter voltage V _BE15 of the transistor (15), the collector and the transistor (13) Emitter voltage
V _CE13 supply voltage V ₀ when the 0.1V to the _{V 0 = V BE15 + I 10} × R 12 + V CE13 + V BE6> V BE15 + V CE13 + V BE6 = 0.7 + 0.1 + 0.7 , and the fact 2V above 1.5V or higher I need.

In view of the above, an object of the present invention is to make it possible to obtain a stable reference voltage even with a relatively low DC power supply of, for example, 1 V or less.

[Means for solving the problem]

The present invention reference voltage generating circuit, for example a first view and a second as shown in FIG thermal voltage V _T so as to output an offset voltage proportional to the operational amplifier circuit (28), from the operational amplifier circuit (28) And a bipolar transistor (29) whose base is supplied with the offset voltage of (i). A collector of the bipolar transistor (29) is connected to one end (1) of the DC power supply, and an emitter of the bipolar transistor (29) is connected to the first terminal. And a second resistor (30) and (31) connected to the other end (ground) of the DC power supply through a series circuit, and the first and second resistors (30) and (31) are connected. A point is connected to the non-inverting input terminal of the operational amplifier circuit (28), and the base of the bipolar transistor (29) is connected to the bipolar transistor via a series circuit of third and fourth resistors (32) and (33). Tran Connected to the inverting input terminal of the operational amplifier circuit (28) and to the output terminal (27) from the connection point of the third and fourth resistors (32) and (33). Is derived.

[Action]

According to斯Ru present invention a positive voltage and adding and outputting voltages proportional to the base-emitter voltage V _BE of the bipolar transistor having a negative temperature coefficient of voltage proportional to the thermal voltage V _T having a temperature coefficient Because it obtains, a stable reference voltage whose voltage does not change with temperature can be generated. In addition, this stable reference voltage can be generated even with a power supply voltage such as 1 V DC voltage that can operate the operational amplifier circuit (28). can do.

〔Example〕

Hereinafter, an embodiment of the reference voltage generating circuit of the present invention will be described with reference to FIG. In FIG. 2, the first
Parts corresponding to those in the drawings are denoted by the same reference numerals.

(34) and (35) show pnp transistors constituting the first stage of the operational amplifier circuit (28), respectively. This transistor (35) is a multi-emitter transistor having an emitter area eight times as large as that of a normal transistor. The emitters of (34) and (35) are connected to each other, and the connection point of this emitter is connected to the collector of a pnp transistor (36).
The emitter of the transistor (36) is connected to the power supply terminal (1) via a resistor (37), and the transistor (36)
Are connected to the respective bases of a pnp transistor (38), which will be described later, and a pnp transistor (39) having a multi-emitter configuration whose emitter area is eight times the normal area. Also, the collector of the transistor (34) has a normal emitter area.
Dipn-connected pnp with 20x multi-emitter configuration
It is connected to the junction between the collector and base of the transistor (40), and the emitter of the transistor (40) is grounded. . Also, the collector of the transistor (35) is connected to the collector of an npn-type transistor (41) having a multi-emitter configuration whose emitter area is 20 times that of a normal transistor, and the emitter of the transistor (41) is grounded. The base is connected to the junction between the base and the collector of the transistor (40). A connection point between the collectors of the transistors (35) and (41) is connected to the base of an npn transistor (42) having a multi-emitter configuration whose emitter area is 20 times larger than that of a normal emitter, and a connection point of the collector ( 43) is connected to the collector of this transistor (42), the emitter of this transistor (42) is grounded, and the collector of this transistor (42) is diode-connected.
The collector and base of the npn transistor (38) are connected to a connection point, and the emitter of the transistor (38) is connected to the power supply terminal (1) via the resistor (43). The base of the transistor (38) is connected to the base of the transistor (39), the emitter of the transistor (39) is connected to the power supply terminal (1), and the collector of the transistor (39) is connected to the emitter having a normal area of 20. Double multi-emitter configuration
npn-type transistor (bipolar transistor) (29)
Connect to the base. In this case, the transistor (34),
The operational amplifier circuit (28) is composed of (35), (38), (39), (40), (41), and (42).

The emitter of the transistor (29) is grounded via a series circuit of resistors (30) and (31), and the resistor (30)
And the connection point of (31) is connected to the base of the transistor (34) constituting the first stage of the operational amplifier circuit (28), and the base of the transistor (29) is connected to the series circuit of the resistors (32) and (33). Connected to the emitter of the transistor (29), the emitter of the transistor (29) is connected to the base of the transistor (35) constituting the first stage of the operational amplifier circuit (28), and the resistor (32) The output terminal (27) is derived from the connection point of (33).

In this example, the two transistors (34) and (35) constituting the first stage of the operational amplifier circuit (28) have different emitter areas, and the ratio is defined as m: n.
In this example, V _T offset is generated as 1: 8,
Since the collector currents of the transistors (34) and (35) are equalized by the current mirror circuits (40) and (41), the difference ΔV _BE between the base voltages of the transistors (35) and (34) is It is. The base of the transistor (35) and the resistor (3
Voltage V _a of the connection point a between 3) and the resistor (30) It is. Here, R ₃₀ and R ₃₁ are resistors (30) and (3
This is the resistance value of 1). The voltage between the connection point b and the connection point a of the base of the transistor (29) and the resistor (32) is the base-emitter voltage V of this transistor (29).
_BE29 and this voltage V _BE29 is _connected to resistors (32) and (33)
The voltage V _ac between the output terminal (27) and the connection point a divided by It is. Here, R ₃₂ and R ₃₃ are resistors (32) and (3
3) is the resistance value. Therefore, the output voltage V _c obtained at the output terminal (27) Becomes Here, V _{T of} the first term is V _T = k · T / q, has a positive temperature coefficient, and its value is around 3300 near room temperature.
ppm / ° C (about 86 µV / ° C). The forward voltage V _BE of the bipolar transistor (29) of the second term has a negative temperature coefficient, and its value is about −2 mV / ° C. Therefore, in this example The resistance of the resistors (30) and (31) and the transistor (3
Select the area of each emitter of 4) and (35) and
3.8, if the respective resistance values of the resistors (32) and (33) are selected and set to 1 / 5.4, the first and second terms cancel each other's temperature characteristics, and the output terminal (27) stable reference voltage V _c does not change in voltage with temperature is obtained.

In this example, for example, the area ratio of the emitters of the transistors (34) and (35) is 1: 8, and the resistors (30), (31),
When the values of (32) and (33) are 5.4 kΩ, 4.5 kΩ, 10 kΩ and 25 kΩ, a reference voltage of 200 mV is obtained at the output terminal (27).

In this case, as the power supply voltage supplied to the power supply terminal (1),
Transistor (40) base-emitter voltage V _BE40
If the voltage is the sum of 0.7V and 0.1V of the collector-emitter voltage of each of the transistors (34) and (36), for example, 0.9V or more, the reference voltage generation circuit of this example operates and a stable reference voltage is obtained. There are benefits that can occur. Further, according to this embodiment, there is an advantage that the configuration is simpler than that of the conventional example shown in FIG.

It should be noted that the present invention is not limited to the above-described embodiment, but can adopt various other configurations without departing from the gist of the present invention.

〔The invention's effect〕

According to the present invention, there is an advantage that a stable reference voltage can be generated even with a relatively low DC power supply of, for example, about 1 V with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of an example of a reference voltage generation circuit of the present invention,
FIG. 2 is a configuration diagram showing an embodiment of the reference voltage generation circuit of the present invention, and FIG. 3 is a configuration diagram showing an example of a conventional reference voltage generation circuit. (1) is a power supply terminal, (27) is an output terminal, (28) is an operational amplifier circuit, (29) is a bipolar transistor, (30),
(31), (32) and (33) are resistors respectively.

Claims (1)

(57) [Claims] 1. An operational amplifier circuit for outputting an offset voltage proportional to a thermal voltage, and a bipolar transistor to which a base is supplied with an offset voltage from the operational amplifier circuit, wherein a collector of the bipolar transistor is provided. Is connected to one end of a DC power supply, and the emitter of the bipolar transistor is connected to the other end of the DC power supply via a series circuit of first and second resistors, and the connection of the first and second resistors is performed. A point is connected to the non-inverting input terminal of the operational amplifier circuit, the base of the bipolar transistor is connected to the emitter of the bipolar transistor via a series circuit of third and fourth resistors, and the inverting terminal of the operational amplifier circuit is connected. A reference voltage which is connected to an input terminal and an output terminal is derived from a connection point of the third and fourth resistors. Raw circuit.