JPS60169919A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce power consumption at holding state by delaying an operating speed slower than normal state when minimum necessary operation is to be executed at the holding state. CONSTITUTION:A microcomputer outputs a signal having prescribed frequency from its oscillation circuit 1 and divides its frequency by a frequency dividing circuit 3. Both outputs CLK1, CLK2 from the circuits 1, 2 are impressed to a switching circuit 3, which is controlled by a control signal CHG from an operation control circuit 5 to output any one output selectively to a clock generator 4. The generator 4 forms a clock signal CP on the basis of the selected signal CLK and outputs the clock signal CP to respective internal circuits. When holding state is detected 6 at a time of power failure, a switching circuit 3 selects the frequency-divided output CLK2, so that the operating speed of the microcomputer is delayed by the frequency divided by the frequency dividing circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of use in harassment The present invention relates to a microcomputer having a hold function and a halt function.

(b) Prior art In general, when a power supply stabilized by rectifying an open power supply is used as a power supply for a microcomputer, when a power outage etc. occurs, the operation of the microcombiator stops, and the accumulation due to the previous operation occurs. The problem is that all the data that was created will be lost.

Therefore, a method is adopted in which the power source is backed up by batteries etc. in the event of a power outage, but if the microcomputer continues to operate in the backup state, the power consumption of the battery etc. will become large, so it is necessary to detect when the backup state has entered. A function for stopping the operation of the microcomputer, that is, a hold function is provided.

In addition, microcomputers made for electronic watches are equipped with a function to stop operation except when necessary, in order to reduce power consumption, as disclosed in Japanese Patent Application Laid-open No. 53-143368. . That is, when a predetermined process is completed, a halt instruction is prepared at the end of the program, and the operation of the microcomputer is stopped by executing the halt instruction, which is called a halt function. Also, when returning from a halt state,
This is when an output signal, such as an IHz signal, from a frequency dividing circuit operating independently of the halt function is applied, and then the predetermined operation is resumed.

By the way, when a micro combiator having a clock or timer function is backed up by a battery or the like during a power outage, it is necessary to perform a timekeeping operation intermittently during a backup state, that is, a hold state. However, since the backup voltage is set as low as possible in order to reduce power consumption as much as possible, the operation during the backup state must be set to be fast enough to operate at that voltage. In this case, the speed E has to be the same even in the normal energized state, resulting in a decrease in the amount of work that can be processed and the drawback that the microcomputer's capabilities cannot be fully utilized.

(c) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and is equipped with a hold function and a halt function, and operates at high speed in a normal energized state, and in a backup state in the event of a power outage. The purpose of this is to reduce power consumption when the rudder is energized and when stopped by manufacturing at a low speed when restarting the operation.

B) Structure of the Invention The present invention has a halt function that stops the operation when a halt command is executed, and when a signal of a predetermined level is applied to the hold terminal, a hold state is entered by the execution of the halt command. A microcomputer,
an oscillation circuit that generates a frequency signal for creating a system clock signal; a first flip-flop that is set by execution of the halt instruction and reset by a predetermined signal, and whose output controls the oscillation of the oscillation circuit; a frequency divider circuit that divides the oscillation output of the oscillation circuit into a predetermined frequency; and a switching circuit that switches between the frequency division output of the frequency divider circuit and the oscillation output and applies it to a clock generator that creates a system clock signal. , a second flip-flop 70 that detects that a signal of a predetermined level is applied to the hold terminal and controls the switching circuit, and the first flip-flop set during the hold function detects that a signal of a predetermined level is applied to the hold terminal. When the operation stoppage is canceled by being reset by
The predetermined signal for resetting the lip-flop is at least a signal for timekeeping.

(E) Embodiment FIG. 1 is a partial block diagram of a micro combinator according to an embodiment of the present invention. The oscillation circuit (1) generates a signal of a predetermined frequency, for example, 200Kllz or 400KH, by connecting a ceramic oscillator, a crystal oscillator, or an R, C (resistance, capacitor) circuit to an external terminal.
Oscillates and outputs the z signal.

The frequency dividing circuit (2) is, for example, a 1/4 frequency dividing circuit, which divides the frequency of the oscillation output CLKI applied from the optical oscillation circuit (11) and outputs the frequency-divided output CLK2.
Both KI and the frequency-divided output CLK2 are applied to a switching circuit (3), and the switching circuit (3) is controlled by a control signal CHG and selectively outputs either the oscillation output CLKI or the frequency-divided output CLK2 to the clock generator ( 4) Output K. A clock generator (4) generates a clock signal CP for controlling the operation of the micro combinator based on the signal CLK output from the switching circuit (3), and outputs it to each internal circuit. That is, the microcomputer performs operations according to instructions based on the clock signal CP, and the operating speed is determined by the signal CL output from the switching circuit (3).
determined by the frequency of K.

The operation control circuit (5) receives a signal HOLD applied to a hold terminal (6) K, a HALT signal outputted from an instruction depuder (7), a boat signal PA applied from an input circuit (8), and a Based on the second signal SEC applied from the circulation circuit (9), a control signal C3TOP or CHG is output to control the start or stop of oscillation of the oscillation circuit (1) and control the switching of the switching circuit (3). do. This operation control circuit (5) is shown in detail in FIG.
It has a first 7-lip-flop that is reset by EC and a vote signal PA, and a second flip-flop that detects that it is in a hold state by a halt signal Wσn, and the output of the first 7-lip-flop is controlled. The signal C3TOP becomes the signal C3TOP, and the output of the second flip-flop becomes the control signal CHG. On the other hand, instruction = 1
The decoder (decoder) decodes the instructions IR sent out sequentially from the address of the ROM (not shown) specified by the program counter (not shown), and controls each circuit to perform operations based on the instructions IR. In particular, when a halt command to stop the operation is executed, a halt signal HALT is output. Therefore, when a halt command is executed and a halt signal HALTThZ is output, a control signal C3TOP is output. Since the oscillation of the oscillation circuit (1) is stopped, the clock signal CP is no longer output from the clock generator (4), and the operation of the microcomputer is stopped.In other words, it enters a halt state.Also, it returns from the halt state. This is when the seconds signal SEC or Portoy No. 100 FA is output.Seconds signal SE
C is the output of a frequency divider circuit (9) that divides the oscillation output 8T of the timekeeping oscillation circuit Q (1), which is always operating regardless of whether the microcomputer stops operating, and is, for example, an I Hz signal. .

That is, the operation is restarted periodically every second by the second signal SEC. On the other hand, the boat signal FA is a signal output from the input circuit (8) of the input port aυ when a signal of a predetermined level is applied to the predetermined input port aυ. That is, it is possible to escape from the halt state by applying a signal of a predetermined level to the input capo H1). When the halt state is released, the program will
The cause of the release is determined and the program corresponding to the cause is executed, but since the last trap of each program is always provided with a halt command, after each program ends, the operation is stopped again by the halt signal HALT and the halt state is returned. become.

On the other hand, the normal power supply voltage is applied to the hold terminal (6).
The hold state is detected when the hold signal HOLD becomes 'L' at the time of power failure.

When the hold signal HOLD is "H" during energization, the control signal CHG K causes the switching circuit (3) to change the oscillation output CL.
KI is selected. During a power outage, when the hold signal HOLD is in the "L" state, that is, in the hold state, when the operation is started by the second signal SEC, the control signal CHG
Since the switching circuit (3) selects the frequency-divided output CLK2, at this time, the operating speed of the microcombinator becomes slower by the frequency divided by the frequency-dividing circuit (2).

FIG. 2 is a concrete logic circuit diagram of the operation control circuit (5), oscillation circuit (1), frequency dividing circuit (2), and switching circuit (3) shown in FIG.

In FIG. 2, the operation control circuit (5) includes a first flip-flop (13i) consisting of a NAND game (Q2);
The first seven flip-flops a3 are set by a halt signal HAL via an inverter αe.
T is applied, and a second signal 5ECiJ is applied to the reset input bean.
' - is applied through the NOR gate α°C, and furthermore, the boat signal PA is applied through the AND gate (1 barrel and the NOR gate an), and the first flip-flop ([
The Q output of 31 is outputted as a control signal C3TOP via the inverter (1!J').The control signal C3TOP is applied to the sector input 100 of the second flip-flop u5I via the NAND gate 4, and Qυ
A hold signal HOLD is applied through the NAND gate (A) and the NAND gate (A), and the output of the NAND gate to which the hold signal HOLD and the reset signal RESET are applied is applied to the reset input π via the inverter (C) and the NOR gate. (e), and furthermore, the output of AND gate (5) is N.

Applied via R gate (4). Further, the output of the second flip-flop Q5F+Q is outputted as a control signal CHG via an inverter (c), and the control signal C)-I
G is applied to the AND gate 7). This AND gate (5) has a hold signal HOLD connected to the inverter (2I).
(2), and the output of AND gate Q'0 is applied to NOR gate η (26).

In addition, the oscillation circuit (1) is a Schmitt inverter (c)
, a NOR gate (to), and an inverter C31), and an oscillation element, such as a crystal resonator, a ceramic resonator, or an R, C circuit is connected to the output of the inverter inverter (31). Terminals 08C4 and 08C2 are connected. Furthermore, a control signal C3TOP is input to one input of the NOR gate (to) to control oscillation. The frequency divider circuit (2) is a 1/4 frequency divider circuit to which T-FF04 (to) is connected, and the output Q of T-FF (c) is passed through a NOR gate controlled by the control signal C3TOP. AND game) is applied to C3ω.

The AND gates (G) and OR gate (GV) form a switching circuit (3), and the output of the NOR gate (2) of the oscillation circuit (1) is controlled by the output of the D-FF (3119) and the output of the inverter. That is, the oscillation output CLKI and the frequency dividing circuit (2
) and the divided output CLK2.

The D-FF unit stores and switches the control signal CHG using the oscillation output CLKI, and also controls the T-FF (
321 is maintained in the set state by the control signal C3TOP or the output of the inverter via the NOR gate (40) and the inverter 0υ.

In the circuit shown in FIG. 2, when the power is turned on, the hold signal HOLD becomes H'', and the reset signal R
Since ESET remains "H" for a predetermined period, the inverter (2
An "H" pulse is output from the output of 51, the first 7 flip-flop a3 and the second flip-flop aω are both in a reset state, and each Q output becomes 1H1'. That is, since the control signal C3T0P is "L", the oscillation circuit (
The oscillation of 1) continues. Also, the control signal CHG is also 'L'
Therefore, the output Q of the D-FF (to) becomes "L", and therefore, the AND gate (to) becomes conductive, and the oscillation output CLKI is selected and output.At this time, the output of the inverter (3!J) becomes " Since it is "H", T-FF (3a (33) remains set, and the AND gate (c) has L II
is applied. In this state, the microcomputer operates at high speed because the clock pulse CP is generated by the oscillation output CLKI.

In the above state, when the halt command is executed and the halt signal HALT becomes a HII pulse, the first 7 lip-flop Q31 is set and the control signal C3TOP becomes H". Therefore, the oscillation of the oscillation circuit (1) stopped,
The microcomputer stops working. At this time, since the hold signal HOLD is H'', the control signal C3T
Since OP="H" is cut off by the NANDAND gate, the second flip-flop (l!19 remains in the reset state. Then, when the second signal SEC or boat signal PA becomes a pulse of I("), First 7 lip-flop Q block [Since it is reset again, the oscillation circuit (1
) oscillation resumes.

On the other hand, when the hold signal HOLD becomes "L" due to a power outage, the output "'H" of the inverter (C) is applied to the NANDAND gate, so the second flip-flop Q5) is set by the control signal C3TOP. becomes possible. That is, when the first 7-lip-flop 031 is in the reset state and the control signal C3TOP is "L", the second 7-lip-flop Q5 is not set. On the other hand, when the halt command is executed and the first 7 lip-flop 03 is set, the control signal C3TOP becomes "H".
The second 7 lip-flop (15) is set. However, in this state, the oscillation circuit (1) is stopped, so
The control signal CHG="H" is not input to the D-FF, so the switching circuit (3) has not yet selected the frequency-divided output CLK2. Therefore, the second signal SEC becomes a 'H' pulse.

Then, the first flip-flop a3 is reset, but at this time, the control signal C3TOP becomes H'', so that
The control signal CHG becomes 'H'. Therefore, the oscillation circuit (1
) resumes oscillation, D-FF (to) receives control signal C
HG="'H" is input, and its output is set to 'H'. Therefore, the AND gate (to) cuts off the oscillation output CLKI, and the AND gate 051 selects the frequency-divided output CLK2.

At the same time, since the set of T-FF (321) is released, the divided output CLK2 whose frequency is divided by 1/4 is applied to the clock generator (4), and the microcomputer operates at a low speed.

In addition, in the hold state, the AND game Hat is connected to the port signal P.
Since A is cut off, operation cannot be restarted even if a signal of a predetermined level is applied to the input port.

That is, only the seconds signal SEC is allowed to resume operation;
By performing only the necessary operation of time counting, power consumption in the hold state is minimized.

In addition, in the hold state, when the first flip-flop (I9) and the second flip-flop 70 knob a9 are in the set state, that is, when the operation is stopped in the hold state, the hold signal is When HOLD becomes 'H', the output of the AND gate (27) to which the control signal CHG='H' is applied becomes 'H', so the first flip-flop Q3) and the second flip-flop a$ The microcomputer is reset, the operation of the oscillation circuit (1) is restarted, and the switching circuit (3) selects the oscillation output CLK1.Therefore, the microcomputer returns to the normal operating state of high-speed operation.

(F) Effects of the Invention As described above, according to the present invention, when performing the minimum necessary operation in the hold state, the speed of the operation is slower than in the normal state (by doing so, the speed of the operation is slower than in the normal state). This has the advantage of reducing power consumption, making it possible to perform essential operations such as timekeeping, and making full use of the capabilities of the microcomputer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a specific logic circuit diagram of some blocks shown in FIG. Explanation of main drawing numbers (1)...Oscillation circuit, (2)...Branch circuit, (
3)...Switching circuit, (4)...Clock generator, (5)...Operation control circuit, (6)...Hold terminal, (7)...Instruction decoder, (8)...・Input circuit, (9)...Pa frequency dividing circuit,
QOI: oscillation circuit for timing, (11): input port. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Mamoru Sano Figure 1

Claims (1)

[Scope of Claims] 1. A microcomputer that has a halt function that stops operation when a halt command is executed, and enters a hold state by executing the halt command as long as a signal at a predetermined level is applied to a hold terminal. an oscillation circuit that generates a frequency signal for creating a system clock signal; and a first oscillation circuit that is set by execution of the halt instruction and reset by an associated signal, and whose output controls the oscillation of the oscillation circuit. a flip-flop, a frequency divider circuit that divides the oscillation output of the oscillation circuit into a predetermined frequency, and a clock generator that switches between the frequency division output of the frequency divider circuit and the oscillation output to create a system clock signal. and a second 7-lip-flop that detects that a signal of a predetermined level is applied to the hold terminal and controls the switching circuit, and the first 7-lip-flop is set during a hold function. 2. A microcomputer characterized in that when the switching circuit selects a branch output when the operation stoppage is canceled by being reset by a predetermined signal, the operating speed of the system is reduced. 2. The microcomputer according to claim 1, wherein the signal for resetting the first flip-flop is at least a timekeeping signal.