JPH02242410A - Frequency division circuit - Google Patents

Abstract

PURPOSE:To prevent the frequency of a system clock to be supplied to each block from being changed even when the frequency of the system clock is switched by supplying the system clock by changing the number of frequency division of the system clock reacting to the switching of the frequency of the system clock. CONSTITUTION:A switch 163 selects and passes the frequency division output 1h of a frequency divider 162 when a switching select signal 1d is set at a low level, and the switch 163 selects and passes the frequency division output 1g of a frequency divider 161 when it is set at a high level. Here, the number of frequency division of the frequency divider 162 is set equal to the frequency division ratio of a pair of frequency division output 1b and 1c of a pre-scaler 13. Thereby, the output 1k of a pre-scaler 16 always kept constant regardless of the change of the frequency of the system clock 1f by a switch 14 is set as the clock sources of an interface and an A/D converter, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a frequency divider circuit that supplies clocks to internal blocks of an integrated circuit such as a microcomputer.

(b) Conventional technology Microcomputers used to control AV equipment or air conditioning equipment have interfaces, AD converters,
This is because it has built-in functions such as timers that are comparable to conventional peripheral LSIs, and in order to operate these functions, each functional block requires a clock with a different frequency, and a clock with a frequency lower than the normal system clock. ,
The system clock is divided and supplied.

An example of a conventional microcomputer clock supply circuit (hereinafter referred to as a frequency divider circuit) will be described with reference to FIG.

The oscillation output (2a) of the original oscillation circuit (22) excited by a crystal oscillator (21) with a resonance frequency of several M cycles is generated by the system clock generator (25) as a system clock (2f) with a waveform suitable for system operation. At the same time, the prescaler (26) performs a predetermined frequency division and becomes a clock source (2k) for an interface, an AD converter, etc. Also, the prescaler (
The predetermined frequency division stage output (2J) of 26) is supplied to the timer (27) as a count source for an 8-bit or 16-bit counter constituting the timer (27).

In a microcomputer configured in this way, the output (2k) of the prescaler (26) or the timer (27
) Since the second signal can be obtained more easily than the overflow signal (2m), a clock function is often added. However, for reasons to be described later, it is difficult to back up this microcomputer in the event of an accident such as a power outage, and it is inevitable that the clock function will be disrupted in the event of an accident.

That is, the power consumption of a microcomputer tends to be approximately proportional to the frequency of the system clock, and it is not preferable from the viewpoint of power consumption to operate it with the system clock of the normal frequency even during standby. Therefore,
During standby, a method is adopted in which the system clock is set to several tenths of the normal clock. This allows for simple backup using a capacitor in the event of a momentary power outage, such as when a device's power cord is accidentally unplugged.

Next, an example of a frequency dividing circuit proposed for this purpose will be explained with reference to FIG.

For example, the frequency of the output (3a) of the source oscillation circuit (32) is 1
0M cycle, and the prescaler (33) converts it into 2
Frequency division output of 5M cycle frequency divided by 1 (3
b) and a frequency division output (3c) of the frequency of 100 cycles which is divided into 1/100. Note that the numerical values used here are for convenience.

Therefore, for example, when the power supply is normal and the system should be operated with the normal 5M cycle system clock, a flag (not shown) is reset, the switching select signal (3d) becomes low level, and the switch (34)
selectively passes the divided output (3b) of 5M cycles and sets the output as (3e>).The output (3b) of this 5M cycle is
e) System clock generator (35) that inputs
converts this into a system clock (3f) with a waveform suitable for system operation and supplies it to the system, and also uses it as a clock source (3K) for interfaces, AD converters, etc. via a prescaler (36). Further, a predetermined frequency division stage output (3j) of the prescaler (36) is supplied as a count source of an 8-bit or 16-bit counter constituting a timer (37).

Therefore, when a flag (not shown) is set due to a momentary power outage, etc., and the switching sector signal becomes high level, the switching device (34) divides the source oscillation frequency by 1/100, and outputs a cycle of 100 (3c). is selectively passed through and its output (3e) is input to the system clock generator (35).As a result, the system clock becomes several tenths of the normal time, and the power consumed by the microcomputer is reduced to several tenths. 1, resulting in a sufficiently low load for the backup capacitor.

However, in the above-mentioned microcomputer, the frequency of the output (3k) of the prescaler (35) during standby is several tenths of the normal frequency, and it is not possible to configure a hardware clock using this as a second signal. Therefore, the overflow signal (3m) of the timer (37) is used. In this case, the software that determines the frequency switching of the system clock and the timer (37) are used.
) is required to use software to write an initial value using an accumulator every time the frequency of the system clock is changed, which has the drawback of increasing the burden on the software.

(c) Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned points. To provide a frequency dividing circuit in which the frequency of a clock supplied to each block does not change even when the frequency of the clock is switched.

(2) Means for Solving the Problems This invention provides an integrated circuit that divides a system clock to obtain a clock source for each block in the system.
The device includes means for switching the frequency of the system clock, and means for changing the frequency division number of the system clock in response to the frequency switching to keep the frequency of the clock source supplied to each block constant.

(e) Effect The above configuration makes backup in the event of an accident such as a momentary power outage relatively simple, and other functions such as the clock function, which operates with a clock obtained by dividing the system clock, are not impaired. It works like this.

(f) Example An embodiment of the present invention will be described with reference to FIG.

Today, the most common microcomputers are several M~IO
It operates with a system clock of M cycles. In order to obtain this system clock, 10M cycles, for example, is selected as the resonance frequency of the crystal oscillator (11) that excites the source oscillation circuit (12), and the prescaler (13) that inputs this oscillation circuit output (1a) is A 5M cycle frequency division output (1b) which divides the 10M cycle source oscillation frequency by 1/2 and a 100K cycle frequency division output (IC) which divides the source oscillation frequency by 1/100 are output. Note that the numerical values used here are convenient values, and in reality, for example, a clock of 3.579545 M cycles suitable for a clock circuit, or a clock of 1.7897725 M cycles by dividing it by half, is finally obtained. Please note that it is necessary to use pre-designed numerical values necessary for this purpose. For example, if the power supply is normal and the microcomputer is
When the system clock of the cycle should be used to operate, a flag not shown is reset, the switching select signal (1d) becomes low level, and the switching device (14)
selectively passes the divided output (1b) of 5M cycles.

The system normally operates based on the 5M cycle system clock (1f) output from the system clock generator (15) which receives this switching output (1e). Furthermore, when the switching select signal (1d) is at a low level, the switching device (163) constituting the prescaler (16) outputs the divided output (1h) of the frequency divider (162) also constituting the prescaler (16). is selectively passed through, and its output (11) is also sent to the prescaler (16).
) to a frequency divider (164). According to this, the frequency division output (1k) which divides the 5M cycle system clock (1f) into a relatively large number is the interface, A
It is used as a clock source for D-controllers, etc. moreover,
The predetermined frequency division stage output (1j> of the frequency divider (164) that constitutes the prescaler (16) is the 8 that constitutes the timer (17).
It is supplied as a count source for a bit or 16-bit counter.

Subsequently, when it becomes necessary to reduce the power consumption of the microcomputer due to an accident such as a momentary power outage, a flag (not shown) is set by the program, and the switching select signal (1d) becomes high level. This results in
The switch (14) outputs the frequency divided by 100 cycles (I
A system clock (1f) of 100 cycles is generated by the system clock generator (15) which selectively passes C) and inputs this. This reduction in the system clock reduces the power consumed by the microcomputer and enables simple backup using a capacitor.

Further, when the switching select signal (1d) becomes low level, the switching device (1d) constituting the prescaler (16)
63) selectively passes the divided output (Ig) of the frequency divider (161) that also constitutes the prescaler (16>).Here, the frequency divider (162) that constitutes the prescaler (16)
By making the division ratio of the pair of division outputs of the prescaler (13) equal to the division ratio of the pair of division outputs of the prescaler (13), the switch (14)
The frequency of the output (11) of the switch (163) when the frequency division output (C) of the cycle is selectively passed to 00, and the frequency of the output (11) of the switch (14) when the frequency division output (IC) of the 5M cycle is selectively passed. The output (1) of the switch (163)
1) can be made equal to the frequency.

In this way, the output of the prescaler (16), which is always constant regardless of changes in the system clock frequency, is used as a clock source for interfaces, AD converters, etc., and the frequency divider (16) constituting the prescaler (16)
164) predetermined frequency division stage output (1j) is the timer (17)
It is supplied as a count source for the 8-bit or 16-bit counter that makes up the 8-bit or 16-bit counter. As a result, even if a hardware clock that uses the output (1k) of the prescaler (16) is constructed, the function will not be impaired due to an accident such as a momentary power outage. Also, the timer (1
If the clock is configured using the overflow signal (1m) in 7), it is sufficient to configure the timer (17) or write an initial value to the load register regardless of the state of the system clock.

Above, this invention has been explained mainly using clock supply to a timer as an example, but it can also be used in addition to clock supply to a timer, for example.
It can also be applied to driving display elements, refreshing RAM, etc. In other words, even if the system clock is changed due to software requests, etc.
It is possible to modify these operations so that they can be performed without any problems.

(G) Effects of the Invention As described above, the present invention has the following advantages: (1) Since the frequency of the system clock can be significantly lowered, a simple backup means can be adopted.

(2) Since the system clock is not stopped, it is easy to return from the sleep state.

(3) It is possible to change the system clock significantly regardless of the capacity of the timer counter.

4> When changing the frequency of the system clock, there is no need to write new data to the reload register, reducing the burden on software.

It is possible to provide a frequency dividing circuit that achieves this remarkable effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams of a conventional example. (11), (21), (31)...Crystal oscillator,
(12), (22), (32>... oscillation circuit,
(13), (16), (26), (33),
(36)...Bnoscalera, (14), (163
), (34)...switcher, (15), (25
), (35)...system clock generator,
<17), (27), (37)... timer,
(1d)...Switching select signal.

Claims (2)

[Claims] (1) In an integrated circuit that divides the system clock to obtain a clock source for each block in the system, a means for switching the frequency of the system clock, and a means for changing the frequency division number of the system clock in response to this frequency switching,
and means for keeping constant the frequency of a clock source supplied to each block. (2) The frequency dividing circuit according to claim 1, wherein the frequency of the system clock is switched in response to execution of a standby command or detection of a power outage.