JPH0580871A - Electronic computer system - Google Patents

Abstract

PURPOSE:To keep the normal processing speed of an electronic computer system by switching the clock to be applied to a CPU to a clock of a lower frequency in order to reduce the power consumption in a keyboard input waiting state and at the same time detecting the using state of the system by means of hardware. CONSTITUTION:A key code storage circuit 2 stores temporarily the key codes inputted through a keyboard 3. A flag register 4 outputs a status signal 10 based on the presence or absence of a key code in the circuit 2. A counter circuit 5 starts its counting operation when the signal 10 shows the absence of an unprocessed key code. Then the circuit 5 outputs a clock selection control signal 11 to a clock frequency selector 6 after a fixed period. The selector 6 switches the frequency of the clock which is supplied to a CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic computer system having a clock frequency selection circuit for the purpose of reducing the power consumption of the system, and particularly to a high clock for the central processing unit while waiting for an input from the keyboard. The present invention relates to an electronic computer system that switches from a frequency clock to a low frequency clock.

[0002]

2. Description of the Related Art FIGS. 3 and 4 are block diagrams showing configurations of first and second electronic computer systems, respectively. The first conventional computer system as shown in FIG. 3 does not have a clock frequency selection circuit described later, and the frequency of the clock supplied from the oscillation circuit 7a to the central processing unit (hereinafter referred to as CPU) 1 is always constant. Met. Therefore, there is a problem that the CPU always operates in synchronization with the high frequency clock supplied from the oscillation circuit 7a and consumes a large amount of power even when the system is not used.
Further, in a system using a battery, there is a problem that the battery is consumed so much that the operable time of the system is shortened.

Therefore, in order to reduce such useless power, in the second conventional electronic computer system as shown in FIG. 4, the period during which the system is not used is detected by the software, and the clock frequency control means. An I / O command (input / output command) is sent to 12.
The clock frequency selection circuit 6 internally divides the high frequency clock supplied from the oscillation circuit 7a into a low frequency clock. The clock frequency control means 12 uses the above-mentioned I / O.
In response to the command, a clock selection control signal for selecting one of the high frequency clock supplied from the oscillation circuit 7a and the internally divided low frequency clock is output to the clock frequency selection circuit 6. .. Thus, when the system is not used, the power consumption can be reduced by lowering the clock frequency.

In the second conventional electronic computer system, the low frequency clock is created inside the clock frequency selection circuit 6, but the low frequency clock is generated by the oscillation circuit 7a provided outside the clock frequency selection circuit 6. Needless to say, it may be generated from another oscillation circuit.

[0005]

However, in the electronic computer system having the above-mentioned conventional clock frequency selection circuit, it is necessary to always detect the timing of switching the clock to the low frequency by software. Therefore, there is a problem that the processing speed of the system in the normal processing state decreases.

Therefore, an object of the present invention is to reduce the power consumption of the system by switching the frequency of the clock to the CPU from the high frequency to the low frequency while waiting for the keyboard input, while the system is being used. It is an object of the present invention to provide an electronic computer system in which the processing speed does not decrease even in the normal processing state of the system and the normal processing speed can be maintained by performing the above detection by hardware.

[0007]

According to a first aspect of the present invention, there is provided an electronic computer system including a central processing unit, an oscillator circuit for generating a high frequency clock for operating the central processing unit, and the high frequency clock. Is internally divided into a low frequency clock, and in response to a clock selection control signal, either the high frequency clock or the low frequency clock is selected, and the selected clock is supplied to the central processing unit. In a computer system having a selection circuit, there is an unprocessed key code in the key code storage circuit for temporarily storing a key code input from a keyboard and to be read into the central processing unit. Flag register that outputs a status signal indicating whether or not to perform Counting is started from a time point when the absence of the card is indicated, and the low frequency clock is selected as the clock selection control signal to the clock frequency selection circuit when the count value indicates that a certain time has elapsed. And a counter circuit that outputs a signal instructing to do so.

In the electronic computer system according to the first aspect, the status signal indicates that the unprocessed key code exists before the lapse of the fixed time after the counter circuit starts the counting operation. Sometimes, the count value is immediately reset. Further, when the status signal indicates the presence of the unprocessed key code in a state where a signal instructing to select the low frequency clock is output as the clock selection control signal, the counter The circuit sends a signal for instructing the clock frequency selection circuit to select the high frequency clock as the clock selection control signal.

An electronic computer system according to a second aspect of the present invention includes a central processing unit, a high frequency oscillating circuit for generating a high frequency clock for operating the central processing unit, and a central processing unit for operating the central processing unit. A low-frequency oscillator circuit for generating a low-frequency clock having a frequency lower than that of the high-frequency clock, and in response to a clock selection control signal, one of the high-frequency clock and the low-frequency clock is selected and selected. In a computer system having a clock frequency selection circuit for supplying a clock to the central processing unit, input from a keyboard,
A key code storage circuit for temporarily storing a key code to be read into the central processing unit; a flag register for outputting a status signal indicating whether or not an unprocessed key code exists in the key code storage circuit; The clock selection control signal is sent to the clock frequency selection circuit when the status signal indicates the absence of an unprocessed key code, and when the count value indicates that a certain time has elapsed. And a counter circuit that outputs a signal instructing to select the low-frequency clock.

In the electronic computer system according to the second aspect, the status signal indicates that the unprocessed key code exists before the lapse of the fixed time after the counter circuit starts the counting operation. Sometimes, the count value is immediately reset. Further, when the status signal indicates the presence of the unprocessed key code in a state where a signal instructing to select the low frequency clock is output as the clock selection control signal, the counter The circuit sends a signal for instructing the clock frequency selection circuit to select the high frequency clock as the clock selection control signal.

[0011]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of an electronic computer system according to the present invention. In the figure,
The CPU 1 is connected to the key code storage circuit 2 via the CPU data bus 9. The key code storage circuit 2 is further connected to the keyboard 3 via the peripheral data bus 8. A plurality of key codes input from the keyboard 3 are stored in the key code storage circuit 2 via the peripheral data bus 8. The CPU 1 arbitrarily sends an I / O command to the key code storage circuit 2 to read the stored key code. The key code storage circuit 2 is further connected to the flag register 4. When a new key code is stored in the key code storage circuit 2, the flag register 4 shows an ON state, and when the CPU 1 reads all the key codes stored in the key code storage circuit 2, the flag register 4 turns OFF. Indicates the state.

That is, the flag register 4 is a counter circuit 5
And supplies a status signal 10 indicating the presence or absence of unprocessed data in the key code storage circuit 2 as an ON / OFF state to the counter circuit 5. The counter circuit 5 starts counting when the status signal 10 is turned off. The counter circuit 5 is connected to the clock frequency selection circuit 6 and supplies a clock selection control signal 11 to the clock frequency selection circuit 6 as described later. When a certain period of time elapses after the counter circuit 5 starts counting while the status signal remains in the OFF state, the counter circuit 5 outputs the clock selection control signal 11 to the clock frequency selection circuit 6 in the ON state. To do. Further, when the status signal 10 indicates the ON state before a certain period of time has elapsed from the start of counting, the counter circuit 5 is immediately reset and the counting is stopped.

The clock frequency selection circuit 6 includes an oscillation circuit 7
It is connected to a. The operations of the clock frequency selection circuit 6 and the oscillation circuit 7a are the same as those of the conventional one, and thus the description thereof will be omitted.

When the clock selection control signal 11 from the counter circuit 5 indicates the ON state, the clock frequency selection circuit 6
Switches the frequency of the clock supplied to the CPU 1 from a high frequency to a low frequency. If the status signal 10 is turned on while the clock frequency selection circuit 6 is already outputting the low frequency clock to the CPU 1, the clock selection control signal 11 is turned off. When the clock selection control signal is turned off, the clock frequency selection circuit 6 switches the clock frequency from the low frequency to the high frequency. That is, the clock selection control signal 11 is turned on only when a certain period of time has passed without an unprocessed key code existing in the key code storage circuit 2, and when a new key code is sent to the key code storage circuit 2, the clock selection control signal is sent. 11 is turned off.
In this way, the clock selection control signal 11 is turned on or off.
By setting to the F state, the clock frequency selection circuit 6 is notified of the input state of the key code from the keyboard 3. Therefore, in the clock frequency selection circuit 6, the clock generated from the oscillation circuit 7a can be appropriately switched between the high frequency and the low frequency based on the input state of the key code and output.

FIG. 2 is a block diagram showing the configuration of another embodiment of the electronic computer system according to the present invention. 2, the same components as those in FIG. 1 are designated by the same reference numerals,
The operation is similar to that described with reference to FIG.

In the figure, the clock frequency selection circuit 6 is connected to two separate oscillator circuits 7a and 7b. The oscillator circuit 7a generates a high-frequency clock used during normal operation of the CPU 1, and the oscillator circuit 7b generates a low-frequency clock used while waiting for keyboard input. The clock frequency selection circuit 6 includes the counter circuit 5
In response to the clock selection control signal 11 supplied from
One of the two types of clocks generated from the oscillator circuits 7a and 7b is selected and sent to the CPU 1.

[0017]

As described above, according to the present invention,
While waiting for keyboard input, the frequency of the clock to the CPU is switched from high frequency to low frequency to realize low power consumption of the system, while detecting the input state of a new key code by hardware. Even in the normal processing state of the system, the processing speed does not decrease, and the normal processing speed can be maintained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an electronic computer system according to the present invention.

FIG. 2 is a block diagram showing the configuration of another embodiment of the electronic computer system according to the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional electronic computer system.

FIG. 4 is a block diagram showing another configuration of a conventional electronic computer system.

[Explanation of symbols]

 1 CPU 2 Key Code Storage Circuit 3 Keyboard 4 Flag Register 5 Counter Circuit 6 Clock Frequency Selection Circuit 7a, 7b Oscillation Circuit 8 Peripheral Data Bus 9 CPU Data Bus 10 Status Signal 11 Clock Selection Control Signal 12 Clock Frequency Control Means

Claims (6)

[Claims] 1. A central processing unit, an oscillating circuit for generating a high frequency clock for operating the central processing unit, the high frequency clock internally divided into a low frequency clock, and responsive to a clock selection control signal. And a clock frequency selection circuit for selecting one of the high frequency clock and the low frequency clock and supplying the selected clock to the central processing unit, wherein: A key code storage circuit for temporarily storing a key code to be read into a central processing unit; a flag register for outputting a status signal indicating whether or not an unprocessed key code exists in the key code storage circuit; Counting starts when the status signal indicates the absence of an unprocessed key code, A counter circuit that outputs a signal instructing the clock frequency selection circuit to select the low frequency clock as the clock selection control signal when the count value indicates that a predetermined time has elapsed. And computer system. 2. The count value is reset immediately when the status signal indicates the presence of the unprocessed key code before the lapse of the fixed time after the counter circuit starts the counting operation. The electronic computer system according to claim 1, wherein 3. When the status signal indicates the presence of the unprocessed key code in a state where a signal instructing to select the low frequency clock is output as the clock selection control signal. 2. The counter circuit sends a signal for instructing the clock frequency selection circuit to select the high frequency clock as the clock selection control signal.
Alternatively, the electronic computer system described in 2. 4. A central processing unit, a high frequency oscillating circuit for generating a high frequency clock for operating the central processing unit, and a low frequency and a low frequency for operating the central processing unit. A low-frequency oscillator circuit that generates a frequency clock, and a clock frequency that selects either the high-frequency clock or the low-frequency clock in response to a clock selection control signal and supplies the selected clock to the central processing unit. An electronic computer system having a selection circuit, a key code storage circuit for temporarily storing a key code input from a keyboard and to be read into the central processing unit, and an unprocessed key code exists in the key code storage circuit. Flag register that outputs a status signal indicating whether or not to Counting is started from the time when the absence of the processing key code is started, and when the count value indicates that a certain time has elapsed, the low frequency clock is supplied to the clock frequency selection circuit as the clock selection control signal. And a counter circuit that outputs a signal instructing to select the electronic computer system. 5. The count value is reset immediately when the status signal indicates the presence of the unprocessed key code before the lapse of the fixed time after the counter circuit starts counting operation. The computer system according to claim 4, wherein 6. When the status signal indicates the presence of the unprocessed key code in a state where a signal instructing to select the low frequency clock is output as the clock selection control signal. 5. The counter circuit sends a signal for instructing the clock frequency selection circuit to select the high frequency clock as the clock selection control signal.
Alternatively, the electronic computer system according to item 5.