JP3000965B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus such as a microcomputer, and more particularly, to a data processing apparatus which realizes a standby function which can stop a CPU function and reduce power consumption.

[0002]

2. Description of the Related Art There are two methods for a standby mode of a conventional data processing device such as a microcomputer having a standby function.

A first method is to stop the clock for the CPU in the standby mode by a halt instruction. This is called "Halt mode".

[0004] A second method is that in a standby mode,
This is a method of stopping all clocks and stopping the operation of the oscillation circuit. This is called "stop mode".

The user selects and uses the above-mentioned two standby modes, that is, the halt mode and the stop mode by an application.

First, during standby, which is the first method, C
The outline of the halt mode in which the clock for the PU is stopped will be described below with reference to the configuration diagram of FIG. 6 and a time chart of FIG. 7 illustrating the operation of the configuration shown in FIG.

Referring to FIG. 6, a microcomputer having the halt mode includes an oscillation circuit 601 and a frequency dividing circuit 602 for dividing an output signal 610 of the oscillation circuit 601.
, CPU 603, timer counter 604, RAM
(Random access memory) 605, ROM (read-on memory) 606, input / output circuit 607, standby control circuit 608, standby release terminal 60
9 are included.

Referring to FIGS. 6 and 7, the CPU 603
When the halt mode is instructed by the instruction executed in step (1), the standby flag of the standby control circuit 608 is set (in the figure, it is set to the high level). Based on this, the standby control circuit 608 outputs the halt signal 611 to the frequency dividing circuit 602.

The frequency dividing circuit 602 stops the clock signal 612 supplied to the CPU 603, thereby
Only 603 stops processing. At this time, the CPU 603
(For example, state values of a program counter, a processor status word, a register, etc.) are held.

Next, cancellation of the halt mode will be described.

When the standby release signal 615 is input from the standby release terminal 609 to the standby control circuit 608, the standby flag in the standby control circuit 608 is reset as shown in FIG.
Accordingly, the standby control circuit 608
The halt signal 611 to the frequency dividing circuit 602 is set to an inactive state (Low level in FIG. 7), and the frequency dividing circuit 60
2 supplies the clock signal 612 to the CPU 603 again, and the CPU 603 resumes its operation. At this time, the CPU 60
3 restarts the operation from the state held before the halt state.

Next, a description will be given of a second method, a stop mode in which all clocks are stopped at the time of standby and the operation of the oscillation circuit is stopped. As a prior art relating to the second method, for example, Japanese Unexamined Patent Publication No. 58-20
A microcomputer described in Japanese Patent No. 5226 is known.

This conventional technique will be briefly described. FIG. 9 is a diagram showing a configuration of a microcomputer having a conventional standby mode. Referring to FIG. 9, this microcomputer includes an oscillation circuit 901, a frequency division circuit 902 for dividing the output signal 910 of the oscillation circuit 901,
CPU 903, time counter 904, RAM 90
5, a ROM 906, an input / output circuit 907, a standby control circuit 908, and a standby release terminal 90.
9 is provided.

FIG. 10 is a time chart for explaining the operation of the microcomputer shown in FIG. 9 and 10, when the standby mode is instructed by a command from the CPU 903, the CPU 903
The standby flag of the standby control circuit 908 is set by the halt command signal 915 output from the CPU. Based on this, the standby control circuit 9
08 outputs a halt signal 914 to each processing unit, and each processing unit shifts to the stop mode.

Thereafter, the standby control circuit 90
8 indicates to the frequency dividing circuit 902 a clock stop signal 91
3 is output to stop the frequency dividing function of the frequency dividing circuit 902, and an oscillation stop signal 917 is output to the oscillation circuit 901 to stop the oscillation.

The frequency dividing circuit 902 stops the clock signal 912 for each processing unit including the CPU 903.
The state of each processing unit including the CPU 903 is held.

Next, cancellation of the standby mode will be described.

When the standby release signal 916 is input from the standby release terminal 909 to the standby control circuit 908, the standby flag in the standby control circuit 908 is reset as shown in FIG.
Accordingly, the standby control circuit 908
The oscillation stop signal 917 for the oscillation circuit 901 is dropped (inactive). Thereby, the oscillation circuit 90
1 resumes oscillation, and the output signal 910 of the oscillation circuit 901 is supplied to the timer counter 904.

The timer counter 904 operates as a delay timer and generates a delay of a predetermined time.
This is because the oscillation circuit 9 stopped in the standby mode
This is because it is necessary to increase the time until the oscillation resumes in the oscillation stable state.

When the timer counter 904 times out and the carry signal 911 is input to the standby control circuit 908, the standby control circuit 90
Numeral 8 sets the clock stop signal 913 to the frequency dividing circuit 902 to an inactive state, and then releases the standby state. Clock signal 912 output from frequency dividing circuit 902
Starts the operation again. When the standby state is released, C
The operation of the PU 903 and each function is resumed from the state held before the standby state.

[0021]

However, the above-mentioned prior art has the following problems.

1. First, the microcomputer of the first method (method of stopping only the CPU clock) described with reference to FIGS. 7 and 8 has the following problems.

1-1. The power consumed by the CPU occupies a large proportion in the microcomputer. If the voltage used is constant, the power consumed is proportional to the current flowing through the circuit. In general, the current flowing in the CPU is
D, PERID is the current flowing in peripheral processing units other than CPU
D. The current (power supply current) IDD of the entire microcomputer is an added value of these, IDD = CPU
IDD + PERIDD.

Here, CPUIDD and PERIDD are respectively expressed by the following equations.

CPUIDD = [steady current flowing to CPU] + [current determined by operating frequency]

PERIDD = [steady current flowing in peripheral processing unit] + [current determined by operating frequency]

When only the CPU clock is stopped,
[Current determined by operating frequency] in CPUIDD
Disappears (becomes zero).

In the case where the circuit is constituted by transistors having a CMOS structure, the above-mentioned [steady current flowing to the CPU] and [steady current flowing to the peripheral processing unit] are several milliamps or less.

However, the [current determined by the operating frequency] of the peripheral processing unit is much higher than the current that constantly flows through the circuit of the peripheral processing unit because the operating frequency is increased with the speeding up of the processing. Therefore, it can be said that the dominant current consumption in the halt mode is [current determined by operating frequency].

If the operating frequency is not different from the normal one, the PERID is maintained even in the standby mode.
D does not decrease at all, and the current consumption cannot be significantly reduced.

Therefore, the method of stopping only the CPU cannot be directly applied to, for example, an application of a mobile phone that operates using a battery as a power supply.

1-2. In order to stop the CPU clock during standby and further reduce the power consumption, it is effective to lower the frequency of the oscillation clock supplied to the oscillation circuit from the outside.

This is because the [current determined by the operating frequency] in the PERIDD is greatly reduced.

In order to realize this, a method is employed in which an external circuit is added to reduce the frequency of the oscillation clock supplied from the outside during standby. However, providing an external additional circuit for controlling the oscillation clock frequency has a problem that the cost is increased, and in an application such as a mobile phone, there is no mounting area for providing the external additional circuit. is there.

1-3. Another method of reducing power consumption irrespective of the external additional circuit is to lower the fractional number of the clock signal output from the frequency divider circuit by the instruction of the CPU before shifting to the halt mode.

In this method, the same effect as the method described in the above item 1-2 can be obtained. Takes time to run.

This will be described with reference to the flowchart shown in FIG. 8. A frequency dividing instruction is executed before the halt instruction is executed, and the frequency dividing instruction is executed even after the standby state is released. Need to return to speed.

For example, in the application of a mobile phone, it is necessary to restart the processing at a high speed from the standby state to the return to the normal operation when the standby mode is released, so that the internal processing speed cannot be reduced. For this reason, there is a problem that even if effective for reducing the current consumption, it cannot be put to practical use.

2. Next, a problem of a method of stopping all the second clocks and stopping the operation of the oscillation circuit will be described.

2-1. For the purpose of reducing power consumption only, there is a great effect as compared with the method of stopping only the CPU clock. That is, when a circuit is formed by CMOS transistors, the current consumption is on the order of microamps. However, this conventional method has a serious problem that it is necessary to secure the oscillation stabilization time by the timer counter before the normal processing is resumed from the stop mode, and it is not possible to quickly return to the processing. In an application such as a mobile phone, the operation of the peripheral processing unit (for example, the operation of the timer counter) operating in the standby mode in the microcomputer is stopped. Cannot be executed, so that the waiting process cannot be performed,
There is a serious problem that.

2-2. In the above-mentioned Japanese Patent Application Laid-Open No. 58-205226, a standby mode in which the operation of the oscillation circuit is not stopped is also described. The problem of not being able to do so remains.

Accordingly, the present invention has been made in view of the above-mentioned problems, and has as its object to greatly reduce power consumption during standby and to quickly shift from standby to normal operation. Therefore, it is an object of the present invention to provide a data processing device suitable for application to a mobile phone or the like.

[0043]

In order to achieve the above object, a data processing apparatus according to the present invention includes a data processing apparatus including at least a central processing unit (hereinafter, referred to as a "CPU") and a peripheral processing unit for performing predetermined processing. In the processing apparatus, the CP
A standby control circuit for generating a standby mode for stopping supply of a clock signal to the CPU according to a program instruction executed by U, a standby release terminal for transmitting a standby release signal to the standby control circuit, and a transition to a standby mode Sometimes
Receiving the first control signal in advance, and thereafter receiving the first control signal.
The second control signal is a signal outputted from separately the CPU
Receiving, based on the first control signal and the second control signal,
Hazuki, standby mode - having a divider circuit for determining Luke switching the frequency division ratio of the clock signal to the peripheral processing device when de.

[0044]

Embodiments of the present invention will be described below. The microcomputer according to the embodiment of the present invention is a microcomputer including a CPU (103 in FIG. 1) and a peripheral processing device (104 in FIG. 1) for performing predetermined processing, and a program executed by the CPU. A clock signal to the CPU (11 in FIG.
4) a standby control circuit (108 in FIG. 1) for generating a standby mode for stopping supply, and a standby release terminal (109 in FIG. 1) for detecting a standby release signal and transmitting it to the standby control circuit; Frequency division control signal output from CPU (112 in FIG. 1)
And a frequency dividing circuit (102 in FIG. 1) for switching the frequency of the clock signal (113 in FIG. 1) to the peripheral processing device in the standby mode to a lower frequency side.

The operation of the embodiment of the present invention will be described. A frequency division control signal is activated in advance by a program instruction executed by the CPU. After that, when the CPU instructs the standby mode by the program instruction,
The halt signal is output from the standby control circuit, the clock supply to the CPU is stopped, and the mode shifts to the halt mode. At this time, the frequency of the clock signal supplied from the frequency dividing circuit to the peripheral processing unit is switched at a low speed and supplied.

As a result, the current consumed by the peripheral processing unit is, for example, a current determined by the operating frequency which is dominant in the peripheral processing unit when the frequency is normally divided by 2 and changed to 32. Is reduced to 1/16, and the current consumption can be greatly reduced.

In another embodiment of the present invention,
The microcomputer may be configured to receive the frequency division control signal from a peripheral processing device (107 in FIG. 1) other than the CPU.

[0048]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a block diagram showing a configuration of a microcomputer according to one embodiment of the present invention. FIG.
2 is a time chart illustrating an operation of the microcomputer according to the embodiment of the present invention illustrated in FIG. 1. FIG.
6 is a flowchart showing a state transition of the microcomputer according to the embodiment of the present invention shown in FIG.

Referring to FIG. 1, a microcomputer according to one embodiment of the present invention includes an oscillation circuit 101 and an oscillation circuit 1.
01, a frequency division control signal 112 from the CPU 103, and a halt signal 111 from the standby control circuit 108, and a frequency division circuit 102 and a CPU clock 114 output from the frequency division circuit 102. CPU 103, RAM 105, and ROM 10
6 and the peripheral clock 11 output from the frequency divider 102
3 and an input / output circuit 107, and a standby control circuit 108 for inputting a halt command signal 115 output from the CPU 103.
A standby release terminal 109 for supplying a standby release signal 116 to the standby control circuit 108,
It comprises.

In the present embodiment, the frequency dividing circuit 102
The configuration is such that the CPU clock 114 is supplied to the processing units related to the operation of the CPU 103, and the peripheral clock is supplied to the other processing units.

Next, the operation of the microcomputer according to one embodiment of the present invention in the halt mode will be described with reference to the time chart of FIG. 2 and the flowchart of FIG.

First, the CPU 103 executes a command for determining the frequency division at the time of the halt, and raises the frequency division control signal 112 output from the CPU 103.

Next, when the halt instruction is executed by the CPU 103, the standby mode is designated and the halt instruction signal 115 rises, the standby flag of the standby control circuit 108 is set.

When the standby flag is set, the standby control circuit 108 outputs a halt signal 111 to the frequency dividing circuit 102.

The frequency dividing circuit 102 includes a CPU 103 and an RA
M105, the CPU clock signal 114 supplied to the ROM 106 is stopped.

Next, since the frequency division control signal 112 has risen, the timer counter 104 and the input / output circuit 107
For example, the operation frequency of the peripheral clock 113 supplied to the processing unit not related to the CPU operation is switched to a low speed as shown in FIG. At this time, the CPU 103, the RAM 105, and the RO
The state of M106 is maintained.

Next, the release of the standby mode will be described.

When a standby release signal 116 is input from the standby release terminal 109 to the standby control circuit 108, the standby flag in the standby control circuit 108 is reset as shown in FIG.

In response to the reset of the standby flag, the standby control circuit 108 drops the halt signal 111 to the frequency dividing circuit 102, and the frequency dividing circuit 102
CPU 103 supplies CPU clock signal 114 again to U103, RAM 105, and ROM 106, and CPU 103 resumes its operation.

When the frequency division control signal 112 has not risen, the operation of switching the peripheral clock 113 to low frequency division is not performed even in the standby state.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a block diagram showing a configuration of a microcomputer according to the second embodiment of the present invention. FIG.
6 is a time chart showing the operation of the microcomputer according to the second embodiment of the present invention shown in FIG.

Referring to FIG. 4, the microcomputer of this embodiment includes an oscillation circuit 401, an output signal 410 of the oscillation circuit 401,
12, a frequency divider 402 that receives the halt signal 411 from the standby control circuit 108, and a CP that receives the CPU clock 414 from the frequency divider 402 as an input.
U403, RAM 405, and ROM 406; a timer counter 404 and an input / output circuit 407 to which a peripheral clock 413 output from the frequency dividing circuit 402 is input;
The standby control circuit 408 for inputting the halt command signal 415 output from the U 403 and a standby release terminal 409 for supplying a standby release signal 416 to the standby control circuit 408 are provided.

In the first embodiment, the frequency division control signal is output from the CPU to control the peripheral clock in the halt mode. In this embodiment, the frequency division control signal 412 is transmitted from the input / output circuit 407. The point of output is different from that of the first embodiment, and other configurations and operations are the same as those of the first embodiment. In the following, description of the same parts as in the first embodiment will be omitted, and only differences from the first embodiment will be described.

In the present embodiment, the configuration is such that the frequency division control signal 412 for controlling the frequency division ratio of the peripheral clock output from the frequency division circuit is supplied to the frequency division circuit via the input / output circuit 407, so that the halt is achieved. Since the peripheral clock in the mode can be externally controlled, it is possible to cope with a case where a high-speed process needs to be temporarily performed by a processing unit other than the CPU 403.

As described in the above prior art, in a data processing device such as a microcomputer used for a terminal such as a mobile phone, for example, high-speed processing required during a call, (communication processing with a base station) And low power consumption during standby when not in a call (this low power consumption increases the use time per charge when using a storage battery, and increases the value as a product), and A high-speed transition from the standby state to normal call processing (ie, quick incoming call processing when a call is received) is an essential condition.

For this reason, in the standby mode, in particular, C
The halt mode, in which peripheral processing units other than the PU can perform processing, is often used. However, there is a serious problem that power consumption does not significantly decrease in the halt mode. The cause of this problem is that the power consumed by the peripheral processing unit in the halt mode does not decrease as compared with the normal operation.

In the above-described embodiment of the present invention, the frequency dividing circuit is provided with a frequency dividing control signal for setting the operating frequency in the halt mode, and the halt instruction is executed to execute the halt mode.
When shifting to the mode, the operating frequency of the clock signal given to the peripheral processing unit is switched to a low frequency and supplied.
In the peripheral processing unit, the power consumed in proportion to the operating frequency is greatly reduced, and as a result, the power consumption of the entire apparatus is significantly reduced.

Further, in the embodiment of the present invention, when the mode shifts from the halt mode to the normal operation, the peripheral processing unit switches to the normal operation frequency, so that the state can be quickly shifted from the call waiting state to the call state.

Further, as described in the second embodiment, by outputting a frequency division control signal to be applied to the frequency division circuit from the input / output circuit, the operating frequency of the peripheral processing unit can be controlled by an externally input signal. And more detailed processing becomes possible.

[0072]

As described above, according to the present invention,
A frequency dividing control signal for setting the operating frequency in the halt mode is given to the frequency dividing circuit. When the halt instruction is executed and the mode shifts to the halt mode, the operating frequency of the clock signal applied to the peripheral processing unit is reduced. The power consumption in the peripheral processing unit is greatly reduced in proportion to the operating frequency, and as a result, the power consumption of the entire apparatus is greatly reduced.

Further, according to the present invention, when the operation mode is shifted from the halt mode to the normal operation, the peripheral processing unit switches to the normal operation frequency, so that there is an effect that it is possible to quickly shift from the call waiting state to the communication state.

Further, according to the present invention, by outputting a frequency division control signal to be applied to the frequency division circuit from the input / output circuit,
The operation frequency of the peripheral processing unit can be controlled by a signal input from the outside, so that more advantageous processing can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating a procedure of an operation according to the first exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional microcomputer having a standby function.

FIG. 7 is a time chart showing the operation of a conventional microcomputer having a standby function.

FIG. 8 is a flowchart showing an operation procedure of the microcomputer having the conventional standby function shown in FIG. 7;

FIG. 9 is a block diagram showing another configuration of a conventional microcomputer having a standby function.

FIG. 10 is a time chart showing the operation of the conventional microcomputer having the standby function shown in FIG.

[Description of Signs] 101 Oscillation circuit 102 Divider circuit 103 CPU 104 Timer counter 105 RAM (random access memory) 106 ROM (Read only memory) 107 I / O circuit 108 Standby control circuit 109 Standby release terminal 110 Output signal of oscillation circuit 101 111 HALT signal 112 Frequency division control signal 113 Peripheral clock supplied to peripheral processing unit 114 CPU clock 115 HALT command signal 116 Standby release signal 401 Oscillator circuit 402 Frequency divider circuit 403 CPU 404 Timer counter 405 RAM 406 ROM 407 I / O circuit 408 Standby control Circuit 409 Standby release terminal 410 Output signal of oscillation circuit 401 411 Halt signal 412 Frequency division control signal 413 Circuit provided to peripheral processing unit Edge clock 414 CPU clock 415 Halt command signal 416 Standby release signal 601 Oscillation circuit 602 Divider circuit 603 CPU 604 Timer counter 605 RAM 606 ROM 607 Input / output circuit 608 Standby control circuit 609 Standby release terminal 610 Output signal of oscillation circuit 601 611 Halt Signal 612 CPU clock 613 Peripheral clock supplied to the peripheral processing unit 614 Holt command signal 615 Standby release signal 901 Oscillator 902 Frequency divider 903 CPU 904 Timer counter 905 RAM 906 ROM 907 I / O circuit 908 Standby control circuit 909 Standby release terminal 910 Oscillation Output signal 911 of circuit 401 911 Carry signal of timer counter 912 Click 913 clock stop signal 914 Holt signal 915 Holt instruction signal 916 standby release signal 917 oscillation stop signal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/04 301

Claims (4)

(57) [Claims] An information processing apparatus includes a central processing unit (hereinafter referred to as a "CPU"), a peripheral processing unit, and a frequency dividing circuit for supplying a clock signal, and has a function of stopping a clock supplied to the CPU in a standby mode. In the data processing device provided with the frequency dividing circuit,
A first control signal is provided and thereafter the first control signal
The second control signal output from the CPU separately from the signal
Provided , based on the first control signal and the second control signal,
The frequency divider circuit stops the clock supply to the CPU and determines whether to switch the peripheral clock supplied to the peripheral processing device to a lower speed than during normal operation .
A data processing device. 2. A central processing unit (hereinafter referred to as "CPU").
And a peripheral processing device that performs a predetermined process. A data processing device comprising:
A standby control circuit for generating a standby mode for stopping supply of a clock signal to U; a standby release terminal for transmitting a standby release signal to the standby control circuit ;
Receiving, after that, separately from the first control signal, the CPU
Receiving the second control signal output from the
A standby mode based on the signal and the second control signal.
The data processing apparatus characterized by having a divider circuit for determining Luke switching the frequency division ratio of the clock signal to the peripheral processing device when de. 3. The CPU according to claim 1, wherein said first control signal supplied to said frequency dividing circuit is output from said CPU by a program command.
That data processing apparatus according to claim 1 or 2, characterized in that. 4. The first control provided to the frequency dividing circuit.
The data processing device according to claim 1 , wherein a signal is output from the peripheral processing device.