JPH01292416A - System for reducing power consumption of processor - Google Patents
System for reducing power consumption of processorInfo
- Publication number
- JPH01292416A JPH01292416A JP63122440A JP12244088A JPH01292416A JP H01292416 A JPH01292416 A JP H01292416A JP 63122440 A JP63122440 A JP 63122440A JP 12244088 A JP12244088 A JP 12244088A JP H01292416 A JPH01292416 A JP H01292416A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- frequency
- reference oscillation
- power consumption
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims description 6
- 230000004044 response Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
プロセッサの消費電力を低減する消費電力低減方式に関
し、
基準発振信号の周波数を切り替え得る基準発振源を設け
、プロセッサの必要処理速度に対応してこの基準発振信
号の周波数を動的に切り替え、消費電力を必要最小限に
することを目的とし、プロセッサに入力される外部事象
の頻度あるいはプロセッサの遊び時間の割合などに基づ
いて処理量を判断する処理量判断部と、この処理量判断
部によって判断された結果に基づいて、周波数を所定段
数上げあるいは所定段数下げた基準発振信号を発生する
基準発振源とを備え、この発生された基準発振信号を用
いて上記プロセッサを駆動するように構成する。[Detailed Description of the Invention] [Summary] Regarding a power consumption reduction method for reducing the power consumption of a processor, a reference oscillation source capable of switching the frequency of a reference oscillation signal is provided, and this reference oscillation signal is adjusted according to the processing speed required of the processor. A processing amount judgment unit that dynamically switches the frequency of the processor and determines the processing amount based on the frequency of external events input to the processor or the percentage of idle time of the processor, etc., with the aim of minimizing power consumption to the necessary minimum. and a reference oscillation source that generates a reference oscillation signal whose frequency is increased by a predetermined number of steps or lowered by a predetermined number of steps based on the result determined by the processing amount determination section, and the reference oscillation source that generates a reference oscillation signal whose frequency is increased by a predetermined number of steps or lowered by a predetermined number of steps based on the result determined by the processing amount determination unit. Configure to drive the processor.
本発明は、プロセッサの消費電力を低減する消費電力低
減方式に関するものである。The present invention relates to a power consumption reduction method for reducing power consumption of a processor.
一般に、Ｃ−ＭＯ３素子を使用したマイクロプロセッサ
は、基準発振源の周波数が高いと、Ｃ−ＭＯ３素子の性
質上、消費電力が大きくなる。このため、電池を電源と
する機器においては、マイクロプロセッサの消費電力を
低減させるために、動作しなくてもよい時に、基準発振
源を停止させる手法がある。しかし、この基準発振源を
停止させる手法を採用した場合、再起動させるための例
えば割り込みのための回路が必要となると共に、再起動
されるまでに時間がかかるという問題がある。更に、マ
イクロプロセッサを動作させる周波数は、最大の仕事量
に見合う周波数に固定的に設定していたため、少しの仕
事量に対しても固定的な周波数で動作され、余分な電力
を消費してしまうという問題があった。Generally, in a microprocessor using a C-MO3 element, when the frequency of the reference oscillation source is high, power consumption increases due to the nature of the C-MO3 element. For this reason, in devices powered by batteries, in order to reduce the power consumption of the microprocessor, there is a method of stopping the reference oscillation source when it does not need to operate. However, if this method of stopping the reference oscillation source is adopted, there is a problem in that a circuit for restarting the reference oscillation source, for example, for interrupt, is required and it takes time to restart the reference oscillation source. Furthermore, since the frequency at which the microprocessor operates was fixedly set to the frequency that corresponds to the maximum amount of work, it would operate at a fixed frequency even for a small amount of work, consuming excess power. There was a problem.
本発明は、基準発振信号の周波数を切り替え得る基準発
振源を設け、プロセッサの必要処理速度に対応してこの
基準発振信号の周波数を動的に切り替え、消費電力を必
要最小限にすることを目的としている。An object of the present invention is to provide a reference oscillation source that can switch the frequency of a reference oscillation signal, dynamically switch the frequency of this reference oscillation signal in accordance with the processing speed required by a processor, and minimize power consumption to the necessary minimum. It is said that
第１図を参照して課題を解決する手段を説明する。 Means for solving the problem will be explained with reference to FIG.
第１図において、プロセッサ１は、処理量判断部１−１
などから構成され、外部事象に対応した処理などを行う
ものである。In FIG. 1, a processor 1 includes a processing amount determining unit 1-1.
It consists of the following, and performs processing in response to external events.
処理量判断部１−１は、外部事象の顛度あるいはプロセ
ッサ１の遊び時間の割合などに基づいて処理量を判断す
るものである。The processing amount determination unit 1-1 determines the processing amount based on the frequency of external events or the percentage of idle time of the processor 1.
基準発振源２は、周波数切替信号に対応して周波数を切
り替えた基準発振信号をプロセッサ１に供給するもので
ある。The reference oscillation source 2 supplies the processor 1 with a reference oscillation signal whose frequency has been switched in response to the frequency switching signal.
本発明は、第１図に示すように、処理量判断部１−１が
プロセッサ１に入力される外部事象の穎度あるいはプロ
セッサ１の遊び時間の割合などに基づいて処理量を判断
してこの処理量に対応する周波数切替信号を基準発振源
２に通知すると、基準発振源２はこの通知を受けた周波
数切替信号に対応する周波数の基準発振信号を発生して
プロセッサｌに供給するようにしている。As shown in FIG. 1, in the present invention, a processing amount judgment unit 1-1 judges the processing amount based on the degree of purity of an external event input to the processor 1 or the percentage of idle time of the processor 1. When the reference oscillation source 2 is notified of the frequency switching signal corresponding to the processing amount, the reference oscillation source 2 generates a reference oscillation signal of a frequency corresponding to the frequency switching signal received and supplies it to the processor l. There is.
従って、プロセッサ１は、処理量に応じた必要最小限の
低い周波数の基準発振信号によって駆動され、ＣＭＯ３
素子などで作成した当該プロセッサ１が消費する電力を
必要最小限にすることが可能となる。Therefore, the processor 1 is driven by the minimum necessary low frequency reference oscillation signal according to the processing amount, and the CMO 3
It becomes possible to minimize the power consumed by the processor 1 made of elements or the like.
次に、第１図および第２図を用いて本発明の１実施例の
構成および動作を順次詳細に説明する。Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 and 2.
第１図において、プロセッサ１は、Ｃ−ＭＯ３素子など
を用いて作成したマイクロプロセッサなどであって、プ
ログラムを格納するＲＯＭ（読み出し専用メモリ）、デ
ータなどを格納するＲＡＭ（読み書き可能なメモリ）な
どから構成されている。このＣ−ＭＯ３素子を用いてプ
ロセッサ１を作成すると、Ｃ−ＭＯ３素子の性質上、駆
動クロック周波数に依存して消費電力が増減する。従っ
て、電池を用いて駆動する携帯用の機器にプロセッサ（
マイクロプロセッサ）１を用いる場合には、本実施例に
よって処理量に見合った必要最小限のクロック周波数で
動的に駆動するようにする。In FIG. 1, a processor 1 is a microprocessor made using C-MO3 elements, etc., and includes a ROM (read-only memory) for storing programs, a RAM (read-write memory) for storing data, etc. It consists of When the processor 1 is created using this C-MO3 element, power consumption increases or decreases depending on the drive clock frequency due to the nature of the C-MO3 element. Therefore, a processor (
When using a microprocessor (microprocessor) 1, according to this embodiment, it is dynamically driven at the minimum necessary clock frequency commensurate with the amount of processing.
基準発振源２は、プロセッサ１からの周波数切替信号に
対応した周波数の基準発振信号を切り替える態様で生成
するものである。The reference oscillation source 2 generates a reference oscillation signal of a frequency corresponding to the frequency switching signal from the processor 1 in a switching manner.
次に、第２図フローチャートを用いて第１図構成の動作
を詳細に説明する。Next, the operation of the configuration shown in FIG. 1 will be explained in detail using the flowchart shown in FIG.
第２図において、■は、通常動作を行う状態を示す。In FIG. 2, ■ indicates a state in which normal operation is performed.
■は、ＣＰＵの処理能力に、高速性が必要か否かを判別
する。これは、現在、基準発振源２からプロセッサ１に
供給されている基準発振信号に基づいて、プロセッサ１
が処理を行い、処理能力に不足が生じ、高速にする必要
があるか否かを判別することを意味している。この高速
性の必要性は、プロセッサ１に入力される外部事象の単
位時間当りの回数、あるいはプロセッサ１の遊び時間の
割合などに基づいて判断するようにしている。ＹＥＳの
場合には、■を行う、ＮＯの場合には、■を行う。In (2), it is determined whether high speed is necessary for the processing capacity of the CPU. This is based on the reference oscillation signal currently supplied to the processor 1 from the reference oscillation source 2.
This means determining whether or not there is a shortage in processing capacity and a need to increase the processing speed is necessary. The necessity of this high speed is determined based on the number of external events input to the processor 1 per unit time or the percentage of idle time of the processor 1. If YES, perform ■; if NO, perform ■.
■は、■で高速性が必要と判断されたので、現在の処理
量の判断を行う、これは、既述したように、プロセッサ
１の処理量（外部事象の発生頻度あるいはプロセッサｌ
の遊び時間の割合などから算出した処理量）をレベルｌ
、レベル２、・・・レベルｎのいずれかに段階づけ、こ
のレベルに対応して周波数を１段、２段、・・・、ｎ段
上げるような周波数切替信号を基準発振源２に通知する
。Since it was determined in ■ that high speed is necessary, the current processing amount is determined.
The amount of processing calculated from the percentage of play time, etc.
, level 2, . . . , level n, and notifies the reference oscillation source 2 of a frequency switching signal that increases the frequency by 1 step, 2 steps, . . . , n steps corresponding to this level. .
これに対応して所定段数周波数の上げられた基準発振信
号を基準発振源２が生成してプロセッサｌに供給する。Correspondingly, the reference oscillation source 2 generates a reference oscillation signal whose frequency has been increased by a predetermined number of steps and supplies it to the processor l.
これにより、プロセッサ１の処理量の増大に対応して、
動的に基準発振信号の周波数が高められる。。As a result, in response to an increase in the processing amount of the processor 1,
The frequency of the reference oscillation signal is dynamically increased. .
■は、■で高速性が必要でないと判断されたので、現在
の処理量の判断を行う、これは、既述したように、プロ
セッサ１の処理量をレベル１、レベル２、・・・レベル
ｎのいずれかに段階づけ、このレベルに対応して周波数
を１段、２段、・・・、ｎ段下げるような周波数切替信
号を基準発振源２に通知する。これに対応して所定段数
周波数の下げられた基準発振信号を基準発振源２が生成
してプロセッサｌに供給する。これにより、プロセッサ
１の処理量の減少に対応して、動的に基準発振信号の周
波数が低められる。Since it was determined in ■ that high speed is not necessary, the current processing amount is determined. The reference oscillation source 2 is notified of a frequency switching signal that lowers the frequency by one step, two steps, . . . , n steps corresponding to the level. Correspondingly, the reference oscillation source 2 generates a reference oscillation signal whose frequency has been lowered by a predetermined number of steps and supplies it to the processor l. As a result, the frequency of the reference oscillation signal is dynamically lowered in response to a reduction in the processing amount of the processor 1.
以上説明したように、本発明によれば、基準発振信号を
切り替え得る基準発振源２を設け、プロセッサｌの処理
量に対応して当該基準発振源２によって発振される基準
発振信号の周波数を増減する構成を採用しているため、
プロセッサ１は、処理量に応じた必要最小限の低い周波
数の基準発振信号によって駆動され、０ＭＯ３素子など
で作成した当該プロセッサ１が消費する電力を必要最小
限にすることができる。As explained above, according to the present invention, the reference oscillation source 2 capable of switching the reference oscillation signal is provided, and the frequency of the reference oscillation signal oscillated by the reference oscillation source 2 is increased or decreased in accordance with the processing amount of the processor l. Because we have adopted a configuration that
The processor 1 is driven by a reference oscillation signal of the minimum required low frequency according to the amount of processing, and the power consumed by the processor 1 made of 0MO3 elements or the like can be minimized.
第１図は本発明の１実施例構成図、第２図は本発明の動
作説明図を示す。
図中、１はプロセッサ、１−１は処理量判断部、２は基
準発振源を表す。FIG. 1 shows a configuration diagram of an embodiment of the present invention, and FIG. 2 shows an operation explanatory diagram of the present invention. In the figure, 1 represents a processor, 1-1 represents a processing amount determination unit, and 2 represents a reference oscillation source.
Claims (1)
いて、 プロセッサ（１）に入力される外部事象の頻度あるいは
プロセッサ（１）の遊び時間の割合などに基づいて処理
量を判断する処理量判断部（１−１）と、この処理量判
断部（１−１）によって判断された結果に基づいて、周
波数を所定段数上げあるいは所定段数下げた基準発振信
号を発生する基準発振源（２）とを備え、 この発生された基準発振信号を用いて上記プロセッサ（
１）を駆動するように構成したことを特徴とするプロセ
ッサの消費電力低減方式。[Claims] In a power consumption reduction method for reducing power consumption of a processor, the amount of processing is determined based on the frequency of external events input to the processor (1) or the percentage of idle time of the processor (1). a reference oscillation source (1-1) that generates a reference oscillation signal whose frequency is raised or lowered by a predetermined number of steps based on the result determined by the processing amount judgment portion (1-1); 2), and using this generated reference oscillation signal, the processor (
1) A method for reducing power consumption of a processor, characterized in that it is configured to drive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63122440A JPH01292416A (en) | 1988-05-19 | 1988-05-19 | System for reducing power consumption of processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63122440A JPH01292416A (en) | 1988-05-19 | 1988-05-19 | System for reducing power consumption of processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01292416A true JPH01292416A (en) | 1989-11-24 |
Family
ID=14835897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63122440A Pending JPH01292416A (en) | 1988-05-19 | 1988-05-19 | System for reducing power consumption of processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01292416A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6021502A (en) * | 1997-03-19 | 2000-02-01 | Mitsubishi Denki Kabushiki Kaisha | System for monitoring power consumption of semiconductor devices |
| US6751741B1 (en) | 1999-02-09 | 2004-06-15 | International Business Machines Corporation | Computer power management apparatus and method for optimizing CPU throttling |
| US6826702B1 (en) | 1999-09-28 | 2004-11-30 | Nec Corporation | Method and apparatus for reducing power consumption of a CPU in a radio set by adaptively adjusting CPU clock frequency according to CPU load |
| JP2005084712A (en) * | 2003-09-04 | 2005-03-31 | Renesas Technology Corp | Cache system |
| US7228445B2 (en) | 2002-06-28 | 2007-06-05 | Kabushiki Kaisha Toshiba | Clock frequency control method and electronic apparatus |
| JP2009032521A (en) * | 2007-07-26 | 2009-02-12 | Panasonic Electric Works Co Ltd | Discharge lamp lighting unit and illumination system |
| JP2009110509A (en) * | 2007-09-28 | 2009-05-21 | Intel Corp | System and method for selecting optimal processor performance level by using processor hardware feedback mechanism |
| US9526026B2 (en) | 2012-09-21 | 2016-12-20 | Fujitsu Limited | Method for controlling information processing apparatus and information processing apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS608920A (en) * | 1983-06-28 | 1985-01-17 | Sharp Corp | Electronic computer |
-
1988
- 1988-05-19 JP JP63122440A patent/JPH01292416A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS608920A (en) * | 1983-06-28 | 1985-01-17 | Sharp Corp | Electronic computer |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6021502A (en) * | 1997-03-19 | 2000-02-01 | Mitsubishi Denki Kabushiki Kaisha | System for monitoring power consumption of semiconductor devices |
| US6751741B1 (en) | 1999-02-09 | 2004-06-15 | International Business Machines Corporation | Computer power management apparatus and method for optimizing CPU throttling |
| US6826702B1 (en) | 1999-09-28 | 2004-11-30 | Nec Corporation | Method and apparatus for reducing power consumption of a CPU in a radio set by adaptively adjusting CPU clock frequency according to CPU load |
| US7228445B2 (en) | 2002-06-28 | 2007-06-05 | Kabushiki Kaisha Toshiba | Clock frequency control method and electronic apparatus |
| JP2005084712A (en) * | 2003-09-04 | 2005-03-31 | Renesas Technology Corp | Cache system |
| JP2009032521A (en) * | 2007-07-26 | 2009-02-12 | Panasonic Electric Works Co Ltd | Discharge lamp lighting unit and illumination system |
| JP2009110509A (en) * | 2007-09-28 | 2009-05-21 | Intel Corp | System and method for selecting optimal processor performance level by using processor hardware feedback mechanism |
| US9526026B2 (en) | 2012-09-21 | 2016-12-20 | Fujitsu Limited | Method for controlling information processing apparatus and information processing apparatus |
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