JPS608920A - Electronic computer - Google Patents

Abstract

PURPOSE:To reduce a power consumption, and also to improve a precessing speed by providing a means for changing an oscillation frequency, and changing a machine cycle of an apparatus in accordance with a key input instruction or a program instruction. CONSTITUTION:A CPU1 is in a low speed mode state by connecting a low speed processing oscillator 8 to a clock generator 5, and when inputting a user program, etc. by a key, it is received in this state. When the input is ended, the CPU becomes in a high speed mode state by connecting a high speed processing oscillator 7 to the generator 5, and executes an internal processing such as an operation, etc. at a high speed. When the internal processing is ended, the CPU becomes in a low speed mode state again. In this way, when a high speed processing of a key input, etc. is unnecessary, the processing is executed by a low speed operation so that the power consumption becomes small, and when it takes time for a processing such as the internal processing, etc., the processing is executed by a high speed operation, by which the execution time is shortened.

Description

[Detailed Description of the Invention] Technical Field> The present invention relates to electronic computers such as small computers and electronic translators, and in particular, by changing the operating speed of the equipment,
This reduces power consumption and improves the processing speed of the device.

<Prior Art> Generally, the operating speed and power consumption of a device are inversely proportional. In contrast, in conventional battery-powered electronic computers, the operating speed (machine cycle) is
There is only one oscillator Z, which determines .

For this reason, there is a problem that if priority is given to operating speed, power consumption increases and it is not possible to withstand long or long-term use, and if priority is given to operating time or period of use, operating speed decreases and high-speed processing cannot be expected. Ta.

Purpose of the present invention The present invention has been made in view of such conventional problems, and its purpose is to improve display, for example, by changing the machine cycle of the device as appropriate in response to key manual commands or program commands.

The key objective is to provide an electronic computer with low power consumption and improved overall processing speed by operating at low speed during manual input (program input) and at high speed during internal processing such as arithmetic operations.

<Example> The present invention will be explained in detail below with reference to the drawings.

FIG. 2 is a schematic configuration diagram of an electronic computer according to the present invention.

In the figure, 1 is a CPU (central processing unit), 2 is a keyboard, 3 is a display memory, and 4 is a display device, which are connected as shown.

5 is a clock generator connected to the CPUI; 6 is a switching gate that switches and connects the oscillator 7 or 8 to the clock generator 5; Gate control is performed in response to the output.

The oscillators 7 and 8 are for determining the machine cycle of the CPUI, and are both composed of crystal oscillators, but the oscillator 7 has a higher oscillation frequency. That is, the oscillator 7 is used for high-speed processing, and the other oscillator 8 is used for low-speed processing.

FIG. 3 is an operation flowchart, and the operation will be explained in detail based on this diagram.

Normally, the CPU resets the output buffer F, and uses the reset output to connect the low-speed processing oscillator 8 to the clock generator 5 to enter the low-speed mode, and input of a user program using keys is accepted in this state. When the input of the user program is finished, that is, when the CPU 1 detects the end statement of the user program, it sets the output buffer F, connects the high-speed processing oscillator 7 to the clock generator 5, and enters the high-speed mode state. Executes internal processing such as calculations.

When the internal processing is completed, the CPU 1 resets the output buffer F again to enter the low speed mode state, and in this state displays the results based on the internal processing.

In this way, when high-speed processing is not required, such as key power or display, processing is performed at low speed to reduce power consumption, and when processing generally requires time, such as internal processing, processing is performed at high speed. We are saving time.

In addition to the machine cycle switching using the program control method as in the above example, as shown in FIG.
The output buffer F may be set or reset by inputting ``LOCK'' or ``LCLOCK,'' or the output buffer F may be set by simply using the ON and OFF keys. Furthermore, it is also possible to normally perform low-speed processing, switch to high-speed processing in relation to a start signal of internal processing, and switch to low-speed processing in relation to an end signal of the same processing.

Effects> As described above, the electronic computer of the present invention is equipped with a means for changing the oscillation frequency (machine cycle) of the CPU in multiple steps, and changes the machine cycle of the device as appropriate according to key manual commands or program commands. Since the power consumption can be changed and the processing speed can be improved, it is most suitable for use in a battery-powered computer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main part of a conventional device, FIG. 2 is a block diagram of a device of the present invention, and FIGS. 3 and 4 (1). (2) is a flowchart for explaining the operation. 1 is a CPU, 5 is a clock generator, 6 is a switching gate, 7 and 8 are oscillators, and F is an output buffer. ■Agent Patent attorney Aihiko Fuku (2 others) Figure 2 HCLOCK LCLOCK Figure 3 RErLIRN RETURN (/) Figure 4 of t2

Claims (1)

[Claims] 1. An electronic computer characterized by being equipped with means for changing the oscillation frequency (machine cycle) of the CPU in multiple stages, so that the machine cycle of the device can be changed as appropriate in accordance with key human commands or program commands. .