JPH0527865A - Device with processor - Google Patents

Abstract

PURPOSE:To reduce power consumption without lowering a processing speed. CONSTITUTION:When a designation signal 131 to be transmitted by a timer 13 designates an operation state for the operation for which a clock signal generation part 12 is made to operate, a first clock signal is generated as a clock signal for the operation of a processor 11. When the designation signal 131 designates a non-operation state, a second signal with frequency for which current consumption of the processor 11 is defined as current in the vicinity of 0 is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus provided with a processor that operates using a battery or the like as a power source, and more specifically,
The present invention relates to an apparatus including a processor that reduces power consumption.

[0002]

2. Description of the Related Art One of various devices using a processor is the device shown in FIG. In this device, according to the operation as the processor 91 for main processing for performing calculation and data processing, and the drawing output from the processor 91, the image memory 93 connected bidirectionally is displayed with characters and figures. The same operation as the drawing processor 92 performing the drawing operation is performed by the same C
A configuration that uses a PU chip is adopted. Then, by using the display processor 94, the image data drawn by the drawing processor 92 in the image memory 93 is read and the read image data is sent to the display 95. Therefore, the characters and figures drawn as data in the image memory 93 are displayed as figures on the display unit 95.

[0003]

Since the display processor 94 in the above configuration reads out the image data drawn in the image memory 93 at a speed synchronized with the display scan of the display unit 95, the processing speed thereof is It is determined dependently and does not affect the display change speed. However, the processing speed of the main processing processor 91 or the drawing processor 92 does not matter in the case of simple processing, but in the case of complicated data processing or image modification, the higher the processing speed is. Data processing and image changes can be performed quickly. However, since the processor 91 and the drawing processor 92 consume more power as the processing speed becomes faster, there is a problem that the processing speed must be reduced in order to reduce the consumption of the battery in the device using the battery.

The present invention has been conceived in order to solve the above problems, and an object thereof is to provide an apparatus including a processor capable of reducing power consumption without lowering the processing speed. ..

[0005]

In order to solve the above-mentioned problems, a device provided with a processor of the present invention is a device having different frequencies.
One of the two kinds of clock signals is the first clock signal and the other is the second clock signal, and the specification signal is a signal that alternately specifies two kinds of states of the operating state and the non-operating state. Generates a first clock signal that is a clock signal for operating the processor when specifies the operating state, and generates a second clock signal that makes the processor inactive when the specifying signal specifies the non-operating state. A configuration is provided that includes a clock signal generation unit that generates a clock signal, and the frequency of the second clock signal is set to a frequency at which the current consumption of the processor is near zero.

[0006]

The clock signal generation unit generates the first clock signal which is the clock signal for operating the processor or the second clock signal which is the clock signal for non-operating according to the designation signal. .. Further, since the processor operates using the clock signal generated by the clock signal generation unit as a reference signal, the processor is in an operating state when the clock signal generation unit generates the first clock signal, and when generating the second clock signal. Inactive state. That is, the current consumption of the processor is the current consumption specified by the processing speed during operation, and the power consumption approximates to 0 during non-operation. On the other hand, due to the configuration of the internal elements of the processor, the current consumption does not become n times even when the processing speed is increased by n times, and remains only m times, which is smaller than n times. Further, when the average processing speed of a processor having n times the processing speed is set to a speed close to the processing speed before being made n times, the ratio of the operating state and the non-operating state designated by the designation signal is 1 pair. (N-1). Therefore, the power consumption P of the processor is P = m × (1 / n) (where m is a value smaller than n).

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the electrical construction of an embodiment of the present invention.

In the figure, a bus line 20 consisting of an address bus and a data bus is connected to a processor 11 which performs calculations, data processing, drawing command transmission, etc., and a keyboard 14 is connected to the bus line 20. , RAM15, ROM
16 and the display controller 17 are connected. The keyboard 14 and the ROM 16 transmit data to the bus line 20, the RAM 15 exchanges data bidirectionally with the bus line 20, and the display controller 17 receives data from the bus line 20. It is configured to be.

The display controller 17 and the image memory 18 are bidirectionally connected, and an output from the display controller 17 is given to the display device 19. The clock signal generated by the clock signal generation unit 12 is given to the processor 11, and the designation signal 131 output from the timer 13 is guided to the clock signal generation unit 12.

In the above configuration, assuming that the processor having a reference processing speed is the processor A, the processing speed of the processor A is shown as speed 1 and the current consumption thereof is shown as a value 1, the present embodiment will be described. The processing speed of the processor 11 used is 2 times that of the processor A.
It is twice as fast. Further, the ratio of the current consumption when the processor 11 processes at twice the speed of the processor A and the current consumption when the processor A processes at the speed of 1 is that the processing speed of the processor 11 is 2 of A
Since it is doubled, the value m is smaller than 2 and larger than 1. Further, the internal structure of the processor 11 is composed of CMOS elements that enable complete static operation.

FIG. 2 is an explanatory view showing the operating states of the main parts of one embodiment of the present invention. The operation of one embodiment of the present invention will be described below with reference to FIG.

During operation, the processor 11 reads a program from the ROM 16 to perform an operation determined by the program. In this operation, when data is sent from the keyboard 14, the data is read and the operation is in accordance with the read data.

The operation according to the data from the keyboard 14 is an operation determined by the data from the keyboard 14 according to the program stored in the ROM 16, and an instruction is given to the display controller 17 via the bus line 20. For example, the image display is changed by giving it, or the processing of a plurality of data stored in the RAM 15 and the processing result are stored in the RAM 15.

Further, the display controller 17 is a processor 11
The image data in the image memory 18 is changed according to the instruction from. In addition, the image data in the image memory 18 is read according to the display timing of the display device 19, and the read image data is sent to the display device 19.
To display the image data.

On the other hand, the timer 13 generates a designating signal 131 in which H level designating an operating state and L level designating a non-operating state alternate with each other for every constant equal period t1, and the clock signal generating section 12 is produced. To send to. The clock signal generation unit 12 to which this signal is guided generates a clock signal having a frequency at which the processing speed of the processor 11 is twice that of the processor A as the first clock signal when the designation signal 131 becomes H level. Then, the generated first clock signal is sent to the processor 11.

Further, when the designation signal 131 becomes L level, the clock signal generator 12 has
The second clock signal is generated with the current consumption of 11 as a current in the vicinity of 0. In the present embodiment, its frequency is set to 0. Therefore, the clock signal generator 12
Sends the signal that remains at the L level continuously to the processor 11 as the second clock signal.

Since the clock signal generator 12 performs the above-described operation, the processor 11 performs one of the above-mentioned operations at a speed twice as fast as that of the processor A in the specified period of the operation state in which the specification signal 131 is at H level. Do one. Further, during the designated period of the non-operating state in which the output of the timer 13 is at the L level, the operation standby state is set.

The processing amount performed by the above operation is the processing amount indicated by the area of the shaded portion 31 in FIG. 2, and the processing speed is twice that of the processor A during the operation, and the operating time is The processing amount indicated as the area of the shaded portion 31 is equal to the processing amount when the processor A continuously performs the processing operation because the ratio between the stop period and the suspension period is 1: 1. ..

On the other hand, the value m indicating the ratio of the current consumption during the operation of the processor 11 and the current consumption of the processor A is larger than 1 and smaller than 2, and the clock signal generator 12 is the second one. Since the current consumption is close to 0 during the period when the clock signal is transmitted, the shaded area in FIG.
The power consumption of the processor 11, which is shown as an area of 32, is shown as P = m × (1/2) where P is the value, and the value P is P <1.

In other words, the data processing amount of the processor 11 is equal to the processing amount when the processor A continuously operates, but the power consumed by the processor 11 is the power consumed by the processor A. It has less power.

The present invention is not limited to the above-described embodiment, and the processor 11 has been described in the case of a configuration using a chip capable of doubling the processing speed of the reference processor A, but other configurations. As an example, the processor 11 can be configured to employ a chip that enables a processing speed three times that of the processor A (however, at this time, the frequency of the first clock signal is The frequency is set to be three times as high, and the ratio of the period for supplying the first clock signal to the processor 11 and the period for supplying the second clock signal is set to 1: 2).

As the frequency of the second clock signal, the case where the frequency is 0 has been described, but as the other frequencies, for example, the first clock signal can be used as a frequency near the lowest frequency allowed by the processor 11. It is possible to configure the frequency to be 1/100 of the frequency of.

The case where the second clock signal is a clock signal having a frequency of 0 and a continuous L level is used as the second clock signal has been described.
A configuration in which continuous H levels are used as the second clock signal is possible.

[0025]

The device having the processor according to the present invention generates the first clock signal as the clock signal for the operation of the processor when the designation signal designates the operation state for the operation to be performed by the clock signal generation section. When the designating signal designates the non-operating state, the operation is such that the second clock signal having a frequency in which the current consumption of the processor is close to 0 is generated. Therefore, the current consumption of the processor is the first clock signal. Since two kinds of current, that is, the consumption current defined by the frequency of the signal and the consumption current in the vicinity of 0, are consumed alternately, the average value of the consumption current is reduced, resulting in a decrease in processing speed. It is possible to reduce the power consumption without the need.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an operating state of a main part of one embodiment of the present invention.

FIG. 3 is a block diagram showing an electrical configuration of a conventional technique.

[Explanation of symbols]

 11 Processor 12 Clock signal generator 131 Designation signal

Claims (1)

Claim: What is claimed is: 1. One of two types of clock signals having different frequencies is used as a first clock signal and the other is used as a second clock signal, and two types of operating state and non-operating state are provided. When the signal for alternately designating the state of 1 is used as the designation signal, when the designation signal designates the operation state, a first clock signal which is a clock signal for operating the processor is generated, and the designation signal is When designating an operating state, a clock signal generating unit for generating a second clock signal which is a clock signal for deactivating the processor is provided, and the frequency of the second clock signal is such that the current consumption of the processor is 0. An apparatus provided with a processor characterized in that the frequency is set to a current in the vicinity.