JPH0384585A - Information processor - Google Patents

Abstract

PURPOSE:To easily reduce the current consumption by lowering the clock frequency of a circuit part which controls a display device, CONSTITUTION:An image is displayed on a CRT 19 by a signal line 21 generat ed under video control 17 and VLI 18 generates a signal line 22 for driving a liquid crystal display device 20 according to the signal line 21 to display an image on the liquid crystal display device 20. In this case, the VLI 18 operates asynchronously with the signal line 21 and the liquid crystal display device 20 can be drive irrelevantly to the frequency of the signal line 21. Conse quently, when only the liquid crystal display device 20 is projected, the frequency of the signal line 21 can be lowered. Therefore, CLK supplied to the CRTC 14 is lowered by a circuit 13 to reduce the current consumption of a VRT 15 which has the largest power consumption. Consequently, the power consump tion of the whole device can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention provides an information processing device with reduced power consumption.

[Prior Art] A conventional power consumption reduction mechanism in an information processing device changes components from components that consume a large amount of current to components that consume less current. For example, in logic IC, TTL
It was known to use CMOS components instead, or to lower the frequency of only the CPU clock signal.

[Problem to be solved by the invention] However, simply replacing the currently used parts with parts that consume less power will consume a lot of power for the entire information processing device, Processing devices have the problem of shortened battery life, resulting in increased weight and the inability to use the device while being carried around.

In addition, as for the method of lowering the CPU clock frequency, the ratio of main memory access time to the actual use of the information processing device is generally not that high, so in reality, it is difficult to reduce the power consumption. The result is that it does not decrease. Furthermore, lowering the clock frequency of the CPU will reduce the performance of the information processing device.

Therefore, in order to solve these problems, it is an object of the present invention to provide an information processing device that reduces power consumption without degrading the performance of the information processing device.

[f! Means for Solving the Problem] The present invention includes a drive circuit that drives a first display body, and a drive circuit that converts signals generated from the drive circuit that drives the first display body to drive a second display body. It is characterized in that it includes a drive circuit, and drives the drive circuit of the first display body with a signal that drives the second display body by switching a clock signal that drives the display body.

[Example] Hereinafter, the present invention will be explained in detail based on examples.

FIG. 1 is a block diagram of a display portion of an information processing apparatus using the present invention. The display part of this information processing device is C
PU 10, system bus (address bus, data bus) 11, oscillation circuit 12, clock switching circuit 13, CRT
C (CRT controller) 14, VRAM 15, CG (
It consists of a character generator) 16, a video control 17, a CRT (cathode ray tube) 19, and a liquid crystal display device 20.
Separate signal for T display (R.

It is composed of a circuit that generates a signal for a liquid crystal display device from G and B).

The information processing device according to the present invention uses a liquid crystal display device as a main display device, and is configured to be able to use a CRT at the same time. An image is displayed on the CRT 19 via a signal line 21 created by the video control 17. Also, based on the signal line 21, VL118
An image is displayed on the liquid crystal display device 20 by creating a signal line 22 for driving the liquid crystal display device. Normally, the frequency of the signal line 21 that drives the CRT is matched to the horizontal synchronization frequency of the CRT, so it has a high frequency of 21 MH2. If the VL 118 can operate asynchronously with the signal line 21, the liquid crystal display device can be driven no matter what the frequency of the signal line 21 is.

FIG. 2 is an example showing in detail the contents of the VL 118 in the block diagram of FIG. 1. If VL118 is designed with such a mechanism, separate CRT signals (VG,
VR, VB) 24 (7) A liquid crystal display device can be driven regardless of the frequency.

By having its own oscillation circuit 23, the VL118 has realized the creation of a liquid crystal display drive signal asynchronous to the input signal.

If the system is such that the CRT 19 and the liquid crystal display device 20 are displayed at the same time, if the frequency of the signal line 21 is lowered, an image will be displayed on the liquid crystal display device 20, but the image will not be properly displayed on the CRT 19. This is because it does not match the horizontal synchronization frequency of the CRT.

Therefore, by switching the frequency of the signal line 21,
When displaying only the liquid crystal display device, the frequency of the signal line 21 can be lowered.

In the information processing device shown in Figure 1, the part that consumes the most power is the VRAM1 connected to the CRTCI4.
It is 5. Further, the display section shown in FIG. 1 must always continue to operate in order to display the screen even when the information processing apparatus is powered on and the CPU 10 is not performing any processing. By the way, R of DPRAM, SRAM5 DRAM, etc. used in VRAM15
AM generally consumes more power as its operating frequency becomes higher. In other words, the most effective way to reduce the power consumption of the information processing device is to lower the operating frequency of the VRAM 15.

In order to lower the operating frequency of the VRAM 15, the CLK frequency applied to the CRTCI 4 shown in FIG. 1 may be lowered.

This also lowers the frequency of the signal line 21. Therefore, as an example of the clock switching circuit 13 shown in FIG. 1, FIG. 3 shows an example of a circuit that halves the frequency of CLK.

CLK input to CLK I N3 i (corresponding to the output of the oscillation circuit 12 in Figure 1) is output as is to CLKOUT32 when the signal of CLKCH033 is "L", and is frequency-divided when CLKCHG33 is It HI+. The frequency is halved and the period is doubled.

Flip-flop 35.36 and N0R34 are CLK
This is a circuit that determines the timing for switching the frequency. C
Sending a signal to the LKCHG33 may be done by software, or may be done by a hardware switch.

As mentioned above, the circuit shown in Figure 3 allows the first
By lowering the CLK applied to the CRTC 14 in the figure, the current consumption of the VRAM 15, which consumes the most power in the information processing device, can be reduced, and as a result, the power consumption of the entire information processing device can be easily reduced.

Especially in the case of a portable battery-powered information processing device, if there is an AC outlet at home, the CLK frequency can be increased and a CRT is used, and if it is used outdoors with battery power, the CLK frequency can be lowered and a liquid crystal display device used. battery life can be extended without reducing performance.

In addition, the weight of the battery can be reduced due to the reduced power consumption.
An information processing device that is easy to carry can be realized.

[Effects of the Invention] In an information processing device, current consumption can be easily and significantly reduced by lowering the clock frequency of at least the circuit section that controls the display device. In particular, in the case of an information processing device using a battery or the like as a power source, the usage time can be significantly extended.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of an information processing device used in the present invention. FIG. 2 is a block diagram of a screen used in the information processing apparatus according to the present invention. FIG. 3 is a diagram of an example circuit for halving the frequency of CLK according to the present invention. 10: 11: 12: 13 = 142 PU System bus oscillation circuit clock switching circuit RTC Fig. 2 Fig. 3

Claims (1)

[Scope of Claims] A drive circuit that drives a first display body, and a drive circuit that converts a signal emitted from the drive circuit that drives the first display body and drives a second display body. An information processing device, characterized in that a drive circuit for the first display body is driven by a signal for driving the second display body by switching a clock signal for driving the display body.