JPH05100765A - Computer system - Google Patents

Abstract

PURPOSE:To perform the power saving by operating an oscillator to supply a clock to a display to be used only out of plural oscillators. CONSTITUTION:Data held by respective registers 121 and 122 are given from a CPU. A selecting register 121 gives a selecting signal to a multiplexer 124 and an enable register 122 gives an enable signal to an oscillator 110. Oscillating circuits 123a-123c are the circuits to generate a basic frequency to operate a CRT 107a, a flat display 107b, and a high resolution CRT 107c respectively, and respective oscillating circuits 123a-123c are operating-controlled by the enable signal sent from the enable register 122. The multiplexer 124 receives the selecting signal sent from the selecting register 121 and outputs the signal from the oscillator 110. Based on the signal, a displaying controller 106 is operated, and the oscillating circuit not in use is rested.

Description

Detailed Description of the Invention

 [Object of the Invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal computer, and more particularly to control of clocks applied to a plurality of display devices.

[0002]

2. Description of the Related Art Monochrome CRTs, color CRTs, high resolution CRTs,
There are flat displays and so on. Since these display devices have different resolutions, frame frequencies, and scanning methods, they are given different clocks. Therefore, it has an oscillator that generates a fundamental frequency corresponding to each display device. Among the clocks sent from the plurality of oscillators, the clock corresponding to the display device to be used is selected, and the display data of the display device and the control signal are generated by the selected clock.

[0003]

However, since the clocks for a plurality of display devices are input, and the clocks of the display devices to be used are selected and output, the oscillators that are not used are also operating, resulting in unnecessary power consumption. Was consumed.

In view of the above points, the present invention provides a computer system that realizes power saving by operating only the oscillator that supplies a clock to a display device to be used among a plurality of oscillators. To aim. [Constitution of Invention]

[0005]

In order to achieve the above object, the present invention is directed to a computer system connectable to a plurality of display devices having different control methods, wherein a plurality of oscillators having different clock frequencies are generated, and the plurality of oscillators. The display device selecting means for determining whether or not the display device is used, and the oscillator operating means for operating the plurality of oscillators based on the display device selecting means.

Further, from the first display device in use to the second display device.
When the instruction to switch to the display device is received, the second oscillator that generates the clock to be supplied to the second display device is activated, and after the frequency of the clock is stabilized, the clock output from the second oscillator is displayed. It is provided with clock control means for sending to the device and stopping the first oscillator corresponding to the first display device.

[0007]

The computer system can be connected to a plurality of display devices having different control methods. There are multiple oscillators, and the frequencies of the generated clocks are different. The display device selection means determines whether or not each display device is used.
The oscillator stopping means stops the oscillator of the unused display device from the information sent from the display device selecting means.
As a result, power saving can be realized by operating only the oscillator that supplies the clock to the display device to be used among the plurality of oscillators.

Further, the clock control means, when receiving the instruction to switch from the first display device in use to the second display device, activates the second oscillator for generating the clock to be supplied to the second display device. .. Then, the clock control means sends the clock output from the second oscillator to the display device and stops the first oscillator corresponding to the first display device after the frequency of the clock is stabilized. As a result, a beautiful image can be displayed without using an unstable clock.

[0009]

EXAMPLE An example of the computer system of the present invention will be described below.

FIG. 1 is a block diagram showing the entire computer system according to this embodiment. The CPU 101 controls the entire system, specifies an address for writing / reading data to / from the memory 105, and outputs a display command to the display control device 106. DMA 108 is Direct Memory Access, and is a device that directly transfers data without going through the CPU 101. When the DMA 108 is transferring data, the CPU 101 cannot access the memory 105 or the like. The keyboard 103 is a means by which a user inputs data. The KBC 102 is a keyboard controller, and when key data is input from the keyboard 103, the CPU outputs a key code corresponding to the input key.
Send to 101. The memory 105 is a semiconductor storage element that holds a BIOS, an OS, application software, and the like. The memory control device 104 controls the timing of reading data from the memory 105 and writing data to the memory 105. The VRAM 111 is a memory that temporarily stores data to be displayed, and is controlled by the display control device 106. The display control device 106 is
CR which is a display device upon receiving a display command from the CPU 101
The display is controlled to be displayed on the T107a, the flat display 107b, or the high resolution CRT 107c. Details of the display control device 106 will be described later. CRT1
07a, flat display 107b, high resolution CR
T107c is a display device, and each display device is
Since the resolution, frame frequency, and scanning method are different,
The fundamental frequency of the video is also different. Therefore, the display control device 1
An oscillation circuit (to be described later) corresponding to each display device is provided in the oscillation device 110 for 06. The power supply controller 109 controls to supply power to each device in the system. The bus 112 is the CPU 101, KBC1
02 is a signal line for connecting the memory control device 104, the memory 105, the display control device 106, and the power supply controller 109, and transmitting a signal between each device. Next, the display control device 106 and the oscillating device 110 of the present embodiment are shown in FIG.
Will be described. The select register 121 and the enable register 122 are storage devices for storing the display device to be used.

The data held in each of the registers 121 and 122 is given from the CPU 101. The select register 121 gives a select signal to the multiplexer 124. The enable register 122 gives an enable signal to the oscillator 110.

The oscillator circuits 123a to 123c each include a CRT10.
7a, flat display 107b, high resolution CRT
107c is a circuit that generates a fundamental frequency for operating. The operation of each of the oscillation circuits 123a to 123c is controlled by an enable signal sent from the enable register 122.

The multiplexer 124 receives the selection signal sent from the select register 121 and outputs the signal from the selected oscillator 110. Based on this signal,
The display control device 106 operates. Next, the operation of this embodiment will be described with reference to the time chart of FIG. First, the time when the system starts up will be shown.

From CPU 101, enable register 1
CRT1 to select register 121 after a delay of 22, T
When the data indicating that 07a is used is sent, the data indicating the CRT 107a is held in each register. The time T is a little longer than the longest time from the start of generation of the clock of the oscillation circuits 123a to 123c to the stabilization thereof, and is set in advance. Enable register 122
Holds data and sets clock enable 1 to'H '
And outputs it to the oscillation circuit 123a in the oscillator 110. The oscillator circuit 123a starts operating when receiving this signal. The oscillator circuit 123a outputs the basic clock for the CRT 107a to the multiplexer 124.

The select register 121 is the CPU 101.
When the data from is held, clock select 1 is'H '
Output to the multiplexer 124. The multiplexer 124 causes the oscillator circuit 1 to operate according to the clock select 1.
The signal sent from 23a is output. Next, CRT10
A case where the display device is changed from 7a to the flat display 107b will be described.

First, the CRT 107a and the flat display 107 are transferred from the CPU 101 to the enable register 122.
Data using both b is sent and held in the enable register 122. The enable register 122 is
When the data is held, the clock enable 1 is kept at “H” and the clock enable 2 is set at “H”.
It outputs to the oscillation circuit 123b in 0. Oscillation circuit 123b
Starts operating when it receives this signal. As a result, the oscillation circuits 123a and 123b output each basic clock to the multiplexer 124. At this time, the select signal input to the multiplexer is still clock select 1.
Since it is H ', the multiplexer 124 outputs the basic clock sent from the transmission circuit 123a.

The CPU 101 uses the enable register 12
2 from the time when data using both the CRT 107a and the flat display 107b was sent, delayed by T,
Flat display 10 to each register 121, 122
Outputs data indicating that only 7b is used. When these registers hold these data, the clock enable 1 and the clock select 1 become "L", the oscillation circuit 123a stops operating, and the multiplexer 124 receives "H" of the clock select 2 and the oscillation circuit 123b. Outputs the basic clock of. Further, other switching can be performed in the same manner. As described above, power saving can be realized by turning on / off the operation of the oscillation circuits 123a to 123c by the clock enable signal.

Further, when the display device is changed, the clock of the display device to be used is stabilized and then displayed, so that a beautiful image can be displayed even when the display device is switched.

[0019]

As described above, the computer system of the present invention can realize power saving by suspending the unused oscillator. In addition, since a stable clock can be supplied even when the display device is switched, a clear image can be displayed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an entire computer system according to an embodiment.

FIG. 2 shows a display control device 106 and an oscillating device 110 of the present embodiment and is another one.

FIG. 3 is a time chart diagram of the present embodiment.

[Description of Reference Signs] 101 CPU 106 Display controller 111 VRAM 107a CRT 107b Flat display 107c High resolution CRT 110 Oscillator 121 Select register 122 Enable registers 123a to c Oscillator circuit 124 Multiplexer

Claims (2)

[Claims] 1. In a computer system connectable to a plurality of display devices having different control methods, a plurality of oscillators having different frequencies of clocks to be generated, and a display device selecting means for determining whether or not the plurality of display devices are used. , An oscillator operating means for operating the plurality of oscillators based on the display device selecting means. 2. The computer system according to claim 1, wherein the second oscillator generates a clock to be supplied to the second display device when receiving a command to switch from the first display device in use to the second display device. And a clock control means for sending the clock output from the second oscillator to the display device and stopping the first oscillator corresponding to the first display device after the clock frequency is stabilized. Characteristic computer system.