JPS60198619A - Information processor - Google Patents

Abstract

PURPOSE:To operate an information processor at an optimum processing speed together with reduction of the power consumption per time, by controlling the drive frequency of a CPU in response to the key input interval. CONSTITUTION:An information processor is provided with a CPU1, a frequency/ voltage converting circuit 6 which produces the voltage corresponding to the interval of the pulse sent from the CPU1, an oscillator 7 which produces a frequency corresponding to the voltage given from the circuit 6, a timer circuit 8, etc. For transmission control of a system clock done by the oscillator 7, the CPU1 decides the present key input process or an arithmetic processing, etc. In the case of the key input processing, the output of the circuit 8 is discontinued for pulses of a fixed interval and the oscillator 7 is oscillated with a low oscillation frequency corresponding to the key input interval. Thus a system clock of a low frequency is delivered to the CPU1. Therefore the processing speed of the CPU1 is reduced when the key input period is long. Thus the power consumption can be reduced with an information processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus that changes processing speed depending on the interval between key inputs.

[Prior Art] In recent years, with the development of OMO3-LSI technology and progress in streamlining office work, portable terminal devices that can perform office work outside the office have begun to be used.

This type of equipment includes central processing units, keyboards, printers,
It is equipped with a display consisting of a liquid crystal, etc., a storage device using 0MO3-RAM, an interface device for data transfer to other small information processing devices, etc., and is applied to data collection outdoors, but its shape , batteries (e.g. nickel-cadmium batteries) are the only power source that can be used due to weight restrictions.
capacity is limited. In addition, if the battery runs out during operation, it will cause a major operational disruption.

For this reason, conventionally, the content of business operations to be processed by this type of portable terminal device has been limited according to the device's performance, and processing has been performed in accordance with the device's performance.

However, as the technology has passed the initial stage of widespread use, there are demands for expanded business content and for portable terminal devices that can perform more advanced processing.

In order to meet this demand, CPU processing speed has been improved and memory capacity has been expanded. However, because the technological progress of batteries, which are power sources, is slower than that of semiconductors, it is necessary to improve the performance of devices while keeping the power source capacity constant.

0MO3-LSI, etc. used in this type of equipment consumes more power in proportion to the frequency of the system clock driven by it, and as the number of LSIs increases to expand processing capacity, power consumption increases. I had done it.

For this reason, there is a strong need to reduce power consumption in portable terminal devices that can perform advanced processing.

[Objective] The present invention has been made in view of the problems of the prior art described above, and an object of the present invention is to provide an information processing device with low power consumption.

[Embodiment] Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

In the figure, l is the CPU, 2 is the RAM composed of 0MO3, etc.
3 is a display device such as a liquid crystal that displays information; 4 is a keyboard; 5 is a printer; 6 is a frequency that receives pulses from the CPU and generates a voltage corresponding to the pulse interval.
Voltage conversion circuit (hereinafter referred to as C-■ conversion circuit), 7 is C-
(2) Voltage value from conversion circuit 6) This is an oscillator (hereinafter referred to as (2) CO) that oscillates at a corresponding frequency, and drives the CPU and others using the oscillation clock from VCO 7 as a system clock. Further, 8 is a timer circuit that generates a time serving as a reference for the pulse interval of the C--■ conversion circuit 6.

The system clock transmission control by the VCO 7 of the apparatus of this embodiment will be explained with reference to the flowchart of FIG.

First, in step 31, it is determined whether the CPU is currently performing key manual processing or other arithmetic processing, etc., and if it is other arithmetic processing, the process proceeds to step S2, where the CPU performs pulse C-V conversion at regular intervals. The C-■ conversion circuit 6 converts the timer output signal from the timer circuit 8 into a voltage corresponding to the pulses output at regular intervals, and converts it into a voltage corresponding to the pulses output at regular intervals.
Output to O7. The VCO 7 outputs an oscillation frequency proportional to this voltage to the CPU and others. Then, the process returns to step SL again.

In the case of key manual processing in step S1, unlike step S3, the CPU 1 stops outputting pulses at regular intervals,
A pulse of a constant width is output for each key input and the process returns to step Sl. Therefore, the output voltage of the C--■ conversion circuit 6 applied to the VCO 7 decreases, the VCO 7 oscillates at a low frequency oscillation frequency corresponding to the keystroke interval, and outputs this low frequency system clock to the CPUI.

For this reason, when the keystroke interval is long, the system clock for the CPUI becomes a low frequency, and the system CPU
The processing speed will be reduced and the power consumption will be greatly reduced.

FIG. 3 shows a pulse output timing chart for each key input.

In order to prevent the output voltage of the C-■ conversion circuit 6 from being too low if only the pulses output for each key input are output, the timer circuit 8 outputs the minimum necessary pulses, and the VCO 7
It is controlled so that the minimum frequency for normal operation of the PUI is output. When key manual processing is performed at high speed and high speed is required for key manual processing, the VCO 7 automatically outputs a system clock at a high frequency. -As explained above, by adjusting the CPU drive frequency according to the interval between key inputs, when the interval between key inputs becomes long and power consumption becomes long, the frequency can be lowered to reduce power consumption per hour. It can be suppressed. In addition, other arithmetic processing can be performed at t±the optimum processing speed of the device.

[Effects] As explained above, according to the present invention, an information processing device with low power consumption can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a control flowchart of the system clock of the device of this embodiment, and FIG. 3 is a pulse output timing chart when the key is manually operated. In the figure, 1...CPU, 2...Memory, 3...Display device, 4...Keyboard, 5...Printer, 6...
・C-■ conversion circuit, 7...VCO18...timer circuit.

Claims (2)

[Claims] (1) An information processing device characterized in that the processing speed is changed according to the interval between key inputs from a key input unit to reduce power consumption. (2) A patent characterized in that the processing speed is changed by changing the oscillation frequency of the system clock in accordance with the key human power interval and driving the device with a system clock that can change the oscillation frequency. An information processing device according to claim 1.