JPH10124200A - Portable information terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable power-controlling by a main CPU at the time of low-speed clock operation immediately before a system is suspended and immediately after resuming by executing power control by main CPU itself at the time of the low-speed clock operation of main CPU having the low-speed clock. SOLUTION: S/W in the system is operated at a high speed by DRAM 7. When no S/W which is operated occurs for more than fixed time, the system is shifted to a suspending state. In this case, S/W is jumped to ROM 5 so as toattain execution. Concerning a suspending processing, a stack is changed-over from DRAM 7 to SRAM 6, the power control of a peripheral device 8 is executed and CPU 9 is changed-over; into the low-speed clock. When a resuming main cause occurs here, the low-speed clock is supplied to CPU 9 by ASIC 4 and the resuming processing is started. The recovery state of a battery voltage is inspected to recognize whether or not the system is realy in the excellent state for starting in the resuming processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power supply control device used for a portable information terminal such as a pocket computer, an electronic organizer, and a PHS, and a control method thereof.

[0002]

2. Description of the Related Art In a conventional portable information terminal, control for realizing low power consumption is performed in order to extend battery life even a little. In particular, as a power supply control method, since thorough low power consumption cannot be realized only by control by the main CPU, an ASIC, a one-chip microcomputer, or the like is used as a means for capturing a part that cannot be supplemented by the S / W control of the main CPU. Was used.

[0003]

In a conventional portable information terminal, when an ASIC is used, it is difficult to make a fine control change.
There was a problem that the IC had to be revised and remounted.

When a one-chip microcomputer is used,
A portable information device or personal computer, which requires a mounting area for one chip microcomputer element and determines product value where portability is important, has a problem in that the size of the body is affected. Further, in the conventional CPU, if the clock frequency is lowered, the main CPU cannot operate and the program operation cannot be performed.

[0005]

Therefore, in the portable information terminal of the present invention, when the main CPU having the low-speed clock operates at the low-speed clock, the power control is performed by the main CPU itself. At the time of the next low-speed clock, the main CPU
The power supply can be controlled by the power supply.

Further, S / W for controlling the power is performed by executing a program written in the ROM. In addition, RO is executed by the second program written in the SRAM.
The power can be controlled by correcting the first program written in M.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the portable information terminal of the present invention, the S / W on the system is operated at high speed by a DRAM. If the S / W that operates for a certain period of time does not become active, the system is shifted to the suspend state. At this time, the S / W jumps to the ROM and executes it there. The suspend process is as follows: (1) The stack is switched from DRAM to SRAM. (2) Perform power control of peripheral devices. (3) Switch CPU to low-speed clock. (4) Stop clock.

When a resume factor occurs, H /
A low-speed clock is supplied to the CPU by W (ASIC), and resume processing is started. Here, the resume processing is performed as follows. (5) Check the battery voltage recovery state to see if it is OK to actually start the system. (6) If the above problem occurs, execute (4) to suspend again. (7) Power control of peripheral devices is performed. (8) Return the stack to the DRAM. (9) Jump to the DRAM and end the resume processing.

[0009]

Embodiments will be described with reference to the drawings.
In FIG. 1, an ASIC having a clock control unit 3 for controlling a clock by a low-speed clock 1 and a high-speed clock 2
4 and a ROM 5 on a CPU bus connected to the ASIC 4
, An SRAM 6, a DRAM 7, and a peripheral device 8, and connected to a CPU 9 that operates with a high-speed clock and a low-speed clock. Here, the SRAM 6 has a backup by a sub-battery.

[0010]

The present invention is embodied in a portable device as described above, and has the following effects. ASIC
By performing the power control at the time of the low-speed clock by the main CPU, detailed control can be programmed, and the maintenance performance is improved.

The number of gates decreases with the reduction in the function of the ASIC. Normally, the power supply control is often added or changed in function until the end of the development, and it is possible to cope with these without changing the hardware, which is extremely effective.

An area for mounting a one-chip microcomputer is not required, and it is easy to realize a notebook-sized portable information terminal.

[Brief description of the drawings]

FIG. 1 is a block diagram of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Low-speed clock 2 High-speed clock 3 Clock control part 4 ASIC 5 ROM 6 SRAM 7 DRAM 8 Peripheral device 9 CPU

Claims (5)

[Claims] 1. A CPU, a clock control unit (3) for switching between a low-speed clock (1) and a high-speed clock (2), a ROM (5) connected to a BUS of the CPU, and an SRA
A portable information terminal in which the M (6), the DRAM (7), and the clock control unit (3) are connected to the BUS of the CPU. 2. A means for switching a clock from a high-speed clock to a low-speed clock or from a low-speed clock to a high-speed clock; and a main CP operating at the low-speed clock to perform voltage control.
A portable information terminal having U (9). 3. A means for switching a clock from a high-speed clock to a low-speed clock when the power supply voltage drops, and a main CP which operates at the low-speed clock to perform voltage control.
A portable information terminal having U (9). 4. A portable information terminal having a main CPU (9) for controlling a power supply according to a program written in a ROM. 5. A portable information terminal having a main CPU (9) for controlling power supply according to a first program written in a ROM and a second program written in an SRAM.