CN1811663A - Power management method of north bridge - Google Patents
Power management method of north bridge Download PDFInfo
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- CN1811663A CN1811663A CN 200610007128 CN200610007128A CN1811663A CN 1811663 A CN1811663 A CN 1811663A CN 200610007128 CN200610007128 CN 200610007128 CN 200610007128 A CN200610007128 A CN 200610007128A CN 1811663 A CN1811663 A CN 1811663A
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Abstract
The present invention provides a power state management method of north bridge. The north bridge monitors power transition state of processor; then adjusting operating clocks and operating voltage of the processor and the main memory according to the determined power state to saving power consumption.
Description
Technical field
The invention relates to the power supply status management method, and be particularly to north bridge power supply status management method.
Background technology
Power management is the moving problem, particularly Yi Dongshi calculation element wanted of one on the Computer Design.Long battery life desired in the design needs positive power management.Some is in the unit of high clock frequency in the computer system, and for example central processing unit (central processing unit, be called for short CPU), primary memory (random access memory is called for short RAM) and chipset etc. are usually than other unit power consumption.These high clock operation unit make power management wherein play the part of suitable pivotal player.
ACPI (Advanced Configuration and Power Interface, abbreviation ACPI) specification 2.0 proposes many methods by leading configuration of operating system and power management (operating system-directed configuration and power management, be called for short OSPM) with the power supply status of transformation calculations machine, operating system and south bridge (south bridge) can be used computer installation at S0, S1, S2, S3, S4, the intercropping of S5 state is switched, and with processor at C0, C1, C2, C3 switches between C4 and other state.
Below introduce the processor power supply state C0～C3 and the system state S0～S5 of ACPI definition.
C0 processor power supply state: processor can execute instruction in this state.
C1 processor power supply state: have the shortest delay.Processor can the retention system high-speed memory As-Is (context).
C2 processor power supply state: this state is than the more power saving of C1 state.A default processor can keep the consistance of its high-speed memory and can monitor accessing operation to primary memory in this state.
C3 processor power supply state: this state is than C1 and the more power saving of C2 state.The high-speed memory of processor is kept its state, but this processor is not required to monitor the accessing operation of primary memory.(Operating System Power Management OSPM) determines that high-speed memory keeps consistance to the operating system power management.
S0 system state: S0 is a working state of system.Therefore processor is at C0, C1, C2, or C3 state.Equipment such as processor are kept its As-Is (context), and to execute instruction as the defined mode of these processor states.Processor keeps and reads and writes the As-Is of dynamic RAM (Dynamic RAM).
The S1 dormant state: the S1 state is to reply to postpone short sleep state.Equipment such as processor are kept its As-Is (context), but do not execute instruction.The As-Is of dynamic RAM (RAM) is retained.
The S2 dormant state: the S2 state is to postpone shorter dormant state turnaround time.S2 is than the power saving of S1 state.Equipment such as processor are not kept its As-Is (context), do not execute instruction yet.The As-Is of dynamic RAM is retained.The S2 dormant state is except the As-Is of equipment such as loss processor (operating system keeps the As-Is of high-speed memory and CPU), and all the other are similar to the S1 dormant state.
The S3 dormant state: the S3 dormant state is to postpone shorter D dormant state turnaround time.S3 is than the power saving of S2 state.Equipment such as processor are not kept its As-Is (context), do not execute instruction yet.The As-Is of dynamic RAM is retained.
The S4 dormant state: the S4 dormant state is the power saving that ACPI supports, but postpones the longest dormant state turnaround time.S4 is than the power saving of S3 state.In the S4 dormant state, processor does not execute instruction.Do not keep equipment As-Is such as dynamic RAM and processor.
S5 soft-off state: the S5 state is not except OSPM stores any current state, and is similar to the S4 state.When replying, need complete boot program in the computer system of S5 state.
The same operation that all can influence primary memory and chipset of processor power supply state with system state.Yet the electrical source consumption of primary memory and chipset along with the processor power supply state is done properly management, does not define in ACPI simultaneously yet in traditional computer system.
On the typical case, power state machine is built in the south bridge, yet the north bridge of tradition between CPU and primary memory can not be managed its power supply status.
Summary of the invention
The invention provides a kind of north bridge method for managing power supply.
Based on above-mentioned purpose, a kind of north bridge method for managing power supply of the present invention comprises:
The power supply status control signal of the power supply status conversion of above-mentioned processor is instructed in monitoring; According to above-mentioned power supply status control signal to determine above-mentioned processor will be transformed to which person in a plurality of power supply statuss; And according to by the above-mentioned power supply status that determined to adjust the corresponding work clock and the operating voltage of an above-mentioned processor and a primary memory.
In addition, the present invention also provides the north bridge with power supply status managerial ability.Above-mentioned north bridge comprises: flow monitor is monitored the power supply status control signal of above-mentioned processor; Power state machine according to above-mentioned power supply status control signal to determine above-mentioned processor will be transformed to which person in a plurality of power supply statuss; And power supply management control unit according to by the above-mentioned power supply status that determined to adjust the corresponding work clock and the operating voltage of an above-mentioned processor and a primary memory.
Description of drawings
Fig. 1 shows the structure calcspar according to the computer installation of the embodiment of the invention;
Fig. 2 A shows that each state reaches the wherein synoptic diagram of conversion in the bist state machine of demonstrating according to a north bridge of the embodiment of the invention;
C0 in the state machine of Fig. 2 B displayed map 2A, C0t, C1, C2, the C3 state reaches the wherein synoptic diagram of conversion;
Fig. 3 shows the power management process flow diagram performed according to the north bridge of the embodiment of the invention; And
Fig. 4 shows a power management operations form.
[label declaration]
1～processor; 2～primary memory; 3～north bridge; 4～south bridge; 5～clock generator; 6～voltage regulator; 7～voltage regulator; 8～drawing engine; 30～power supply management control unit; 35～clock source; 36～power state machine; 37～ACPI command decoder; 38～drawing engine; 39～flow monitor; 41～power state machine.
Embodiment
The present invention proposes a kind of power supply status management method of north bridge.
Fig. 1 shows the computer system 10 with north bridge power supply status management function of the present invention.
Computer system 10 comprises processor 1, primary memory 2, is connected in north bridge (the north bridge between processor 1 and the primary memory 2, be called for short NB) 3 and connect north bridge 3 south bridge (southbridge is called for short SB) 4, be connected the voltage regulator (voltageregulator) 7 between south bridge 4 and the primary memory 2 and be connected processor 1 and south bridge 4 between clock generator 5 and another voltage regulator 6.Those skilled in the art's known computer systems 10 can comprise other more multiprocessor.
In the present invention, the north bridge 3 with power supply status managerial ability comprises: flow monitor 39 according to the power supply status control signal to monitor the power supply status conversion of above-mentioned processor; ACPI command decoder 37 is in order to decode above-mentioned power supply status control signal; Power state machine 36 according to above-mentioned power supply status control signal to determine above-mentioned processor will be transformed to which person in a plurality of power supply statuss; And power supply management control unit 30 is according to work clock and the operating voltage of the above-mentioned power supply status that is determined with adjustment processor 1 and primary memory 2.
In the present invention, south bridge 4 also has power state machine 41, has ACPI system state all or part of in the power state machine 36 (system state) and processor state (processor state) in the power state machine 41.
Fig. 2 A is processor power supply constitutional diagram in the power state machine 36 of the present invention and 41.Wherein, C0 is processor working state (processor running state); C1 is pause command state (haltcommand state); C2 is processor second level state (processor level 2 state); C3 is processor third level state (processor level 3 state); C0t is C0 deceleration (throttle) state, and in this state, the work clock and the operating voltage of processor are lowered; And C3d is the C3 state of drawing engine when closing.
Fig. 2 B is the processor/system power supply constitutional diagram at north bridge.C0 is a processor working state; Cx is the processor state among Fig. 2 A; S1 is that the switch power supply unlatching suspends in primary memory state (power-onsuspend-to-RAM state); S3 is that power-off suspends in Disk State (power-offsuspend-to-disk state); S5 is power down state (power-off state).
Arrow in Fig. 2 A and Fig. 2 B is represented the possible state transformation of computer system 10.
Fig. 3 is the power management process flow diagram of north bridge 3 of the present invention.
At first, the power management control signal (step S100) of flow monitor 39 monitoring processors 1.Then, ACPI command decoder 37 is with above-mentioned power management control signal decode (step S200).Power state machine 36 will be converted into which person (step S300) of a plurality of states according to above-mentioned decoded power management control signal decision processor 1.At last, power supply management control unit 30 according to above-mentioned power state machine 36 and by the above-mentioned power supply status that determined to adjust the work clock and the operating voltage (step S400) of processor 1 and primary memory 2.
In the present invention, the work clock of processor 1 and operating voltage are adjusted with clock generator 5 and voltage regulator 6 respectively.The work clock of primary memory 2 and operating voltage are not adjusted with clock source 35 and voltage regulator 7.
Fig. 4 shows the power management operations form that the present invention proposes.Need be appreciated that the function in this form can start according to user's hobby or forbidden energy.According to above table, the work clock of processor 1 and primary memory 2 and operating voltage all along with conversion state extremely adjust.Above table is summed up the power supply status management of north bridge 3.The function of some this whole form can start according to user's hobby or forbidden energy.
In the C3 state, according to the standard of ACPI, processor 1 refusal monitoring is also ignored interruption.If there is not untreated state transformation in the north bridge 3, drawing engine is kept and is shown operation and accessing main memory 2, and order primary memory 2 enters self pattern (self-refresh mode).North bridge 3 and primary memory 2 all enter power down mode.
In the C3d state, if there is not untreated state transformation in the north bridge 3, drawing engine stops to show operation, enters D3 state (defining as the ACPI specification), and order primary memory 2 enters self pattern (self-refresh mode).At the C3d state, north bridge 3 is closed (shutdown), and forbidden energy phase-locked loop (Phase-locked loop is called for short PLL) wherein.
The present invention proposes a kind of power supply status management method of north bridge.Dynamically adjust work clock and operating voltage and can obtain preferable usefulness and the management of power supply consume preferably according to flow monitor at north bridge.Compared to the north bridge that does not have power state information, via utilizing above-mentioned built-in power state machine, north bridge can be managed the power supply of north bridge and storer more energetically.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (14)
1. a north bridge method for managing power supply is executed in north bridge, and the power supply status in order to processor in the managing computer system and primary memory comprises:
Monitor the power supply status conversion of above-mentioned processor; And
Utilize power state machine, according to work clock and the operating voltage of above-mentioned monitoring to adjust above-mentioned processor and above-mentioned primary memory.
2. north bridge method for managing power supply according to claim 1, wherein, the above-mentioned steps of monitoring power supply status conversion also comprises:
Monitor the power supply status control signal of above-mentioned processor;
Above-mentioned power supply status control signal is decoded to determine above-mentioned processor will be transformed to which person in a plurality of power supply statuss; And
According to the above-mentioned power state machine in above-mentioned north bridge to determine the corresponding work clock and the operating voltage of above-mentioned processor and above-mentioned primary memory.
3. north bridge method for managing power supply according to claim 1, wherein, above-mentioned a plurality of power supply statuss comprise C0t state, C1 state, C2 state, C3 state and S1 state.
4. north bridge method for managing power supply according to claim 3, wherein, when above-mentioned processor during at above-mentioned C0t state (deceleration regime), said method also comprises:
Reduce the work clock and the operating voltage of above-mentioned processor and above-mentioned primary memory; And
As do not detect any memory access operations, with a plurality of unlatching page or leaf pre-charge in the above-mentioned primary memory.
5. north bridge method for managing power supply according to claim 3, wherein, when above-mentioned processor during at above-mentioned S1 state, said method also comprises:
Stop the work clock of above-mentioned processor, and reduce the operating voltage of above-mentioned processor;
Order above-mentioned primary memory to enter the self pattern; And
Phase-locked loop forbidden energy with above-mentioned north bridge.
6. north bridge method for managing power supply according to claim 3, wherein, above-mentioned C3 state also comprises the C3d state, and drawing engine is closed in above-mentioned C3d state.
7. memory bridge, in order to the power supply status of managing computer system, wherein the aforementioned calculation machine also comprises processor and primary memory, comprises:
Flow monitor is in order to monitor the power supply status conversion of above-mentioned processor;
Power state machine, in order to according to above-mentioned monitoring to determine which power supply status above-mentioned processor will be transformed to; And
Power supply management control unit in order to according to above-mentioned power state machine and the above-mentioned power supply status that is determined, is adjusted the work clock and the operating voltage of above-mentioned processor and above-mentioned primary memory.
8. memory bridge according to claim 7 also comprises:
The Advanced Configuration and Power Interface demoder is in order to the power supply status control signal decoding of the power supply status conversion that will indicate above-mentioned processor.
9. memory bridge according to claim 7, wherein, above-mentioned power state machine comprises C0t state, C1 state, C2 state, C3 state and S1 state.
10. memory bridge according to claim 9, wherein, when above-mentioned processor during at above-mentioned C0t state (deceleration regime), above-mentioned power supply management control unit reduces the work clock and the operating voltage of above-mentioned processor and above-mentioned primary memory respectively, and above-mentioned primary memory is in the nonpageable pattern.
11. memory bridge according to claim 9, wherein, when above-mentioned processor during at above-mentioned C1 or C2 state, above-mentioned power supply management control unit reduces the work clock and the operating voltage of above-mentioned processor and above-mentioned primary memory respectively, and above-mentioned primary memory is in the nonpageable pattern.
12. memory bridge according to claim 9, wherein, when above-mentioned processor is in above-mentioned S1 state, above-mentioned power supply management control unit stops the work clock of above-mentioned processor, above-mentioned first voltage regulator reduces the operating voltage of above-mentioned processor, above-mentioned primary memory is in the self pattern, and the phase-locked loop of above-mentioned memory bridge is by forbidden energy.
13. memory bridge according to claim 9, wherein, above-mentioned C3 state also comprises the C3d state, and drawing engine is closed in above-mentioned C3d state.
14. memory bridge according to claim 7, wherein, above-mentioned memory bridge is a north bridge.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/215,222 | 2005-08-30 | ||
| US11/215,222 US7624286B2 (en) | 2005-02-01 | 2005-08-30 | Power management method of north bridge |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1811663A true CN1811663A (en) | 2006-08-02 |
| CN100552600C CN100552600C (en) | 2009-10-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100071286A Active CN100552600C (en) | 2005-08-30 | 2006-02-09 | North bridge electric power controller and method thereof |
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| CN (1) | CN100552600C (en) |
| TW (1) | TWI316657B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010102548A1 (en) * | 2009-03-09 | 2010-09-16 | 华为技术有限公司 | Single board energy-saving device, method thereof, and single board |
| TWI465917B (en) * | 2011-12-12 | 2014-12-21 | Via Tech Inc | Bridging device and energy saving method thereof |
| TWI514154B (en) * | 2011-12-12 | 2015-12-21 | Via Tech Inc | Bridging device and energy saving method thereof |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI448902B (en) * | 2007-08-24 | 2014-08-11 | Cypress Semiconductor Corp | Bridge device with page-access based processor interface |
| TWI395096B (en) * | 2009-05-12 | 2013-05-01 | Via Tech Inc | Power management method and related chipset and computer system |
| TWI601006B (en) * | 2011-10-31 | 2017-10-01 | 聯想企業解決方案（新加坡）有限公司 | Memory control system and computer system having the same |
| US9377844B2 (en) | 2011-10-31 | 2016-06-28 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Memory refresh rate throttling for saving idle power |
-
2005
- 2005-11-18 TW TW94140573A patent/TWI316657B/en active
-
2006
- 2006-02-09 CN CNB2006100071286A patent/CN100552600C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010102548A1 (en) * | 2009-03-09 | 2010-09-16 | 华为技术有限公司 | Single board energy-saving device, method thereof, and single board |
| CN101833365B (en) * | 2009-03-09 | 2011-09-14 | 华为技术有限公司 | Single board energy saving device, method and single board |
| US8456145B2 (en) | 2009-03-09 | 2013-06-04 | Huawei Technologies Co., Ltd. | Device and method for single board energy-saving and single board |
| TWI465917B (en) * | 2011-12-12 | 2014-12-21 | Via Tech Inc | Bridging device and energy saving method thereof |
| TWI514154B (en) * | 2011-12-12 | 2015-12-21 | Via Tech Inc | Bridging device and energy saving method thereof |
| US9477300B2 (en) | 2011-12-12 | 2016-10-25 | Via Technologies, Inc. | Bridging device and power saving method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200708926A (en) | 2007-03-01 |
| TWI316657B (en) | 2009-11-01 |
| CN100552600C (en) | 2009-10-21 |
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