1316657 98年7月29曰修正替換頁 九、發明說明： 【發明所屬之技術領域】 本發明係有關於電源狀態管理方法’且特別有關於北橋電源 狀態管理方法。 【先前技術】 電源管理是電腦設計上的一動要課題，特別是移動式的計算 裝置。设計上所期望的長電池壽命需要積極的電源管理。電腦系 ® 統中有些在高時脈頻率的單元，例如中央處理器（central processing unit ’ 簡稱 CPU)、主記憶體（rand〇m access memory，簡稱 ram)、 以及晶片組等，通常比其它單元耗電。這些高時脈操作單元使得 其中的電源管理扮演相當關鍵角色》 進階組態及能源介面（Advanced Configuration and Power Interface，簡稱ACI>I)規格2.0提出許多方法透過作業系統主導組 態及電源管理（operating system-directed configuration and power ® management ’簡稱OSPM)以變換電腦裝置的電源狀態，作業系統 及南橋(south bridge)能藉以將電腦裝置在SO, Sl，S2, S3, S4, S5狀 態間作切換，並且將處理器在CO, C1，C2, C3,C4及其它狀態間切 換。 以下介紹ACPI定義的處理器電源狀態C0-C3以及系統狀態 S0〜S5 ° C0處理器電源狀態：處理器在此狀態中可以執行指令。 » C1處理器電源狀態：具有最短的延遲。處理器可以保留系統 0608-A40317TWF1 5 1316657 98年7月29日修正替換頁 快取記憶體之目前狀況（context)。 C2處理器電源狀態：此狀態比ci狀態更省電。預設一處理 器可以在此狀態中保持其快取記憶體的一致性並且能夠監聽對主 記憶體的存取動作。 C3處理器電源狀態：此狀態比ci及C2狀態更省電。處理 器的快取記憶體維持其狀態，但是該處理器未被要求監聽主記憶 體的存取動作。作業系統電源管理（Operating System Power Management, OSPM)確定快取記憶體維持一致性。 SO系統狀態：SO是系統工作狀態。因此處理器在c〇，Cl，C2, 或C3狀態。處理器等設備維持其目前狀況（context)，並以如同這 些處理器狀態所定義的方式執行指令。處理器保留並讀寫動態隨 機存取記憶體(Dynamic RAM)的目前狀況。 S1休眠狀態：S1狀態是回復延遲較短的睡眠狀態。處理器等 設備維持其目前狀況(context) ’但是不執行指令。動態隨機存取記 憶體(RAM)的目前狀況被保留。 S2休眠狀態：S2狀態是回復時間延遲較短休眠狀態。S2比 si狀態省電。處理器等設備不維持其目前狀況（context)，也不執 行指令。動態隨機存取記憶體的目前狀況被保留❶S2休眠狀，離除 了遺失處理器等設備的目前狀況以外（作業系統保留快取記憤體 及CPU的目前狀況），其餘與S1休眠狀態相似。 S3休眠狀態：S3休眠狀態是回復時間延遲較短的休眠狀 6 0608-A40317TWF1 1316657 98年7月29日修正替換頁 態。S3比S2狀態省電。處理器等設備不維持其目前狀況(context)， 也不執行指令。動態隨機存取記憶體的目前狀況被保留。 S4休眠狀態：S4休眠狀態是ACPI所支援的最省電，但回 復時間延遲最長的休眠狀態。S4比S3狀態省電。在S4休眠狀態， . 處理器不執行指令。不保留動態隨機存取記憶體以及處理器等設 _ 備目前狀況。 S5軟關機狀態：S5狀態除了 OSPM不儲存任何目前狀態以 ^ 外，與S4狀態相似。在S5狀態的電腦系統在回復時，需要完整 的開機程序。 處理器電源狀態和系統狀態一樣都會影響主記憶體及晶片組 的作業。然而在傳統的電腦糸統中主記憶體及晶片組的電源消耗 並未隨著處理器電源狀態作妥善管理，同時也未在ACPI中作定 義。 典型上，電源狀態機被建在南橋内，然而，傳統介於CPU及 主記憶體之間的北橋不能管理其電源狀態。 【發明内容】 本發明提供一種北橋電源管理方法。 基於上述目的，本發明之一種北橋電源管理方法包含： 監測指導上述處理器之電源狀態變換的電源狀態控制信號； 根據上述電源狀態控制信號以決定上述處理器將被變換至複數電 源狀態中的哪一者；以及根據被決定之上述電源狀態.以調整上述 0608-A40317TWF1 7 98年7月29日修正替換頁 1316657 處理器及一主記憶體之對應工作時脈及工作電壓。 另外，本發明也提供具有電源狀態管理能力的北橋。上述北 橋包含：一流量監測器監測上述處理器之電源狀態控制信號；一 電源狀態機根據上述電源狀態控制信號以決定上述處理器將被變 換至複數電源狀態中的哪一者；以及一電源管理控制單元根據被 決定之上述電源狀態以調整上述處理器及一主記憶體之對應工作 時脈及工作電壓。 【實施方式】 本發明提出一種北橋的電源狀態管理方法。 第1圖顯示本發明之具有北橋電源狀態管理功能之電腦系統 10 ° 電腦系統10包含一處理器1、一主記憶體2、連接於處理器1 及主記憶體2之間的一北橋(north bridge，簡稱NB)3、以及連接 北橋3的一南橋(south bridge，簡稱SB)4、連接在南橋4與主記憶 體2之間的電壓調節器（voltage regulator)7、以及連接在處理器1 及南橋4之間的時脈產生器5及另一電壓調節器6。熟習此技藝者 已知電腦系統10可以包含其它更多處理器。 在本發明中，具有電源狀態管理能力的北橋3包含：一流量 監測器3 9根據電源狀態控制信號以監測上述處理器之電源狀態變 換；一 /lCPI命令解碼器37用以將上述電源狀態控制信號解碼； 一電源狀態機3 6根據上述電源狀態控制信號以決定上述處理器將 0608-A40317TWF1 8 1316657 98年7月29曰修正替換頁 被變換至複數電源狀態中的哪一者；以及一電源管理控制單元30 根據被決定之上述電源狀態以調整處理器1及主記憶體2之工作 時脈及工作電壓。 在本發明中，南橋4也具有一電源狀態機41，電源狀態機41 中具有電源狀態機36中全部或部分的ACPI系統狀態（system state) 及處理器狀態（processor state)。 第2A圖為本發明電源狀態機36及41中處理器電源狀態圖。 其中，C0為處理器工作狀態（processor running state ); C1為暫停 命令狀態（halt command state); C2為處理器第二級狀態(processor level 2 state) ; C3 為處理器第三級狀態（processor level 3 state); COt 為CO減速(throttle)狀態，在此狀態中，處理器的工作時脈及工作 電壓被降低；以及C3d是繪圖引擎關閉時的C3狀態。 第2B圖是在北橋的處理器/系統電源狀態圖。C0為處理器 工作狀態；Cx為第2A圖中的處理器狀態；S1為開電源開啟暫 停於主記憶體狀態（p〇wer-on suspend-to-RAM state) ; S3為電源關 閉暫停於磁碟狀態（power-off suspend-to-disk state) ; S5為電源關 閉狀態（power-off state)。 在第2A及2B圖中的箭頭代表電腦系統10可能的狀態變換。 第3圖是本發明之北橋3的電源管理流程圖。 首先’流量監測器39監測處理器1的電源管理控制信號（步 驟S100)。接著，ACPI命令解碼器37將上述電源管理控制信號解 0608-A40317TWF1 β9 1316657 Π—'—~— 98年7月29日修正替換頁 碼（步驟S200)。電源狀態機36根據上述被解喝的電源管理控制信 號決定處理器1將變換至複數狀態之哪一者（步驟S3〇〇)。最後， 電源管理控制單元30根據上述電源狀態機36及被決定之上述電 源狀態以調整處理器1及主記憶體2之工作時脈及工作電壓（步驟 S400)〇 在本發明中’處理器1之工作時脈及工作電壓分別以時脈產 生器5及電壓調節器6調整。主記憶體2之工作時脈及工作電壓 ® 別以時脈源35及電壓調節器7調整。 第4圖顯示本發明提出的電源管理動作表格。須要了解的是 此表格中的功能可以依據使用者之喜好來啟動或禁能。根據上述 表格，處理器1及主記憶體2之工作時脈及工作電壓皆隨著變換 所至的狀態來調整。上述表格總結北橋3的電源狀態管理。某些 這整個表格的功能可以依據使用者之喜好來啟動或禁能。 ^ 在C3狀態中，依據ACPI之標準，處理器1拒絕監聽並忽略 中斷。如果北橋3中沒有未處理的狀態變換，繪圖引擎維持顯示 作業並存取主記憶體2,並命令主記憶體2進入自我更新模式 (self-refresh mode)。北橋3及主記憶體2皆進入最省電狀態。 在C3d狀態中，如果北橋3中沒有未處理的狀態變換，繪圖 引擎停止顯示作業，進入D3狀態（如ACPI規格所定義），並命令 主記憶體2進入自我更新模式（self-refresh mode)。在C3d狀態， 北橋3關閉（shutdown)，並且禁能其中的鎖相迴路（Phase-locked 0608-A40317TWF1 10 1316657 98年7月29日修正替換頁 loop，簡稱 PLL)。 本發明提出一種北橋的電源狀態管理方法。動態調整工作時 脈及工作電壓可以根據在北橋的流量監測器獲得較佳的效能及較 好的電源耗損管理。相較於沒有電源狀態資訊的北橋，經由利用 . 上述内建的電源狀態機，北橋可以更積極地管理北橋及記憶體的 電源。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本 ® 發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當 可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請 專利範圍所界定者為準。 0608-A40317TWF1 11 1316657 98年7月29日修正替換頁 【圖式簡單說明】 第1圖顯示根據本發明實施例之一電腦裝置的結構方塊圖； 第2A圖顯示根據本發明實施例之一北橋示範的内建狀態機 中各狀態及其中變換的示意圖； 第2B圖顯示第2A圖的狀態機中CO, COt，Cl, C2, C3狀態及 其中變換的示意圖； 第3圖顯示根據本發明實施例之北橋所執行的電源管理流程 I圖；以及 第4圖顯示一電源管理動作表格。 【符號說明】 1〜處理器；2〜主記憶體；3~北橋；4〜南橋；5〜時脈產生器；6〜電 壓調節器；7〜電壓調節器；8〜繪圖引擎；30〜電源管理控制單元； 35〜時脈源；36〜電源狀態機；37〜ACPI命令解碼器；38〜繪圖引 擎；39〜流量監測器；41〜電源狀態機。 0608-A40317TWF1 121316657 July 29, 1998 Revision Correction Page IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a power state management method' and particularly to a Northbridge power state management method. [Prior Art] Power management is a major issue in computer design, especially for mobile computing devices. The long battery life expected in design requires aggressive power management. Some units in the high-frequency frequency of the computer system, such as the central processing unit (CPU), rand〇m access memory (ram), and chipset, are usually better than other units. Power consumption. These high-speed operation units make power management play a key role. Advanced Configuration and Power Interface (ACI>I) Specification 2.0 proposes many methods to dominate configuration and power management through the operating system ( Operating system-directed configuration and power ® management 'OSPM for short) to change the power state of the computer device, the operating system and the south bridge can switch the computer device between SO, Sl, S2, S3, S4, S5 states. And switch the processor between CO, C1, C2, C3, C4 and other states. The following describes ACPI-defined processor power states C0-C3 and system states S0~S5 ° C0 processor power state: The processor can execute instructions in this state. » C1 processor power state: has the shortest delay. The processor can retain the system 0608-A40317TWF1 5 1316657 July 29, 1998 Correction Replacement Page The current state of the cache memory. C2 processor power state: This state is more power efficient than the ci state. The preset one processor can maintain the consistency of its cache memory in this state and can monitor the access action to the main memory. C3 processor power state: This state is more power efficient than the ci and C2 states. The cache memory of the processor maintains its state, but the processor is not required to listen for access to the main memory. Operating System Power Management (OSPM) determines that cache memory maintains consistency. SO system status: SO is the system working state. So the processor is in the c〇, Cl, C2, or C3 state. Devices such as processors maintain their current context and execute instructions in a manner as defined by the state of these processors. The processor retains and reads the current state of dynamic random access memory (Dynamic RAM). S1 sleep state: The S1 state is a sleep state with a short response delay. Devices such as processors maintain their current state 'but do not execute instructions. The current state of dynamic random access memory (RAM) is preserved. S2 sleep state: The S2 state is a short sleep state with a reply time delay. S2 saves power compared to the si state. Devices such as processors do not maintain their current state of context and do not execute instructions. The current state of the DRAM is reserved for the S2 sleep state, except for the current state of the device such as the lost processor (the operating system retains the current state of the cache and the CPU), and the rest is similar to the S1 sleep state. S3 sleep state: S3 sleep state is a sleep state with a short response time delay. 6 0608-A40317TWF1 1316657 July 29, 1998 Corrected the replacement page. S3 saves power compared to the S2 state. Devices such as processors do not maintain their current context and do not execute instructions. The current state of DRAM is preserved. S4 sleep state: The S4 sleep state is the most power-saving supported by ACPI, but the recovery time has the longest sleep state. S4 saves power compared to the S3 state. In the S4 sleep state, the processor does not execute the instruction. The current state of the dynamic random access memory and the processor are not retained. S5 soft power off state: The S5 state is similar to the S4 state except that the OSPM does not store any current state with ^. When the computer system in the S5 state is replying, a complete booting procedure is required. The processor power state, like the system state, affects the operation of the main memory and the chipset. However, in traditional computer systems, the power consumption of the main memory and the chipset is not properly managed with the processor power state, nor is it defined in ACPI. Typically, the power state machine is built into the South Bridge, however, the traditional North Bridge between the CPU and the main memory cannot manage its power state. SUMMARY OF THE INVENTION The present invention provides a north bridge power management method. Based on the above object, a north bridge power management method of the present invention includes: monitoring a power state control signal that directs power state transition of the processor; and determining, according to the power state control signal, which of the plurality of power states the processor is to be converted to And adjusting the corresponding working clock and operating voltage of the processor and a main memory according to the above-mentioned power state determined by the above-mentioned 0608-A40317TWF1 7 July 29, 1998. In addition, the present invention also provides a North Bridge with power state management capabilities. The north bridge includes: a flow monitor monitoring a power state control signal of the processor; a power state machine determining, according to the power state control signal, which one of the plurality of power states the processor is to be converted; and a power management The control unit adjusts the corresponding working clock and operating voltage of the processor and a main memory according to the determined power state. [Embodiment] The present invention provides a power state management method for a north bridge. 1 shows a computer system 10 with a north bridge power state management function of the present invention. The computer system 10 includes a processor 1, a main memory 2, and a north bridge connected between the processor 1 and the main memory 2 (north). Bridge, referred to as NB) 3, and a south bridge (SB) 4 connected to the north bridge 3, a voltage regulator 7 connected between the south bridge 4 and the main memory 2, and connected to the processor 1 And a clock generator 5 between the south bridge 4 and another voltage regulator 6. It is known to those skilled in the art that computer system 10 can include many more processors. In the present invention, the north bridge 3 having the power state management capability includes: a flow monitor 39 for monitoring the power state transition of the processor according to the power state control signal; a /lCPI command decoder 37 for controlling the power state Signal decoding; a power state machine 36 according to the power state control signal to determine which of the plurality of power states the processor converts to 0608-A40317TWF1 8 1316657 July 29, 2007; and a power source The management control unit 30 adjusts the operating clock and operating voltage of the processor 1 and the main memory 2 in accordance with the determined power state. In the present invention, the south bridge 4 also has a power state machine 41 having all or part of the ACPI system state and processor state of the power state machine 36. Figure 2A is a diagram showing the state of the processor power supply in the power state machines 36 and 41 of the present invention. Where C0 is the processor running state; C1 is the halt command state; C2 is the processor level 2 state; C3 is the processor third level state (processor) Level 3 state); COt is the CO throttle state, in which the processor's operating clock and operating voltage are reduced; and C3d is the C3 state when the drawing engine is off. Figure 2B is a diagram of the processor/system power state at Northbridge. C0 is the operating state of the processor; Cx is the state of the processor in FIG. 2A; S1 is the power-on suspension in the main memory state (p〇wer-on suspend-to-RAM state); S3 is the power-off paused in the magnetic state Power-off suspend-to-disk state; S5 is the power-off state. The arrows in Figures 2A and 2B represent possible state transitions of computer system 10. Fig. 3 is a flow chart showing the power management of the north bridge 3 of the present invention. First, the flow monitor 39 monitors the power management control signal of the processor 1 (step S100). Next, the ACPI command decoder 37 corrects the above-mentioned power management control signal by 0608-A40317TWF1 β9 1316657 Π-'-~- July 29, 1998 correction page number (step S200). The power state machine 36 determines which of the plurality of states the processor 1 will switch to based on the above-described decommissioned power management control signal (step S3). Finally, the power management control unit 30 adjusts the operating clock and the operating voltage of the processor 1 and the main memory 2 according to the power state machine 36 and the determined power state (step S400). In the present invention, the processor 1 The working clock and operating voltage are adjusted by the clock generator 5 and the voltage regulator 6, respectively. The working clock and operating voltage of the main memory 2 are not adjusted by the clock source 35 and the voltage regulator 7. Fig. 4 shows a power management action table proposed by the present invention. It is important to understand that the functions in this form can be activated or disabled depending on the user's preference. According to the above table, the operating clock and operating voltage of the processor 1 and the main memory 2 are adjusted in accordance with the state of the transition. The above table summarizes the power state management of Northbridge 3. Some of the functions of this entire form can be activated or disabled depending on the user's preference. ^ In the C3 state, processor 1 refuses to listen and ignores interrupts according to ACPI standards. If there is no unprocessed state transition in Northbridge 3, the drawing engine maintains the display job and accesses the main memory 2, and commands the main memory 2 to enter the self-refresh mode. Both Northbridge 3 and Main Memory 2 enter the most power-saving state. In the C3d state, if there is no unprocessed state transition in Northbridge 3, the drawing engine stops displaying the job, enters the D3 state (as defined by the ACPI specification), and commands the main memory 2 to enter the self-refresh mode. In the C3d state, the north bridge 3 is shut down, and the phase-locked loop therein is disabled (Phase-locked 0608-A40317TWF1 10 1316657 July 29, 1998 revised replacement page loop, referred to as PLL). The invention provides a power state management method for a north bridge. Dynamic adjustment of the operating clock and operating voltage can be achieved based on the better performance and better power consumption management of the flow monitor at Northbridge. Compared to the North Bridge without power status information, the North Bridge can more actively manage the power of the North Bridge and memory via the built-in power state machine. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and it is to be understood that those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. 0608-A40317TWF1 11 1316657 Revised replacement page on July 29, 1998 [Simplified Schematic] FIG. 1 is a block diagram showing the structure of a computer device according to an embodiment of the present invention; FIG. 2A is a view showing a north bridge according to an embodiment of the present invention. Schematic diagram of each state in the built-in state machine and its transformation; Figure 2B shows a schematic diagram of CO, COt, Cl, C2, C3 states and their transformations in the state machine of Figure 2A; Figure 3 shows implementation in accordance with the present invention For example, the power management process I diagram executed by the North Bridge; and Figure 4 shows a power management action table. [Symbol description] 1~ processor; 2~ main memory; 3~ north bridge; 4~ south bridge; 5~ clock generator; 6~ voltage regulator; 7~ voltage regulator; 8~ drawing engine; Management control unit; 35~ clock source; 36~ power state machine; 37~ACPI command decoder; 38~ drawing engine; 39~ flow monitor; 41~ power state machine. 0608-A40317TWF1 12