JP2008243049A - Information processor and memory control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor reducing power consumption of a memory device according to an operation condition of a multiprocessor system and efficiently using a plurality of processors of the same configuration in the information processor. <P>SOLUTION: An EC/KBC 21 monitors the number of operating cores 11a-11b built in a CPU 11, and according to the number of operating cores 11a-11b, the main memory 13 is controlled for saving power consumption for each memory configuration unit of the main memory 13. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory control technique suitable for application to an information processing apparatus such as a personal computer equipped with a CPU having a plurality of instruction processing units (cores) called, for example, a multi-core CPU.

  In recent years, information processing apparatuses that can be driven by a battery and that are easy to carry, such as notebook personal computers, have become widespread. Recently, a wireless communication environment has been established, so if you carry this kind of information processing device, you can get the latest data and work while you are out or on the move. .

This type of information processing apparatus tends to have advanced functions expected to be installed, such as a function of receiving and viewing television program data that is scrambled and broadcast. In order to cope with this increase in functionality, this type of information processing apparatus is devised every day to improve its processing performance. For example, a multiprocessor system is capable of executing a variety of sophisticated processes in a short time by mounting a plurality of processors. On the other hand, this type of information processing device is premised on being used while away from home or moving, so how to ensure continuous operation time when battery is driven, that is, how to save power How to plan is a very important issue. For this reason, various proposals have been made to save power in a multiprocessor system (see, for example, Patent Document 1). The electronic computer disclosed in Patent Document 1 realizes a reduction in power consumption while suppressing the influence on processing performance by controlling the degree of parallelism in accordance with the power supply status, CPU load, and the like.
JP-A-9-138716

  By the way, in order to achieve further power saving with this type of information processing apparatus, it is also necessary to control the operation of the memory device which is the work area of the CPU. In power saving control in a memory device, it is common to start some kind of power saving operation when access is interrupted after a certain time. Therefore, in this conventional power saving control, even if, for example, in a multiprocessor system equipped with four CPUs, three CPUs are stopped and shifted to a power saving mode in which only one CPU operates, this 1 As long as access from one CPU continues, the memory device cannot start the power saving operation.

  Recently, a new type of CPU called a multi-core CPU having a plurality of instruction processing units (cores) has been developed. Thereby, a multiprocessor system can be realized by one CPU. In this case, for example, even if a transition is made to the power saving mode in which only one of the four cores is operated, the multi-core CPU that is one chip in hardware appears to be always in operation from the outside. Therefore, especially for a memory device accessed from a multi-core CPU, a new operation control method for power saving is strongly desired.

  The present invention has been made in view of such circumstances, and provides an information processing apparatus and a memory control method that can reduce the power consumption of a memory device in accordance with the operating status of a multiprocessor system. With the goal.

  In order to achieve this object, an information processing apparatus according to the present invention includes a CPU having a plurality of instruction processing units, a memory device including a plurality of memory constituent units, and an operation of the plurality of instruction processing units on the CPU. And memory control means for executing operation control of the memory device for each of the plurality of memory constitutional units according to the number.

  The memory control method of the present invention is a memory control method for an information processing apparatus including a CPU having a plurality of instruction processing units and a memory device composed of a plurality of memory structural units. The operation control of the memory device is executed for each of the plurality of memory configuration units in accordance with the number of operations of the plurality of instruction processing units.

  According to the present invention, it is possible to provide an information processing apparatus and a memory control method that can reduce the power consumption of a memory device in accordance with the operating status of a multiprocessor system.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a hardware configuration example of the information processing apparatus according to the present embodiment. This information processing apparatus is realized as, for example, a notebook-type personal computer 1 that can be battery-driven and easily carried.

  As shown in FIG. 1, the computer 1 includes a CPU 11 having four instruction processing units (execution cores) including a core (1) 11a, a core (2) 11b, a core (3) 11c, and a core (4) 11d. This is a multi-core CPU mounted system to be mounted. Note that the memory control method of the present invention described in the present embodiment is not limited to a dual-core CPU-equipped system equipped with a so-called dual-core CPU that incorporates two execution cores. The present invention is also applicable to a multi-core CPU mounting system in which a type of CPU is mounted.

  As shown in FIG. 1, the computer 1 includes the CPU 11, the host controller 12, the main memory 13, the display controller 14, the display device 15, the display memory 16, the I / O controller 17, and the storage device 18. , A power controller 19, a clock generator 20, an embedded controller / keyboard controller (EC / KBC) 21, a keyboard 22 and the like.

  The CPU 11 is a processor for integratedly managing and controlling the operations of each unit in the computer 1, and operates under the control of the operating system (OS) loaded from the storage device 18 to the main memory 13 and this OS. Execute various application programs including utilities. The various application programs include a memory management utility program 101 described later. Various application programs including the OS and the memory management utility program 101 are installed in the storage device 18 in advance.

  The host controller 12 is a bridge device that connects the local bus of the CPU 11 and the I / O controller 17. The host controller 12 has a function of executing communication with the display controller 14 via a bus, and also includes a memory controller that controls access to the main memory 13.

  The display controller 14 controls a display device 15 used as a display monitor of the computer 1. A display memory 16 is connected to the display controller 14, and a display signal to be sent to the display device 15 is generated from image data written in the display memory 16 by the OS or various application programs.

  The I / O controller 17 includes a controller for controlling the storage device 18. The I / O controller 17 also controls the power supply controller 19, the clock generator 20, and the EC / KBC 21.

  The power controller 19 controls the operation power of the CPU 11 and the main memory 13. The clock generator 20 controls supply of operation clocks for the CPU 11 and the main memory 13. The operation power supply control by the power supply controller 19 and the operation clock supply control by the clock generator 20 are performed by operation commands output from the I / O controller 17.

  The EC / KBC 21 is a one-chip microcomputer in which a built-in controller for power management that controls supply of power from a battery or an external AC power source to each unit and a keyboard controller for controlling the keyboard 22 are integrated. With this EC / KBC 21, the computer 1 executes operation control of the main memory 13 in accordance with the operation status of the CPU 11. Hereinafter, this point will be described in detail.

  FIG. 2 is a diagram showing the configuration of the main memory 13 installed in the computer 1 and the host controller 12 that controls access to the main memory 13. In the computer 1, memory management is executed by the virtual memory method using the main memory 13 and the storage device 18 by a function of the OS.

  As shown in FIG. 2, the main memory 13 is composed of four memory constituent units: a memory unit (A) 13a, a memory unit (B) 13b, a memory unit (C) 13c, and a memory unit (D) 13d. Each of the memory units 13a to 13d is accessed in units of 8 bytes, and each of the memory units 13a to 13d has either a power-on state or a power-off state under the control of the host controller 12, and In the power-on state, the state further includes either a state where a normal clock is supplied or a state where a slowed clock is supplied. Here, the former is referred to as a normal operation state, and the latter is referred to as a power saving operation state. If an access to the memory unit in the power saving operation state occurs, the host controller 12 returns the clock of the memory unit to the normal speed (that is, once returns to the normal operation state), and after the access is completed. If access to the memory unit is interrupted after a certain time, the clock is slowed down again. Even if the access to the memory unit in the normal operation state is interrupted for a certain time from the beginning, the host controller 12 does not reduce the clock of the memory unit.

  On the other hand, when the CPU 11 requests data writing or data reading, the host controller 12 controls which memory unit is accessed to process the data writing or data reading in units of 16 bytes. . The host controller 12 can independently access the memory unit (A) 13a or the memory unit (C) 13c and the memory unit (B) 13b or the memory unit (D) 13d. For example, the memory unit (A) 13a and the memory unit (B) 13b can be accessed simultaneously.

  In addition, the host controller 12 controls the state of each of the memory units 13a to 13d individually so as to shift between the normal operation state and the power saving state, and the memory unit (A) 13a, the memory unit (C) 13c, or the memory Control is performed to turn on and off the power in two systems of the unit (B) 13b and the memory unit (D) 13d. That is, the host controller 12 sends an instruction to the I / O controller 17 for inputting an operation command to the power supply controller 19 according to the memory unit (A) 13a, the memory unit (C) 13c or the memory unit (B) 13b, An instruction to the I / O controller 17 for inputting an operation command to the clock generator 20 can be made in units of the unit (D) 13d in individual units for each of the memory units 13a to 13d.

  Further, the host controller 12 arranges the main memory space on each of the memory units 13a to 13d (although as described above, memory management is performed in the virtual storage system in the computer 1). Can be controlled. For this purpose, the host controller 12 has a main memory space arrangement control unit 121.

  For the main memory 13 having such a configuration, the EC / KBC 21 executes the following control according to the number of operating cores 11a to 11d on the CPU 11. The memory management utility program 101 is software that provides an interface for the user to arbitrarily set the contents of memory control to be executed in correspondence with the number of operating cores 11a to 11d. Held in the KBC 21. That is, the control content described below is an example based on setting information at a certain point in time, and the memory control method of the present invention is not limited to this.

  Note that the number of operating cores 11a to 11d is separately controlled according to, for example, the remaining battery level when the battery is driven, the load on the CPU 11, and the like, and the control result is notified to the EC / KBC 21. ing.

(1) When the number of active cores is 4 or 3 When the number of active cores is 4 or 3, the EC / KBC 21 sets all the memory units 13a to 13d to the power-on state and the normal operation state. An instruction is given to the host controller 12. At this time, the EC / KBC 21 gives an instruction to the host controller 12 so that the main memory space is arranged as shown in FIG. That is, it is instructed to allocate the memory units 13a to 13d evenly in units of 128 bytes.

  Then, the host controller 12 writes data to or reads data from the main memory 13 in units of 16 bytes in units of the memory unit (A) 13a and the memory unit (B) 13b or the memory unit (C) 13c and the memory unit. (D) Access and process 13d simultaneously.

(2) When the number of operating cores is 2 When the number of operating cores is 2, the EC / KBC 21 sets the power on state and the normal operating state for the memory unit (A) 13a and the memory unit (B) 13b, In addition, for the memory unit (C) 13c and the memory unit (D) 13d, an instruction is given to the host controller 12 to set the power-on state and the power-saving operation state. At this time, the EC / KBC 21 instructs the host controller 12 so that the main memory space is arranged as shown in FIG. That is, the memory unit (A) 13a, the memory unit (B) 13b, the memory unit (C) 13c, and the memory unit (D) 13d are divided into the normal operation state. (B) It is instructed to preferentially assign 13b. More specifically, when a real memory area is newly allocated to the main memory space, the real memory area is secured with priority from the memory unit (A) 13a and the memory unit (B) 13b.

  Then, the host controller 12 writes data to or reads data from the main memory 13 in units of 16 bytes in units of the memory unit (A) 13a and the memory unit (B) 13b or the memory unit (C) 13c and the memory unit. Access and process (D) simultaneously.

(3) When the number of active cores becomes 1 When the number of active cores becomes 1, the EC / KBC 21 determines the allocation destination of the real memory area allocated to the main memory space as the memory unit (A) 13a, the memory unit (B ) 13b only, the main memory space gives an instruction to the host controller 12 as shown in FIG. That is, it is divided into the memory unit (A) 13a and the memory unit (C), and the memory unit (A) 13a is assigned with priority.

  When the host controller 12 receives this instruction, the memory unit (A) 13a and the memory unit (C) are entered in the main memory space to which the real memory areas of the memory unit (B) 13b and the memory unit (D) are allocated. ) When performing reallocation to reallocate the real memory area of 13c and newly allocating the real memory area to the main memory space, the memory unit (A) 13a is preferentially assigned to the memory unit (A) 13a, Secured only from the memory unit (C) 13b.

  At this time, the EC / KBC 21 sets the host so that the memory unit (A) 13a is in the power-on state and the normal operation state, and the memory unit (C) 13c is in the power-on state and the power-saving operation state. An instruction is given to the controller 12. Further, the EC / KBC 21 instructs the host controller 12 to turn off the unused memory unit (B) 13b and memory unit (D) 13d.

  Then, the host controller 12 processes the data writing to the main memory 13 and the data reading by accessing the memory unit (A) 13a or the memory unit (C) independently in units of 8 bytes twice.

  As described above, in the computer 1, operation control of the main memory 13 for power saving is appropriately executed according to the number of operating cores 11 a to 11 d on the CPU 11.

  FIG. 4 is a flowchart showing a memory control procedure according to the number of core operations of the multi-core CPU executed by the computer 1.

  When the number of operating cores 11a to 11d on the CPU 11 reaches 3 or 4 (YES in step A1), the EC / KBC 21 first sets all the memory units 13a to 13d of the main memory 13 to the power-on state and the normal operation state. An instruction is given to the host controller 12 to set (step A2). Then, the EC / KBC 21 gives an instruction to the host controller 12 so that the main memory space is evenly arranged in the memory units 13a to 13d (step A3).

  Further, when the number of operating cores 11a to 11d on the CPU 11 becomes 2 (NO in step A1, YES in step A4), the EC / KBC 21 stores the memory unit (A) 13a and the memory unit (B) of the main memory 13. 13b is set to the power-on state and the normal operation state, while the memory controller (C) 13c and the memory unit (D) 13d are instructed to set the power-on state and the power-saving state to the host controller 12 (step A5, step A6). Then, the EC / KBC 21 gives an instruction to the host controller 12 so that the main memory space is preferentially arranged in the memory unit (A) 13a and the memory unit (B) 13b (step A7).

  Further, when the operating number of the cores 11a to 11d on the CPU 11 becomes 1 (NO in step A4, YES in step A8), the EC / KBC 21 is in a state in which the memory unit (A) 13a of the main memory 13 is in the power-on state. In the operation state, the memory unit (C) 13c gives an instruction to the host controller 12 to set the power on state and the power saving state (step A10, step A11). At this time, the EC / KBC 21 instructs the host controller 12 to set the memory unit (B) 13b and the memory unit (D) 13d to the power-off state (step A11). Then, the EC / KBC 21 gives an instruction to the host controller 12 so that the main memory space is preferentially arranged in the memory unit (A) 13a (step A12).

  As described above, according to the computer 1, it is possible to reduce the power consumption of the memory device in accordance with the operation status of the multiprocessor system.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

The figure which shows the hardware structural example of the information processing apparatus (personal computer) which concerns on one Embodiment of this invention 2 is a diagram illustrating a configuration of a main memory installed in the computer of the embodiment and a host controller that controls access to the main memory. FIG. The figure for demonstrating the allocation principle of the main memory space in the computer of the embodiment The flowchart which shows the procedure of the memory control according to the number of core operation | movement of the multi-core CPU performed with the computer of the embodiment

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Information processing apparatus (computer), 11 ... CPU, 11a-11d ... Core, 12 ... Host controller, 13 ... Main memory, 13a-13d ... Memory unit, 14 ... Display controller, 15 ... Display device, 16 ... For display Memory, 17 ... I / O controller, 18 ... Storage device, 19 ... Power controller, 20 ... Clock generator, 21 ... Embedded controller / keyboard controller (EC / KBC), 22 ... Keyboard, 101 ... Memory management utility program, 121 ... Main memory space allocation control unit.

Claims (7)

A CPU having a plurality of instruction processing units;
A memory device comprising a plurality of memory building units;
Memory control means for performing operation control of the memory device for each of the plurality of memory configuration units according to the number of operations of the plurality of instruction processing units on the CPU;
An information processing apparatus comprising:   2. The apparatus according to claim 1, further comprising setting means for setting operation control contents of the memory device to be executed by the memory control means in accordance with the number of operating the plurality of instruction processing units on the CPU. Information processing device. Power supply means for executing power supply control for operating the memory device for each of the plurality of memory configuration units;
The information processing apparatus according to claim 1, wherein the memory control unit powers on or off each of the plurality of memory structural units via the power supply unit. A clock supply means for executing operation clock supply control for the memory device for each of the plurality of memory constituent units;
2. The information processing apparatus according to claim 1, wherein the memory control unit switches a clock frequency of each of the plurality of memory structural units via the clock supply unit.   4. The information processing apparatus according to claim 3, further comprising means for rearranging data on a memory structural unit to be powered off to another memory structural unit in which a power-on state is maintained.   5. The information processing apparatus according to claim 4, further comprising means for controlling the data to be arranged with priority given to a memory unit that operates with a normal clock over a memory unit with a reduced clock speed. A memory control method for an information processing apparatus including a CPU having a plurality of instruction processing units and a memory device composed of a plurality of memory constituent units,
The operation control of the memory device is executed for each of the plurality of memory configuration units according to the number of operations of the plurality of instruction processing units on the CPU.
And a memory control method.

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