JP2003337634A - Computer apparatus, method for controlling processor, program for running the method by computer, computer- readable recording medium with the program recorded thereon - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve power savings, without having to need extra hardware for a computer system with a CPU, of which the clock frequency can be controlled. <P>SOLUTION: A computer apparatus has a timer 5 capable of setting an arbitrary time, sets the timer 5 when an OS (operating system) starts up an interrupt handler 2, makes a CPU 1 change the clock frequency to be higher and quickly execute response processing from the start up of the handler 2, and makes the CPU 1 lower the clock frequency, when the timer 5 has expired. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operating system (hereinafter referred to as OS) operating on a computer system having a central processing unit (hereinafter referred to as CPU) whose clock frequency is controllable. The present invention relates to a technique for controlling power consumption by controlling a frequency.

[0002]

2. Description of the Related Art In various computer systems, it is necessary to reduce the amount of increase in carbon dioxide (CO2) in recent years by increasing the battery life, reducing power consumption, and performing power saving control that suppresses temperature rise due to heat generation. This is one of the important functions of the OS and application programs in response to requests from global environmental issues such as reduction of energy consumption and energy consumption. Here, there are the following conventional power saving methods.

As a conventional power saving system, FIG. 5 is a block diagram showing the configuration of an electronic device provided with a power saving system in the "low power consumption system for electronic devices" described in JP 2000-39930 A, for example. . As shown in FIG. 5, the electronic device is composed of a C-MOS and operates with a system clock, a CPU unit 501, a program memory unit 502 in which a program to be executed is stored, and between the program memory unit 502 and the CPU unit 501. A monitor circuit unit 503 that monitors the address, determines the type of the program currently being executed, and calculates the required processing capacity;
VCXO that determines the clock speed provided to the U unit 501
A clock speed control unit 505 including a circuit 504 is included.

The operation of the electronic device configured as described above will be described below. The program that works is
It is classified into a waiting function part and an event function part. The wait function is a program that can execute an operation regardless of time, and the event function is a program that is started by an interrupt process and needs to end the process in real time.

When these operations coexist,
The CPU unit 501 accesses the program memory unit 502, and the monitor circuit unit 503 determines from the access address whether the currently operating process is a standby function or an event function, and the standby function If so, the operation processing speed is decreased, or if it is an event function, the operation processing speed is increased. By performing conversion on the execution program, the processing speed required for the CPU unit 501 is calculated. As a result, the determined voltage value is output to the VCXO circuit 504 which is the clock transmission source, and the CPU section 50
1 determines the clock frequency speed at which it operates.

By this operation, the CPU section 501 can always operate at the minimum clock frequency, and the power consumption is reduced. In other words, in the conventional method, a clock control circuit unit that determines the type of program being processed by the CPU and provides an optimum clock is provided, and the clock speed is reduced when the software load is low, such as interrupt processing. If you need to react in real time, increase the clock speed and adjust the processing capacity
Since the PU operates with the minimum processing capacity required by software, it is possible to reduce the power consumption in the electronic device.

[0007]

However, such a conventional method requires special hardware for monitoring the addresses between the program memories and between the CPUs to judge the type of the program being executed. Therefore, there is usually a problem that an electronic device having such a power saving function cannot be easily realized.

The present invention has been made in order to solve the above-mentioned problems, and is provided with a timer capable of setting an arbitrary time, and for example, a human causes an interrupt event such as a key input to cause a reaction of a computer system. In order not to make it feel slow, the operating system sets the timer at the time of starting the key input interrupt handler and changes the clock frequency to a high value for the CPU so that the response process after the interrupt handler is started is executed quickly. In addition, by changing the clock frequency to a lower value for the CPU when the timer expires, the clock frequency is changed only during the period when the computer system must respond at high speed after an interrupt event is generated, without requiring special hardware. Increase the frequency and decrease the clock frequency during other periods. Aims to improve the power saving of the entire computer system.

[0009]

A computer device according to the present invention is a computer device provided with a processor device operable by an operation clock of any one of a plurality of clock frequencies, While detecting the occurrence of an interrupt event, when the specific interrupt event occurs, a clock frequency higher than the clock frequency before the occurrence of the specific interrupt event for a predetermined time from the occurrence of the specific interrupt event. The processor device is operated with an operating clock, and after a lapse of a predetermined time from the occurrence of the specific interrupt event, an operating clock having a clock frequency lower than a clock frequency during a predetermined time from the occurrence of the specific interrupt event. It is characterized in that the processor device is operated.

The computer device detects the occurrence of the specific interrupt event and, when the specific interrupt event occurs, generates the specific interrupt event for a predetermined time from the occurrence of the specific interrupt event. The processor device is operated with an operating clock having a higher clock frequency than the previous clock frequency, and after a lapse of a predetermined time from the occurrence of the specific interrupt event, a clock frequency during a predetermined time from the occurrence of the specific interrupt event. It is characterized by having an operating system for operating the processor device with an operating clock having a lower clock frequency.

The computer device sets a time for keeping the clock frequency of the operating clock of the processor device high as a high clock operation time, and when the specific interrupt event occurs, the specific interrupt event is generated. During the high clock operation time, the processor device is operated with an operation clock having a clock frequency higher than the clock frequency before the occurrence of the specific interrupt event.

The computer device, in a predetermined case,
The high clock operating time is changed.

A processor control method according to the present invention is a processor control method for controlling a processor device operable by an operation clock of any one of a plurality of clock frequencies, in which a specific interrupt event occurs. When the specific interrupt event occurs, the operating clock having a higher clock frequency than the clock frequency before the specific interrupt event occurs for a predetermined time from the occurrence of the specific interrupt event. The processor device is operated, and after a lapse of a predetermined time from the occurrence of the specific interrupt event, the processor device is operated with an operation clock having a clock frequency lower than a clock frequency during a predetermined time from the occurrence of the specific interrupt event. It is characterized by operating.

A program for causing a computer to execute the processor control method according to the present invention is used in a computer equipped with a processor device that can operate with an operation clock having any one of a plurality of clock frequencies. Is a program for executing a processor control method for controlling the occurrence of a specific interrupt event, and when the specific interrupt event occurs, a predetermined time from the occurrence of the specific interrupt event. Generating the specific interrupt event after a lapse of a predetermined time from the generation of the specific interrupt event by operating the processor device with an operating clock having a clock frequency higher than the clock frequency before the generation of the specific interrupt event. From the specified time Characterized in that at the operating clock of a clock frequency lower than the clock frequency is a program for executing the processor control method for operating the processor device to the computer.

A computer-readable recording medium in which a program for causing a computer to execute the processor control method according to the present invention is recorded is a processor operable with an operation clock having any one of a plurality of clock frequencies. A computer-readable recording medium recording a program for causing a computer including a device to execute a processor control method for controlling the processor device, wherein the occurrence of a specific interrupt event is detected and the specific interrupt event is detected. Occurs, the processor device is operated with an operating clock having a clock frequency higher than the clock frequency before the occurrence of the specific interrupt event for a predetermined time from the occurrence of the specific interrupt event, and Interrupt event After the passage from the door of the occurrence of a predetermined time,
A computer-readable record recording a program for causing a computer to execute a processor control method for operating the processor device at an operation clock having a clock frequency lower than a clock frequency for a predetermined time from the occurrence of the specific interrupt event. It is a medium.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. Figure 1
FIG. 1 is a configuration diagram of a computer system (computer device) according to Embodiment 1 of the present invention. 1 in FIG.
Is a CPU (processor device) having an interface capable of changing the clock frequency. An interrupt handler 2 is an execution unit of interrupt processing. Reference numeral 3 is a task which is an execution unit of the application. An OS 4 manages the operations of the interrupt handler 2 and the task 3. 5
Is a timer that can set an arbitrary time, generates an interrupt when the set time expires, and notifies the OS 4 of the interrupt. Reference numeral 6 is a keyboard for generating an interrupt when a key is input and notifying the OS 4. Reference numeral 7 denotes an entire computer system (computer device). Here, the OS 4 in FIG. 1 is a program executed on a computer, can be recorded in a computer-readable storage medium, and can also be transferred via a communication network.

In the present embodiment, for convenience, one interrupt handler 2 and two task 3 (task A and task B) are used.
However, it is possible to extend so that there are as many as possible. Further, for convenience, the clock frequency of the CPU 1 is changed in two stages, a high state and a low state, but the clock frequency can be finely changed. Further, for the sake of convenience, the interrupt handler 2 operates on the extension of the processing of the OS 4, but it may have an individual execution unit such as the task 3 of the application as in the present embodiment.

Next, the operation will be described with reference to the flowchart of FIG. When a key input is performed on the keyboard 6 of FIG. 1, the OS 4 executes step 201 of FIG.
The CPU 1 recognizes that an interrupt event has occurred.
Next, in step 202, it is determined whether or not the corresponding interrupt is the power saving control timer 5 set by the OS 4, and when the corresponding interrupt is not the power saving control timer 5 set by the OS 4, in step 203. The clock frequency of the CPU 1 is set higher than that before the occurrence of the interrupt event. Next, at step 204, a timer 5 for power saving control that performs an expiration at an arbitrary time is set. In addition, timer 5
The timer value set to is equivalent to the high clock operating time.
Then, the process proceeds to step 205 and the corresponding interrupt handler 2 determined in step 202 is executed. Next, in step 206, the task 3 of the application is rescheduled, and in step 207, the interrupt processing is completed, so that the interrupt disabled state is released. Next, in step 208, task 3 of the application suitable for execution by the rescheduling in step 206 is executed, and the process returns to the process of recognizing occurrence of the next interrupt in step 201.

Here, task 3 of the application is
It has a priority value that is a judgment that execution is prioritized, and can take an execution state, an executable state, a stop state, and an end state. These state transitions are task 3 itself, interrupt handler 2, and OS 4 , The actual state transition of the task 3 is performed by the scheduling process of the OS 4. For example, when the task A with the low priority shown in FIG. 1 is in the running state and the task B with the high priority is in the stopped state, if the state of the task B is designated as the ready state by the interrupt handler 2, the scheduling of the OS 4 thereafter is performed. As a result, the task A becomes the executable state and the task B becomes the executable state.

Further, the CPU 1 is automatically set to the interrupt disabled state when an interrupt occurs, and the cancellation of the interrupt disabled state must be explicitly performed by software such as the OS 4 at the end of the interrupt processing. Furthermore, CP
U1 is assumed to have a register that identifies an interrupt factor that can be referred to by software such as the OS4, but the computer system 7 has an interrupt control unit (IC).
Even if the dedicated hardware of U) is provided, the interrupt generated from the software can be specified in the same manner.

On the other hand, when the corresponding interrupt is the power saving timer 5 set by the OS 4 in step 202, the clock frequency of the CPU 1 is set lower than that in step 209 and the interrupt of step 207 is set. Proceed to the process for canceling the prohibited state.

As described above, according to the computer system according to the first embodiment, the timer 5 that can set an arbitrary time is provided, the OS 4 sets the timer 5 when the interrupt handler 2 is activated, and the CPU 1 On the other hand, by changing the clock frequency to a higher value, the response processing after starting the interrupt handler 2 is executed faster, and by changing the clock frequency to the CPU 1 when the timer 5 is expired, no special hardware is required. , The clock frequency is increased only during the period when the computer system 7 must respond to the processing at high speed after the interrupt event occurs, and the clock frequency is reduced during the period other than that, thereby improving the power saving of the entire computer system 7. Can be made.

Embodiment 2. Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a configuration diagram of a computer system according to the second embodiment of the present invention. In the present embodiment, task 3 of the first embodiment
A timer time holding unit 11 for holding the time set in the timer 5, which can be accessed for setting and reference from the software of the OS 4 or the OS 4. In the drawings, the same reference numerals indicate the same constituent elements.

Next, the operation will be described with reference to the flowchart of FIG. When a key input is made on the keyboard 6 of FIG. 3, the OS 4 executes step 30 of FIG.
At 1, the CPU 1 recognizes the occurrence of an interrupt event. Then in step 302, the corresponding interrupt is OS4.
It is determined whether or not the timer 5 for power saving control set by is set. If the corresponding interrupt is not the timer 5 for power saving control set by the OS 4, at step 303, the clock frequency of the CPU 1 is set before the occurrence of the interrupt event. Also set high. Next, in step 304, the timer time holding unit 1
1, the time for keeping the clock frequency of the CPU 1 high (high clock operating time) is acquired, and step 30
Set the timer 5 for power saving control that expires at the time acquired in 5. Then, in step 306, the corresponding interrupt handler 2 determined in step 302 is executed. Next, in step 307, the task 3 of the application is rescheduled and the task 3 suitable for the next execution is selected. In step 308, the interrupt disabled state is released when the interrupt processing is completed. Next, in step 309, task 3 of the application suitable for execution by rescheduling is executed, and the process returns to the process of recognizing the occurrence of the next interrupt in step 301.

On the other hand, when the corresponding interrupt is the power saving control timer 5 set by the OS 4 in step 302, the clock frequency of the CPU 1 is set lower in step 310 and the interrupt of step 308 is set. Proceed to the process for canceling the prohibited state.

As described above, according to the computer system according to the second embodiment, the timer 5 which can access the setting and the reference from the software of the task 3 and the OS 4 is used.
Since the timer time holding unit 11 for holding the time set to is provided and the OS 4 sets the timer 5 by referring to the timer time holding unit 11 when the interrupt handler 2 is activated, the interrupt event occurs. After that, the power saving control is performed from the software according to the situation, for example, by increasing the period during which the computer system 7 has to respond to the processing at high speed in a situation where the load is heavy such as multimedia playback and the processing is long. It is possible to dynamically adjust the period for which power is applied, and it is possible to realize effective power saving control.

In the above-described first and second embodiments, the computer system which is an example of the computer device according to the present invention has been described. However, the processor control method according to the present invention according to the operation procedure shown in the first and second embodiments, Also, a program for causing a computer to execute the processor control method can be realized. Further, the program for causing the computer to execute the processor control method can be recorded in a computer-readable recording medium.

The characteristics of the computer system shown in the first and second embodiments will be restated below. The computer system according to the first embodiment is a computer system that executes a predetermined program by a central processing unit (CPU) having an interface whose clock frequency can be changed. A task that is an execution unit, a timer that can set an arbitrary time, manages the operation of the interrupt handler and the task, sets the timer when the interrupt handler starts, and sets a clock for the central processing unit. And an operating system for performing power saving control for changing the frequency to a high value and changing the clock frequency to a low value for the central processing unit when the timer expires.

The computer system according to the second embodiment includes a timer time holding unit that holds the time set in the timer, which is accessible from the task and the operating system, and the task includes the timer time holding unit. The holding time is dynamically changed, and the operating system refers to the timer time holding unit to set the time in the timer.

[0030]

According to the present invention, the clock frequency of the operating clock of the processor device is increased when an interrupt event occurs, and the clock frequency of the operating clock of the processor device is decreased after a predetermined time has elapsed from the occurrence of the interrupt event. Therefore, it is possible to achieve power saving of the computer device without using special hardware.

Further, according to the present invention, since the high clock operating time can be changed, the high clock operating time is lengthened in a situation where the load is heavy and the processing is long such as multimedia reproduction. Therefore, appropriate power saving can be achieved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer system according to a first embodiment of the present invention.

FIG. 2 is a flowchart of the power saving process according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a computer system according to a second embodiment of the present invention.

FIG. 4 is a flowchart of the power saving process shown in the second embodiment of the present invention.

FIG. 5 is a configuration diagram showing a conventional power saving system.

[Explanation of symbols]

1 central processing unit, 2 interrupt handler, 3 tasks, 4 operating system, 5 timer, 6
Keyboard, 7 computer system, 11 timer time holding unit.

   ─────────────────────────────────────────────────── ─── Continued front page    (54) [Title of Invention] Computer apparatus, processor control method, and processor control method executed by computer                     And a program for causing a computer to execute the processor control method                     Computer readable recording medium

Claims (7)

[Claims] 1. A computer device comprising a processor device operable by an operating clock having any one of a plurality of clock frequencies, the computer device detecting occurrence of a particular interrupt event and When an interrupt event occurs, for a predetermined time from the occurrence of the specific interrupt event, the processor device is operated with an operating clock having a clock frequency higher than the clock frequency before the occurrence of the specific interrupt event, A computer characterized in that, after a lapse of a predetermined time from the occurrence of a specific interrupt event, the processor device is operated with an operating clock having a clock frequency lower than the clock frequency during the predetermined time from the occurrence of the specific interrupt event. apparatus. 2. The computer apparatus detects the occurrence of a specific interrupt event and, when the specific interrupt event occurs, the specific interrupt event for a predetermined time period from the occurrence of the specific interrupt event. The processor device is operated with an operating clock having a clock frequency higher than the clock frequency before the occurrence of, and after a lapse of a predetermined time from the occurrence of the specific interrupt event, The computer device according to claim 1, further comprising an operating system for operating the processor device with an operating clock having a clock frequency lower than the clock frequency. 3. The computer device sets a high clock operating time to keep a clock frequency of an operating clock of the processor device high, and the specific interrupt event is generated when the specific interrupt event occurs. 2. The computer according to claim 1, wherein the processor device is operated with an operating clock having a clock frequency higher than the clock frequency before the occurrence of the specific interrupt event during the period from the occurrence of the high clock operating time. apparatus. 4. The computer device according to claim 3, wherein the computer device changes the high clock operating time in a predetermined case. 5. A processor control method for controlling a processor device capable of operating with an operation clock of any one of a plurality of clock frequencies, which detects the occurrence of a specific interrupt event and When an interrupt event occurs, for a predetermined time from the occurrence of the specific interrupt event, the processor device is operated with an operating clock having a clock frequency higher than the clock frequency before the occurrence of the specific interrupt event, After a lapse of a predetermined time from the occurrence of the specific interrupt event, the processor device is operated with an operation clock having a clock frequency lower than a clock frequency during a predetermined time from the occurrence of the specific interrupt event. Processor control method. 6. A program for causing a computer including a processor device operable by an operation clock having any one of a plurality of clock frequencies to execute a processor control method for controlling the processor device. , Detecting the occurrence of a specific interrupt event, and when the specific interrupt event occurs, higher than the clock frequency before the occurrence of the specific interrupt event for a predetermined time from the occurrence of the specific interrupt event Operating the processor device with an operating clock having a clock frequency, and operating a clock frequency lower than a clock frequency during a predetermined time from the occurrence of the specific interrupt event after a predetermined time has elapsed from the occurrence of the specific interrupt event. Operate the processor device with a clock A program that causes a computer to execute a processor control method that causes the computer to create the program. 7. A program for causing a computer having a processor device operable by an operation clock of any one of a plurality of clock frequencies to execute a processor control method for controlling the processor device is recorded. A computer-readable recording medium, which detects the occurrence of a specific interrupt event, and when the specific interrupt event occurs, the specific interrupt event for a predetermined time from the occurrence of the specific interrupt event. The processor device is operated with an operating clock having a clock frequency higher than the clock frequency before the occurrence of, and after a predetermined time has elapsed from the occurrence of the specific interrupt event, Clock frequency lower than clock frequency A computer-readable recording medium having recorded therein a program for causing a computer to execute a processor control method for operating the processor device at an operation clock of a wave number.