JP2006072698A - Power-saving-adapted device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein a recently popular portable terminal that employs power saving control of bringing a CPU to a sleep state except during processing and bringing it back to an awake state at the timing of processing takes predetermined time to bring the sleep state to the awake state and involves delay in processing after recovery from the sleep state. <P>SOLUTION: When power saving control brings a CPU to a sleep state, if a timer has been started to show the next processing timing, a dummy timer that will time out at the time that is the timing minus predetermined time for recovery to an awake state is started to ensure that the CPU is in an awake state at the original processing timing. Timeout processes in a tolerance range are batched to save resources used. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power saving device that shifts to a power saving mode under a predetermined condition.

In the case of a device that operates by supplying power from a battery, such as a portable terminal, which has been widespread in recent years, the user desires that it can be used for as long as possible with a single charge. For this reason, devices such as portable terminals in recent years are designed to increase the power saving effect by shifting a part of the device to the sleep state for the purpose of reducing unnecessary current consumption when the necessary processing is not performed. It is normal. By the way, many devices such as portable terminals are provided with a function of performing an operation (job) designated at a reserved time using a timer. When a device having this function enters the sleep state with the operation reserved, it takes time to enter the sleep state and return to the awake state (normal mode) again. Therefore, the device operates accurately at the reserved time. There is a problem that is not executed. For example, Patent Document 1 discloses a power-saving device that copes with such a problem and enables a job to be accurately started at a time reserved in advance. In Patent Document 1, an operation state control unit for shifting from the sleep state to the awake state is provided separately from the sleep target processing unit, so that the processing unit is shifted to the awake state in advance at the reserved time. Thus, a power-saving device configured to execute a job accurately at a reserved time is disclosed.
JP 2002-186179 A

  However, in the invention of Patent Document 1, an operation state control processing unit for shifting from Sleep to Awake is required separately from the sleep target processing unit, and there is a problem that the operation state control processing cannot be Sleeped. . It is an object of the present invention to provide a power saving device that can start a job accurately at a reserved time without separately providing an operation state control unit.

  In order to solve the above-described problem, a power saving compatible device according to claim 1 of the present application measures an elapsed time by starting an operation unit that operates according to set contents and a timer, and reaches a predetermined timeout time. Power saving support provided with a timer control unit that sometimes instructs the operation unit to operate, and a power saving control unit that shifts at least a part of the operation unit to a sleep state (non-operation state) when a predetermined condition is satisfied When the timer is activated when the timer control unit shifts to the sleep state, the timer control unit shifts from the time-out time of the activated timer and the sleep state to the awake state (normal operation state). It is characterized in that a dummy timer having a dummy time-out time set in consideration of a predetermined time taken to start is started.

  With this configuration, when the timer time-out time arrives, an interrupt due to a dummy timer time-out occurs prior to that, so that the generating operation unit is in the Awake state, and the original timer time-out process is performed in the Awake state. Therefore, even when the time-out process is performed after returning from Sleep, the time-out process can be executed at an accurate time.

  In addition to the configuration according to claim 1, the power saving device according to claim 2 of the present application is shorter than a predetermined time required for the time until the timeout to shift from the sleep state to the awake state (normal operation state). A timer control unit that instructs the power saving control unit to stop the transition to the sleep state.

  With this configuration, when it is more advantageous from the standpoint of timer accuracy and power consumption to wait for a timer timeout without shifting to the Sleep state, the transition to the Sleep state can be stopped.

  In addition to the configuration of claim 1, the power saving device according to claim 3 of the present application has a predetermined allowance time for each timer when a plurality of timers are activated when the sleep state is set. A timer within the error range is extracted as a batch processing timer, a batch timeout time is calculated based on at least one timeout time among the timeout times of the batch processing timer, and a plurality of timeout processes are grouped at the timeout time at once. And a timer control unit that starts a dummy timer so that at least a part of the operation unit shifts to the awake state at the batch processing time-out time. By performing a plurality of time-out processes collectively with this configuration, the time-out process can be performed efficiently, and the resources of the apparatus (CPU resources when controlled by the CPU) can be used efficiently.

  Further, the power saving device according to claim 4 of the present application has the configuration according to claim 3, and the average value of the earliest timeout time and the latest timeout time among the timeout times of the batch processing timer is determined as a batch timeout time. A timer control unit is provided. With this configuration, when performing a plurality of timeout processes at once, the earliest timeout time and the latest timeout time can be considered with the same weight.

  Furthermore, the power saving device according to claim 5 of the present application, in addition to the configuration according to claim 3, determines the batch processing time-out time by reflecting a preset priority of the batch processing timer. It is a feature. With this configuration, it is possible to answer the user's desire to reduce the error of the high priority timer as much as possible.

  In addition to the configuration of claim 1, the power saving device according to claim 6 of the present application has an interrupt other than a timeout in a state where the timer is activated and the operation unit is shifted to the sleep state. When a factor occurs and the operation unit shifts to the Awake state, after performing interrupt processing, check whether a timer that has a timeout time within a predetermined error range has been started from that point, and the corresponding timer In the case where it exists, it is characterized in that it includes a timer control unit that continuously performs a timeout process.

  With this configuration, when an interrupt other than a timer interrupt occurs and the state becomes an awake state, if there is a time-out process within the error range, it is collectively performed, so that stabilization wait (stable wait until the awake state is reached) Therefore, power consumption can be reduced.

  Further, in the power saving device according to claim 7 of the present application, an interrupt factor other than a timeout occurs when the timer is started and the operation unit is in the sleep state, and the operation unit is in the awake state. After the interrupt processing, check whether a timer that has a timeout time within the specified error range has been started from that point, and if the timer has been started, A timer control unit for stopping the corresponding dummy timer is provided.

  With this configuration, an unnecessary dummy timer can be stopped, and device resources can be used efficiently.

  As described above, according to the present invention, before the CPU shifts to the sleep state, the presence or absence of a timer that has been activated is determined. If there is a timer that has been activated, the time to timeout is calculated, By starting a new timer that deducts a predetermined time for the CPU to transition from the sleep state to the awake state, it is not necessary to acquire the current time during sleep and determine whether to awake. There is an effect that the time-out process can be executed at an accurate time even in the state where the sleep mode is set to sleep.

(Embodiment 1)
Embodiment 1 of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a mobile phone embodying the present invention. The mobile phone according to the present embodiment also includes a CPU (not shown) as in the case of a normal mobile phone, and various functions can be achieved by running programs such as application software (hereinafter referred to as applications) on the CPU. Is realized.

  In general, a portable terminal including a mobile phone has a function of shifting to a power saving mode in order to lengthen a battery driving time. In this specification, the power saving mode is set to a (CPU) sleep state or not a power saving state. Is described as an Awake state.

  The application 101, the application 102, and the application 103 are applications that operate on a mobile phone. These applications run on the CPU and perform various operations according to the set contents. In other words, the CPU and the application constitute an operation unit.

  The timer control unit 105 is a control unit for starting a timer in response to a request from an application or another control unit. It also plays the role of starting the specified application when the requested timer times out.

  The device state monitoring unit 106 monitors various states in the device, and when there is no processing to be performed by the CPU, instructs the power saving control unit 107 to transition to the sleep state.

  It is assumed that transition from the sleep state to the awake state is caused by an interrupt from the hardware.

  An operation flow of the power saving control unit 107 in the mobile phone according to the first embodiment will be described with reference to FIGS. FIG. 2 is a flowchart showing the timer activation process at the time of Sleep, and shows the process from the time when the apparatus state monitoring unit 106 instructs the power saving control unit 107 to transition to the Sleep state, from S201 to S205. It consists of FIG. 5 is an explanatory diagram showing timer activation processing timing during Sleep.

  In step S201, when the power saving control unit receives a transition instruction from the device state monitoring unit to the sleep state, it inquires the timer control unit 105 about the current timer state. That is, an inquiry is made as to whether the timer is currently activated, and if it is activated, the time at which each timer times out is obtained.

  In S202, the difference between the time of the timer that times out in the shortest time (S502) and the current time (S501) are compared, and this is set as T1 (S503).

  The transition from the Awake state to the Sleep state and the transition from the Sleep state to the Awake state require a predetermined time depending on the hard condition and the software condition. The time taken for the transition from the awake state to the sleep state is ΔT1 (S507). The time taken for the transition from the sleep state to the awake state is ΔT2 (S506). T1 obtained in S202 is compared with ΔT1 and ΔT2. In the case of T1> (ΔT1 + ΔT2), the state transits to the sleep state. At this time, the system actually enters the awake state after T1 + ΔT2. In order to bring this to the awake state after T1, a dummy timer (S505) having a timer value T2 = T1-ΔT2 is newly set. The dummy timer is a timer that performs a timeout process at a specified timeout time but does not instruct the operation unit to perform a specified operation. When timeout processing is performed, interrupt processing is performed, so that the system shifts to the Awake state after ΔT2. Therefore, by setting the dummy timer, the time for the system to be in the Awake state is T2 + ΔT2 = (T1−ΔT2) + ΔT2 = T. This process is shown in S203, S204, and S205.

  In T203, when T ≦ (ΔT1 + ΔT2), it is more advantageous to wait for the timer to timeout without transitioning to the sleep state from the viewpoint of accuracy or power of the timer. Therefore, the transition to the sleep state is not performed. As described above, in the present embodiment, when the time-out time of the activated timer arrives, the apparatus is always in the Awake state, so that the time-out process is accurately executed at the reserved time.

(Embodiment 2)
Next, the second embodiment will be described with reference to FIGS. FIG. 3 is a flowchart showing a timer change procedure at the time of Sleep in the second embodiment. The flowchart of FIG. 3 is a flowchart showing processing from the time when the apparatus state monitoring unit 106 instructs the power saving control unit 107 to transition to the sleep state, and includes steps S301 to S310. FIG. 6 is an explanatory diagram showing timer change processing timing during Sleep. As in the first embodiment, this embodiment also applies the present invention to a mobile phone, and the overall configuration is as shown in FIG. Hereinafter, the timer changing procedure will be sequentially described.

  First, in S301, a timer allowable error Te (S601) is determined. Note that a fixed value may be used as Te, or what is set by the user is stored and may be read and used.

  In step S <b> 302, the power saving control unit 107 inquires the timer control unit 105 about the timeout time of the timer having the closest timeout time and obtains it.

  The timer time acquired in S303 is T1 (S602).

  If there is a next timer, the time-out time of the next time-out timer is inquired in S304, and the time acquired in S305 is set as T2 (S603).

  In the case of (T1 + Te)> (T2-Te), even if the timers are timed out together, they are within the allowable error range. Therefore, the time Td for performing time-out processing in S306 is the same as T1 and T2. Determined by considering weight. Since T1 and T2 are considered with the same weight, Td is the midpoint of the time zone within the allowable error range, and Td = (T2−Te) + ((T1 + Te) − (T2−Te)) / 2 = It can be obtained as (T1 + T2) / 2. For example, it is assumed that the allowable error Te is 7 minutes, three timers are started, and the respective time-out times are 12:10, 12:11, and 12:20. The limit value within the tolerance of the timer that times out at 12:10 is 12:17, and the limit value within the tolerance of the timer that times out at 12:20 is 12:13. The timer can perform timeout processing collectively. The time Td for time-out processing collectively is Td = (12: 10 + 12: 20) / 2 = 12: 15.

  In S307, the timer for changing the timeout is stored.

  If there is a timer that times out next time, S304 to S307 are repeated.

  If there is no timer that times out or the timer that times out next does not satisfy (T1 + Te)> (T2−Te), in S308, all the timers that change the timeout are changed to time out at Td.

  In S309, a timer (S605) with a timeout time Td−ΔT2 is set.

  In S310, the state shifts to the Sleep state.

  As described above, in the present embodiment, in addition to the effects of the first embodiment, efficient timeout processing can be performed by collectively processing timers within the set allowable error.

  In the above method, when there are three or more timers that perform timeout processing collectively, the timeout time that is farthest from T1 is T2 among the timeout times of the timers that are collectively processed. , T1 and T2 are taken into consideration, and the time-out time Td to be collectively processed is obtained, but the average value of time-out times that can be collectively processed may be Td. For example, when there are three timers to be processed together, the respective timeout times are set as T1, T2, and T3, and Td is obtained as Td = (T1 + T2 + T3) / 3. According to this method, it is possible to consider the timeout times of timers that perform timeout processing collectively with the same weight.

  Furthermore, a separate tolerance may be set for each timer. For example, it is assumed that the allowable error when the timeout time is T1 is Te1, and the allowable error when the timeout time is T2 is Te2. In this case, when T1 + Te1> T2-Te2, both timers are collectively timed out.

  The time Td at which timeout processing is performed collectively is Td = (T2−Te2) + ((T1 + Te1) − (T2−Te2)) / 2. That is, when both tolerances are equal, Td is the average value of T1 and T2, and when Te1 is greater than Te2, Td is on the T2 side relative to the average value of T1 and T2, and when Te2 is greater than Te1. , Td is on the T1 side of the average value of T1 and T2.

(Embodiment 3)
Next, Embodiment 3 will be described with reference to FIGS. 4 and 7. FIG. FIG. 4 is a flowchart showing a timer processing procedure at the time of another interrupt according to the third embodiment, and includes steps S402 to S408. The flowchart shown in FIG. 4 is processing from the time point when the interrupt control unit 104 detects an interrupt. In the third embodiment, as in the first and second embodiments, the present invention is applied to a mobile phone, and the overall configuration is as shown in FIG. The processing at the time of another interrupt will be described below.

  In S402, a timer allowable error Te (S702) is acquired.

  In S403, an inquiry is made to the timer control unit 105 as to whether or not the timer is activated. If there is an activated timer, an inquiry is made from the timer control unit about the timeout time T1 (S703) of the timer having the closest timeout.

  In the case of T1 <Te, even if the process with the closest timeout is executed, it is within the allowable error range. Therefore, the timer controller 105 is stopped with the dummy timer and the timer with the closest timeout in S405, and the timeout is detected in S406. Perform the closest process.

  Steps S403 to S406 are repeated until there is no active timer in the timer control unit or T1 <Te is not satisfied.

  As described above, in the present embodiment, when an interrupt other than a timer occurs, a time-out process within the allowable error range is also performed, and unnecessary dummy timers are stopped, thereby effectively reducing CPU resources. It can be used for.

(Embodiment 4)
The present embodiment is a modification of the second embodiment, and when priority is set for the timer, among the plurality of timers that perform timeout processing collectively, the error of the timer with high priority is reduced. Thus, the timeout time is determined.

  FIG. 8 is a flowchart showing processing for determining the timeout processing time in the present embodiment, and includes S801 to S811.

When individual timers are set, it is assumed that the user sets priorities in five levels (5 is the highest and 1 is the lowest). For example,
For timer 1, timeout time: 12:10 Priority: 3
For timer 2, timeout time: 12:15 Priority: 2
For timer 3, timeout time: 12:20 Priority: 5
(Hereinafter referred to as setting example 1).

  Thereafter, when there is a sleep state transition instruction from the apparatus state monitoring unit 106 to the timer control unit 105, the timer control unit 105 executes a timeout process shown in FIG. First, in step S801, the allowable error of the timer is set to Te.

  In the next step S803, the timer control unit 105 is inquired about the timer state. In step S803, the timeout time of the timer with the closest timeout is set to T1. In step S804, the time-out times and priorities of all timers having a time-out time Tj satisfying T1 + Te ≧ Tj−Te are extracted from the activated timers. It is said. Now, assuming that Te = 7 minutes, the timer 1, timer 2 and timer 3 in the setting example 1 all satisfy this condition, and therefore the respective timeout times and priorities are extracted.

  In the next step S805, it is checked whether or not there is only one timer with the highest priority. If there is only one, the process proceeds to step S806, and if not (two or more), the process proceeds to step S807. In step S806, the time-out time of the timer with the highest priority is set as a time Td at which time-out processing is performed collectively. In the setting example 1, the priority of the timer 3 is the highest, so the timeout time 12:20 is set as Td. In step S807, an average value of timeout times of timers having the highest priority is set as Td. For example, Te is also 7 minutes, and three timers are set as follows (hereinafter referred to as setting example 2).

Timer 1 timeout time: 12:10 Priority 3
Timer 2 timeout time: 12:12 Priority 5
Timer 3 timeout time: 12:20 Priority 5
In the case of setting example 2, since timer 2 and timer 3 both have the highest priority, the average time-out value 12:16 of timer 2 and timer 3 is Td.

  In the next step S808, it is checked whether Td ≦ T1 + Te, that is, whether Td is within the allowable error range of the time-out time of the timer closest to the time-out. If Td ≦ T1 + Te, the process proceeds directly to S810. If not, that is, if Td is later than the allowable error range of T1, the process proceeds to step S809, where T1 + Te is set to Td. In the next step S810, it is checked whether Td ≧ TL-Te. That is, it is checked whether or not Td is within the allowable error range of the time-out time of the timer having the latest time-out time among the timers targeted for time-out processing. If Td ≧ TL−Te, the process is terminated as it is. If not, that is, if Td is earlier than the allowable error range of TL, T2−Te is set to Td.

  As described above, in the present embodiment, in principle, the time-out time of the timer with the highest priority (the average value when there are a plurality of times) is adopted as the time for performing the time-out processing collectively, and is within an allowable error range. Only when outside the time zone, by adopting the limit value of the time zone within the allowable error range as Td, it is possible to determine the time for performing the time-out process collectively so that the error of the timer with high priority is minimized. An efficient time-out process can be performed by reducing the error of a timer whose priority is set high so that the user wants to time out accurately and performing the time-out process collectively. The priority may not be set by the user, but may be assigned in advance according to the type of job (such as sounding an alarm or sending an email) activated by a timer. Furthermore, it is good also as a structure which a user can change arbitrarily the priority allocated beforehand. In addition, the priority is not limited to five levels, it is only necessary to determine the order, and it may be set with fine numerical values (numbers from 0 to 100, etc.), or roughly in three levels such as high, medium, and low. You may make it classify into.

  As described above, in the first to fourth embodiments, the case where the present invention is applied to a mobile phone has been described. However, the application of the present invention is not limited to the mobile phone, and the sleep state is set regardless of the mobile device or the fixed device. Of course, it can be applied to electronic and electrical equipment having a function to be transferred.

  The power-saving device according to the present invention is useful as a portable device that is controlled mainly by a battery such as a cellular phone. Further, the present invention can also be applied to uses such as fixed devices that need to be turned on but do not perform processing and need to reduce power consumption.

Block diagram of a mobile phone that implements the power saving device of the present invention Flow chart showing the timer start processing procedure at the time of Sleep Flow chart showing the timer change processing procedure during Sleep Flow chart showing the timer processing procedure for other interrupts Explanatory drawing which shows the timer starting processing timing at the time of Sleep Explanatory drawing which shows the timer change processing timing at the time of Sleep Explanatory diagram showing timer processing timing at other interrupts Flow chart showing the processing for determining the timeout processing time

Explanation of symbols

101 to 103 Application 104 Interrupt control unit 105 Timer control unit 106 Device state monitoring unit 107 Power saving control unit

Claims (7)

An operation unit that operates according to the set contents;
A timer control unit that counts the elapsed time by starting a timer and instructs the operation unit to operate when a predetermined timeout time is reached;
A power saving device including a power saving control unit that shifts at least a part of the operating unit to a sleep state (non-operating state) when a predetermined condition is satisfied,
When the timer is started, when the timer is started, the timer control unit determines a time-out time of the started timer and a predetermined time required for shifting from the Sleep state to the Awake state (normal operation state). A power-saving device characterized by starting a dummy timer having a dummy time-out time in consideration of time. The timer control unit instructs the power saving control unit to stop the transition to the sleep state when the time until the timeout is shorter than a predetermined time required for the transition from the sleep state to the awake state. The power saving device according to claim 1. The timer control unit extracts a timer whose timeout time is within a predetermined allowable error range as a batch processing timer when a plurality of timers are activated when setting the sleep state, and the batch processing timer A batch timeout time is calculated based on at least one of the timeout times, and a plurality of timeout processes are performed at a time at the timeout time, and at least a part of the operation unit at the batch processing timeout time is 2. The power saving apparatus according to claim 1, wherein the dummy timer is activated so as to shift to the awake state. 4. The apparatus according to claim 3, wherein the timer control unit sets an average value of an earliest timeout time and a latest timeout time among the timeout times of the batch processing timer as a batch timeout time. 4. The apparatus according to claim 3, wherein the timer control unit determines the batch processing time-out time by reflecting a preset priority of the batch processing timer. The timer control unit
When an interrupt factor other than a timeout occurs when the timer is started and the operation unit is transitioning to the sleep state, and the operation unit transitions to the awake state, 2. The apparatus according to claim 1, wherein it is checked whether or not a timer having a timeout time within a predetermined error range is started, and if a corresponding timer exists, the timeout process is continued. . The timer control unit
When the timer is started and the operating unit is in the sleep state, an interrupt factor other than timeout occurs and the operating unit enters the awake state.
After performing interrupt processing, check whether a timer with a timeout time within a predetermined error range has been started from that point, and whether a timer with a timeout time within a predetermined error range has not been started. 2. The apparatus according to claim 1, wherein when the corresponding timer is activated, the dummy timer activated corresponding to the timer is stopped.

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