JPH0740212B2 - Divider circuit - Google Patents

Description

The present invention relates to a frequency dividing circuit for supplying a clock to an internal block of an integrated circuit such as a microcomputer.

(B) Conventional technology The microcomputer used to control AV equipment or air-conditioning equipment incorporates functions comparable to conventional peripheral LSIs such as interfaces, AD converters, timers, etc.
In order to operate these functions, a clock having a different frequency for each functional block, that is, a clock having a frequency lower than the normal system clock is required, so the system clock is divided and supplied.

An example of a conventional clock supply circuit (hereinafter referred to as a frequency dividing circuit) of a microcomputer will be described with reference to FIG.

The oscillation output (2a) of the source oscillation circuit (22) excited by the crystal oscillator (21) having a resonance frequency of several M cycles is the system clock (2f) whose waveform is adapted to the system operation by the system clock generator (25). Is converted into a clock source (2k) for an interface, an AD converter or the like by being subjected to predetermined frequency division by a prescaler (26). Further, a predetermined frequency division stage output (2j) of the prescaler (26) is supplied to the timer (27) as a count source of an 8-bit or 16-bit counter which constitutes the timer (27).

In the microcomputer configured as described above, the second signal can be easily obtained from the output (2k) of the prescaler (26) or the overflow signal (2m) of the timer (27), so a clock function is often added. However, because of the reasons described below, it is inevitable that this microcomputer will have difficulty in backing up in the event of an accident such as a power failure, and that the clock function will be impaired in the event of an accident.

That is, the power consumption of the microcomputer tends to be substantially proportional to the frequency of the system clock, and it is not preferable from the viewpoint of power consumption to operate the system clock at the normal frequency even during standby. Therefore,
In standby mode, the system clock is set to 1/10
The method is adopted. This makes it possible to perform a simple backup with a capacitor in case of an instantaneous power failure in which the power cord of the device is unplugged by mistake.

Next, an example of the frequency dividing circuit proposed for such a purpose will be described with reference to FIG.

The frequency of the output (3a) of the source oscillation circuit (32) is, for example, 10 M cycles, and the prescaler (33) divides it by a factor of 5 M cycles to divide the output (3b) and the frequency of 10 M cycles.
Frequency division output (3
c) is output. The numerical values used here are for convenience.

So, for example, if the power supply is normal and the system
When it should be operated with the system clock of 5M cycles, a flag (not shown) is reset, the switching select signal (3d) becomes low level, and the switching device (34) selectively passes the frequency division output (3b) of 5M cycles. The output is (3e). The system clock generator (35) which inputs the output (3e) of this 5M cycle converts this into a system clock (3f) having a waveform suitable for the operation of the system and supplies it to the system, and also through the prescaler (36). Use as clock source (3K) for interface, AD converter, etc. Further, the predetermined frequency division stage output (3j) of the prescaler (36) is supplied as the count source of the 8-bit or 16-bit counter which constitutes the timer (37).

Therefore, when a flag (not shown) is set by a momentary power failure and the switching sect signal becomes high level, the switching device (34) divides the source oscillation frequency by 1/100 to output the output (3c) of 100K cycles. The signal is selectively passed, and its output (3e) is input to the system clock generator (35). As a result, the system clock becomes several tenths of the normal time, the power consumed by the microcomputer can be reduced to several tenths, and the backup capacitor can have a sufficiently low load.

However, in the above-mentioned microcomputer, the frequency of the output (3k) of the prescaler (35) becomes 1/10 of the normal time in the standby state, and it is not possible to configure a hardware clock by using this as a second signal. Therefore, the overflow signal (3m) of the timer (37) is used. In this case, the system that detects the system clock frequency switching and the reload register (not shown) that composes the timer (37) uses the system. Software that writes an initial value using an accumulator each time the frequency of the clock is switched is required, which has the drawback of increasing the load on the software.

(C) Problem to be Solved by the Invention The present invention has been made in view of the above points, and is an integrated circuit that divides a system clock to obtain a clock source of each block in the system. It is an object of the present invention to provide a frequency dividing circuit in which the frequency of the clock supplied to each block does not change even when the frequency is switched.

(D) Means for Solving the Problems The present invention relates to an integrated circuit that divides a system clock to obtain a clock source for each block in the system.
The system includes means for switching the frequency of the system clock, and means for changing the frequency division number of the system clock in response to the frequency switching to keep the frequency of the clock source supplied to each block constant.

(E) Operation The above configuration makes backup in case of an accident such as a momentary power failure relatively easy, and may impair other functions such as a clock function that operates with a clock obtained by dividing the system clock. Acts to prevent it.

(F) Embodiment An embodiment of the present invention will be described with reference to FIG.

Today, the most common microcomputers are several M to 10M
Operates on the cycle system clock. To obtain this system clock, the resonance frequency of the crystal oscillator (11) that excites the source oscillation circuit (12) is selected to be, for example, 10 M cycles, and the prescaler (13) that inputs this oscillation circuit output (1a) is Divide the source oscillation frequency of 10 M cycles by 1/2
It outputs a 5M-cycle divided output (1b) and a 100K-cycle divided output (1c) that divides the source oscillation frequency by 1/100. The numerical values used here are for convenience,
In practice, for example, it is necessary to use a pre-designed numerical value necessary to finally obtain a clock of 3.579545M cycles suitable for a clock circuit or 1.7897725M cycles that divides it by half. Add note. Therefore, for example, if the power supply is normal and the microcomputer is
When operating with the system clock of 5M cycles, a flag (not shown) is reset, the switching select signal (1d) becomes low level, and the switching device (14)
5M cycle divided output (1b) is selectively passed. The system normally operates based on the 5M-cycle system clock (1f) output by the system clock generator (15) which receives the switch output (1e).
Further, when the switching select signal (1d) is at a low level, the switching device (163) forming the prescaler (16)
Is a divider (16) that also constitutes the prescaler (16).
The divided output (1h) of 2) is selectively passed and its output (1i)
A divider (164) that also constitutes the prescaler (16)
To enter. As a result, the divided output (1k), which divides the 5M cycle system clock (1f) in relatively large numbers, is used as the clock source for the interface and AD converter. In addition, the frequency divider (16
The output (1j) of the predetermined frequency division stage of 4) is supplied as the count source of the 8-bit or 16-bit counter which constitutes the timer (17).

Then, when it becomes necessary to reduce the power consumption of the microcomputer due to the occurrence of an accident such as an instantaneous power failure, a flag (not shown) is set by the program and the switching select signal (1d) becomes high level. As a result, the switch (14) selectively passes the divided output (1c) of 100K cycles, and the system clock generator (15) which inputs this selectively outputs the system clock (1c) of 100K cycles.
f) is generated. This lowering of the system clock reduces the power consumed by the microcomputer and enables simple backup with a capacitor.

Further, when the switching select signal (1d) becomes low level, the switching device (163) forming the prescaler (16)
Also selectively passes through the frequency division output (1g) of the frequency division (61) that constitutes the prescaler (16). Here, by setting the frequency division number of the frequency divider (162) forming the prescaler (16) to be equal to the frequency division ratio of the frequency division output of the pair of the prescaler (13), the switching device (14) operates in 100 K cycles. The frequency of the output (1i) of the switch (163) when selectively passing the divided output (1c), and the switch (14c) when the switch (14) selectively passes the divided output of 5M cycles (1c) ( 16
The frequency of the output (1i) of 3) can be made equal.

Thus, the output (1k) of the prescaler (16), which is always constant regardless of the change of the system clock frequency, is used as the clock source of the interface, AD converter, etc., and the frequency divider (164) constituting the prescaler (16). The predetermined frequency division stage output (1j) is supplied as the count source of the 8-bit or 16-bit counter that constitutes the timer (17). As a result, even if a hardware timepiece that uses the output (1k) of the prescaler (16) is configured, the function will not be hindered by an accident such as a momentary power failure. When the clock is constructed using the overflow signal (1 m) of the timer (17), it is sufficient to write the initial value irrespective of the state of the system clock into the reload register constituting the timer (17).

In the above, the present invention has been mainly described by taking the clock supply to the timer as an example, but other than the clock supply to the timer, for example,
It can also be applied to driving a display element or refreshing a ram. That is, even if the system clock is changed due to a software request,
It is possible to change so that these operations can be performed without any hindrance.

(G) Effects of the Invention As described above, according to the present invention, (1) since the frequency of the system clock can be significantly reduced, a simple backup means can be adopted.

(2) Since the system clock is not stopped, it is easy to return from the standby state.

(3) It is possible to significantly change the system clock regardless of the capacity of the timer counter.

(4) When changing the frequency of the system clock, it is not necessary to write new data to the reload register, so that the load on software is reduced.

It is possible to provide a frequency divider circuit that has the remarkable effect.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams of a conventional example. (11), (21), (31) ... Crystal oscillator, (12), (2
2), (32) ... Oscillation circuit, (13), (16), (26),
(33), (36) …… Prescaler, (14), (163),
(34) ... Switcher, (15), (25), (35) ... System clock generator, (17), (27), (37) ...
… Timer, (1d) …… Switch select signal.

Claims (2)

[Claims] 1. A means for generating a plurality of clock pulses having different frequencies, a switching means for selectively outputting the plurality of clock pulses, and an operation of an internal circuit based on the clock pulse selected by the switching means. In an integrated circuit including a system clock generator for generating a system clock, the system clock of the system clock generator is frequency-divided to obtain a clock source of a required block, and in response to the switching of the switching unit. A frequency dividing circuit comprising means for changing the frequency dividing number of the frequency dividing means to keep the frequency of the clock source constant. 2. The frequency dividing circuit according to claim 1, wherein the frequency of the system clock is switched in response to execution of a standby instruction or detection of a power failure.