JPS60163739U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS60163739U JPS60163739U JP1984050357U JP5035784U JPS60163739U JP S60163739 U JPS60163739 U JP S60163739U JP 1984050357 U JP1984050357 U JP 1984050357U JP 5035784 U JP5035784 U JP 5035784U JP S60163739 U JPS60163739 U JP S60163739U
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- semiconductor element
- power semiconductor
- semiconductor equipment
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図および第2図は従来の半導体装置を説明する断面
図、第3図は本考案の半導体装置を説明する断面図、第
4図は本考案に用いるヒートシンクを説明する上面図で
ある。
11は固着基板、12はヒートシンク、13はパワー半
導体素子、14は半田層、15は台地である。1 and 2 are cross-sectional views illustrating a conventional semiconductor device, FIG. 3 is a sectional view illustrating a semiconductor device of the present invention, and FIG. 4 is a top view illustrating a heat sink used in the present invention. 11 is a fixed substrate, 12 is a heat sink, 13 is a power semiconductor element, 14 is a solder layer, and 15 is a plateau.
Claims (1)
ー半導体素子を半田で固着する半導体装置に於いて、上
記ヒートシンク上面にパワー半導体素子より若干小さい
台地を設け、前記パワー半導体素子の周辺の半田の厚み
を中央より厚く形成することを特徴とする半導体装置。In a semiconductor device in which a power semiconductor element is fixed with solder on a fixing substrate via a heat sink with good thermal conductivity, a plateau slightly smaller than the power semiconductor element is provided on the upper surface of the heat sink, and the solder around the power semiconductor element is disposed on the upper surface of the heat sink. A semiconductor device characterized by being formed thicker at the center.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984050357U JPS60163739U (en) | 1984-04-05 | 1984-04-05 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984050357U JPS60163739U (en) | 1984-04-05 | 1984-04-05 | semiconductor equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60163739U true JPS60163739U (en) | 1985-10-30 |
Family
ID=30568412
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984050357U Pending JPS60163739U (en) | 1984-04-05 | 1984-04-05 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60163739U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5466073A (en) * | 1977-11-04 | 1979-05-28 | Nec Corp | Semiconductor device |
-
1984
- 1984-04-05 JP JP1984050357U patent/JPS60163739U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5466073A (en) * | 1977-11-04 | 1979-05-28 | Nec Corp | Semiconductor device |
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