JPS6015946A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS6015946A
JPS6015946A JP12328483A JP12328483A JPS6015946A JP S6015946 A JPS6015946 A JP S6015946A JP 12328483 A JP12328483 A JP 12328483A JP 12328483 A JP12328483 A JP 12328483A JP S6015946 A JPS6015946 A JP S6015946A
Authority
JP
Japan
Prior art keywords
fuse
circuit
voltage
power supply
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12328483A
Other languages
Japanese (ja)
Other versions
JPH0584062B2 (en
Inventor
Fumiaki Fujii
文明 藤井
Koichi Kodera
浩一 小寺
Hideya Otani
大谷　秀弥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP12328483A priority Critical patent/JPS6015946A/en
Publication of JPS6015946A publication Critical patent/JPS6015946A/en
Publication of JPH0584062B2 publication Critical patent/JPH0584062B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To improve reliability, and to detect the state in which a fuse is connected under high resistance easily and positively by connecting a MOSFET in series with the fuse as a variable resistor, increasing the resistance value of the MOSFET on a detection and measuring potential difference at both ends of the fuse. CONSTITUTION:A MOSFET such as a P channel type MOSFETQ is connected in series between supply voltage VDD and VSS together with a fuse F consisting of polysilicon, etc. A gate terminal in the MOSFETQ is connected to a ground line GL for a circuit. Pads P1 and P2, through which currents are flowed and which blow out and treat the fuse F, are connected at both ends of the fuse F, a probe is brought into contact with the pads P1 and P2 at the stage of a wafer, and the fuse can be blown out by applying proper voltage to both ends of the fuse F and flowing large currents. When the fuse circuit is used as a level setting means for a voltage regulating circuit for an apparatus such as a CODEC, the fuse circuit is connected so that the potential of a connecting node (n) between the fuse F and the MOSFETQ is used as input voltage to an inverter IV.

Description

【発明の詳細な説明】 〔技術分野〕 この発明は、県債回路技術、さらには、ヒーーズの切断
の有無を判定する技術に関し１例えば、ヒユーズ切断を
備えた半導体装置におけるヒユーズ切断の有無を判定す
る場合に適用して有効な技術に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to prefectural bond circuit technology, and more particularly, to a technology for determining whether or not a fuse is blown.1 For example, the present invention relates to a technology for determining whether or not a fuse is blown in a semiconductor device equipped with a fuse blown. Regarding techniques that are effective when applied.

〔背景技術〕[Background technology]

本発明者は、この発明に先だち、牛導体第積回路技術に
関し、以下にのべる技術を開発した。Prior to this invention, the present inventor developed the following technology regarding the cow conductor product circuit technology.

Ａ／Ｄ　、　Ｄ／Ａ変換器とこれに供給される基準電圧
を発生する基準電圧発生回路とを有するＣ０ＤＥＣ（符
号器−復号器）のような半導体集積回路においては、プ
ロセスのバラツキにより発生される基準電圧が変動され
、これが変換精度に大きな影響を与える。そのため、プ
ロセスの最終段階で基準電圧を所望の値に正確に設定さ
せるための電圧調整回路を設けることが望ましい。この
ような電圧調整回路におけるレベル設定手段として、第
１図に示すように、電源電圧ＶＤＤとＶＳＳとの間に抵
抗几とポリシリコン等からなるヒユーズＦとを直列接続
し、その接続ノードの電位をインバータＩＶの入力とす
るようにしたものを考えた。In a semiconductor integrated circuit such as a C0DEC (encoder-decoder), which has an A/D and D/A converter and a reference voltage generation circuit that generates a reference voltage to be supplied to the converter, the The reference voltage used in the conversion is varied, which has a significant impact on conversion accuracy. Therefore, it is desirable to provide a voltage adjustment circuit to accurately set the reference voltage to a desired value at the final stage of the process. As a level setting means in such a voltage adjustment circuit, as shown in FIG. 1, a resistor and a fuse F made of polysilicon or the like are connected in series between the power supply voltages VDD and VSS, and the potential of the connection node is set. We considered a system in which the input voltage is used as the input of the inverter IV.

このレベル設定手段は、ヒユーズＦを切断するとノード
ｎのａｔ位がτＬ源電圧ＶＤＤレベルにされ、ヒユーズ
Ｆが切断されないときはノードｎの電位が電源電圧ＶＨ
８に近いレベルにされる。This level setting means is such that when the fuse F is cut, the at level of the node n is set to the τL source voltage VDD level, and when the fuse F is not cut, the potential of the node n is set to the power supply voltage VH.
It will be brought to a level close to 8.

このレベル設定手段全複数個用いて電圧調整回路の設定
部を豊成し、測定された基準電圧の誤差に応じて適当な
レベル設定手段内のヒユーズを切断してやることによ、
ｂ　Ｍｆ１ｇＴ主圧の補正を行なえるようにすることが
できる。By using all the plurality of level setting means to enrich the setting section of the voltage adjustment circuit, and cutting off the fuse in the appropriate level setting means according to the error of the measured reference voltage,
b The Mf1gT main pressure can be corrected.

また、本発明者は、上記のようなレベル設定手段におい
ては、切断処理を行なったヒユーズＦが確実に切断され
ているか否かを検査する場合、ヒユーズＦの両端に電圧
をかけて電流を流し、その電流値を測定することによシ
切断の有無を判定する方法を考えた。In addition, the inventor has proposed that in the level setting means as described above, when inspecting whether or not the fuse F that has been cut is reliably cut, a voltage is applied across the fuse F to cause a current to flow. We devised a method to determine the presence or absence of cutting by measuring the current value.

ところが半導体＊Ｓ租回路におけるヒユーズの切断方法
には、ヒユーズに大きな電流を流して溶断させる方法や
レーザによる方法等があるが、電流による溶断の場合は
、ヒユーズの中心部分は溶けて飛散するが両側に＃［ｉ
ｌ　＜ポリシリコンが残って切断が完全に行なわれない
ことがある。この場合、ヒユーズは極めて高い抵抗とし
てノードｎと電源πＬ圧Ｖ８Ｊ＋　との間に存在するこ
とになり、電圧をかけても非常に小さな電流が流れるに
すぎないため、電流測定によってはこれを検出すること
ができない。However, there are methods for cutting fuses in semiconductor *S circuits, such as blowing a large current through the fuse and blowing it, and using a laser.However, when blowing with an electric current, the center of the fuse melts and scatters. #[i on both sides
l<Polysilicon may remain and the cutting may not be completed completely. In this case, the fuse exists as an extremely high resistance between the node n and the power supply πL voltage V8J+, and even if a voltage is applied, only a very small current flows, so this can be detected depending on the current measurement. I can't.

しかるに、半導体集積回路においては、溶断されたヒユ
ーズの成分が飛散できるようにするため、ヒーーズの上
方の眉間絶縁膜やパシベーション膜は除去され、開口さ
れる。そのため、上記のごとく、ヒユーズの一部が残っ
ていると、この開口部分から水分等が侵入して付着し、
切断されたようにみえたヒユーズが導通状態（低抵抗）
にされて所望のレベル設定が行なえなくなるおそれがあ
る。However, in semiconductor integrated circuits, the glabella insulating film or passivation film above the fuse is removed and opened to allow the components of the blown fuse to scatter. Therefore, as mentioned above, if a part of the fuse remains, moisture can enter through this opening and stick to it.
The fuse that appeared to be disconnected is now conductive (low resistance)
There is a risk that the desired level setting may not be possible.

つまり、電流測定によるヒーーズの切断の有無の判定で
は検出精度が低く、信頼性を欠くことになる。In other words, determination of whether the heater is disconnected by current measurement has low detection accuracy and lacks reliability.

なお、ヒユーズの切断の崩無′ｌｋ顕微鏡を用いた外観
検査によシ判定する方法もあるが、この検査は人間の目
に頼らざるを得ないため、能率が悪いとともに、疲労に
よる見落し等の問題点もあることが分かった。There is also a method to determine if the fuse has collapsed by visually inspecting it using a microscope, but this inspection is inefficient as it relies on the human eye and is prone to oversights due to fatigue. It turns out that there are some problems.

〔発明の目的〕[Purpose of the invention]

本発明の一つの目的は、高信頼性の集私回路を提供する
ことにある。One object of the present invention is to provide a highly reliable private collector circuit.

この発明の他の目的は、従来に比べて顕著な効果を奏す
るヒユーズ切断の有無の判定技術を提供することにある
。Another object of the present invention is to provide a technique for determining whether or not a fuse is blown, which is more effective than conventional techniques.

この発明の他の目的は、例えばこの発明をヒ一ズを有す
る半導体装置に適用した場合に、不完全なヒユーズ切断
すなわちヒーーズが高抵抗接続している状態を容易かつ
確宍に検出できるようにすることにある。Another object of the present invention is to easily and reliably detect incomplete fuse disconnection, that is, a state in which the heaters are connected with high resistance, when the present invention is applied to a semiconductor device having a fuse, for example. It's about doing.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代嚢的なものの概要
をｆｔ１ｉ沖に説明すれば下記のとおりである。Among the inventions disclosed in the present application, an outline of the sac-like one is as follows.

すなわち、この発明は、例えば半導体装置のレベル設定
手段に用いられるヒユーズと直列にＭＯＳＦＥＴ　（絶
縁ゲート型電界効果トランジスタ）を可変抵抗として接
続し、検出時にその抵抗値を上げてやりてヒユーズ両端
の電位差を測定することによって、ヒユーズが高抵抗接
続されているときはそれが明確な電位差として検出でき
るようにして上記目的を達成するものである０ 以下図面を用いてこの発明を具体的に説明する。That is, the present invention connects a MOSFET (insulated gate field effect transistor) as a variable resistor in series with a fuse used, for example, as a level setting means in a semiconductor device, and increases the resistance value at the time of detection to measure the potential difference across the fuse. The above object is achieved by measuring a high resistance connection of a fuse so that it can be detected as a clear potential difference.

〔実施例〕〔Example〕

第２図は本発明を半導体装置におけるレベル設定手段に
適用した場合の一実施例を示すものである。FIG. 2 shows an embodiment in which the present invention is applied to level setting means in a semiconductor device.

この実施例では、＋５Ｖのような電源電圧ＶＤＤと一５
■のような電源電圧Ｖ８Ｂ　との間に、ポリシリコン等
からなるヒユーズＦとともに、例えばＰチャンネル形の
ＭＯ８ＦＦ３ＴＱが直列接続されている。そして、この
ＭＯ８ＦＥＴＱのゲート端子は、回路のグランドライン
ＧＬに接続されている。また、特に制限されないがヒユ
ーズＦの両端にはこれに電流を流して切断処理を行なう
だめのパッドＰ１　とＰ２とが接続されており、ウェー
７・の段階でこのパッドＰ、とＰ２にプローブを接触さ
せ、ヒユーズＦの両端に適当な電圧をかけて大きな電流
してやることにより溶断てきるようにされている。なお
、上記ヒユーズ回路を例えばＣ０ＤＥＣの電圧調整回路
用のレベル設定手段として用いる場合には、上記ヒユー
ズＦとＭＯ８ＦＥＴＱとの接続ノード！１の電位をイン
バータＩＶの入力１ｄ２圧とするように接続される。In this embodiment, a power supply voltage VDD such as +5V and a
A P-channel type MO8FF3TQ, for example, is connected in series with a fuse F made of polysilicon or the like between the power supply voltage V8B as shown in (2). The gate terminal of this MO8FETQ is connected to the ground line GL of the circuit. Further, although not particularly limited, pads P1 and P2 are connected to both ends of the fuse F to perform the cutting process by passing current through them, and probes are connected to these pads P and P2 at the stage of way 7. By bringing them into contact and applying an appropriate voltage to both ends of the fuse F to generate a large current, the fuse F can be blown out. In addition, when the above-mentioned fuse circuit is used as a level setting means for the voltage adjustment circuit of CODEC, for example, the connection node between the above-mentioned fuse F and MO8FETQ! It is connected so that the potential of 1 is the input 1d2 voltage of the inverter IV.

上記レベル設定手段においては、半導体装置の通常動作
時に電源電圧ＶＤＤラインに＋５■、ＶＳａジインに一
５ｖまたグランドラインＧＬにはＯｖのような電跡電圧
が供給される。そのため、上記Ｍ　０８　Ｆ　Ｅ　Ｔ　
ＱのゲートにはＯＶの電圧が印加されるので、オン状態
にされ、ヒユーズＦが切断されてい名ときには、ノード
ｎは電源電圧ＶＤＤ（＋５■）に近いレベルにされる。In the level setting means, during normal operation of the semiconductor device, trace voltages such as +5 V are supplied to the power supply voltage VDD line, -5 V to the VSa line, and Ov to the ground line GL. Therefore, the above M 08 F E T
Since a voltage of OV is applied to the gate of Q, it is turned on, and when fuse F is disconnected, node n is brought to a level close to power supply voltage VDD (+5).

またヒユーズＦが切断されていないときは、ノードｎは
電源電圧Ｖ８ｓ（−５Ｖ）に近いレベルにされるように
されている。このときＭＯＳＦＥＴ−Ｑおよびヒユーズ
Ｆに流される貫通電流を小さく（１０μ八以下に）する
ため、ＭＯ８ＦＢＴＱのゲート長を半導体装置内の他の
ＭＯＳＦＥＴよりも大きくしてＷ／Ｌ比を小さくするこ
とによってオン抵抗がＩＭ〜１０ＭΩ程度になるように
設定しである。Further, when the fuse F is not cut, the node n is set to a level close to the power supply voltage V8s (-5V). At this time, in order to reduce the through current flowing through MOSFET-Q and fuse F (to 10μ8 or less), the gate length of MO8FBTQ is made larger than other MOSFETs in the semiconductor device to reduce the W/L ratio. The on-resistance is set to about IM~10 MΩ.

従って、上記レベル設定手段においては、次のようにし
て上記ヒーーズＦの切断の有無を容易に検出することが
できる。すなわち、ウェーハの段階で電源パッドＰ　ｐ
　、Ｆ　Ｂ　＋　Ｐ　ｏ　にそれぞれテスト用のグロー
ブを当てて電源電圧を供給し、同じくヒユーズＦの両端
に接続されたパッドＰ、、１）、。Therefore, in the level setting means, it is possible to easily detect whether or not the heater F is disconnected in the following manner. That is, at the wafer stage, the power supply pad P p
, F B + P o with test gloves applied to supply power supply voltage, and pads P, , 1), which are also connected to both ends of fuse F.

にグローブを当ててその電位差を軌み取ればよい、この
とき、ヒユーズＦが切断されていれば電位差は＃′！！
はＩＯＶになるし、ヒユーズＦが切断されていなければ
電位差はほとんどゼロに近くなる。しかも、この場合上
記パッドＰ。に供給する電圧を、ＭＯ８ＦＥＴＱのゲー
ト・ソース間に印加される電圧Ｖ。ＳがこのＭＯ８ＦＢ
ＴＱのしきい値電圧Ｖｔｈよりも少し大きいＶｔｈ＋α
となるまで、相対的に上げてやる。すると、ＭＯ８ＦＥ
ＴＱのＶ。Ｓが＋５■とされる通常動作時のオン抵抗（
ＩＭ〜１０ＭΩ）に比べて、その抵抗値がかなり大きく
され、１００ＭΩ程度になるようにしてやることができ
る。All you have to do is apply a glove to the line and measure the potential difference.At this time, if fuse F is disconnected, the potential difference is #'! !
becomes IOV, and if fuse F is not cut, the potential difference will be almost zero. Moreover, in this case, the pad P mentioned above. The voltage supplied to MO8FETQ is the voltage V applied between the gate and source of MO8FETQ. S is this MO8FB
Vth+α slightly larger than TQ threshold voltage Vth
I will raise it relatively until it becomes . Then, MO8FE
V of TQ. On-resistance during normal operation when S is +5■ (
The resistance value can be made considerably larger than that (IM~10MΩ) to about 100MΩ.

そのため、上記の場合、ヒユーズＦの溶Ｑｊ［が不完全
で例えば１ＯＮ１０程度の高抵抗として存在していたと
しても、ｆＸＯ８ＦＥＴＱのオン抵抗が１００ＭΩ以上
にされることにより、ヒユーズＦの両端には、電源１ｉ
圧■ＤＤ−ｖｓｓ間をへａｏｓｐＥＴＱのオン抵抗とヒ
ユーズＩＩ′の抵抗の比で公開した１Ｖ程度のパ市泣差
が生じるため、容易にこの俗断不良状態を検出できるよ
うになる。Therefore, in the above case, even if the melting Qj[ of the fuse F is incomplete and exists as a high resistance of, for example, 1ON10, the on-resistance of the fXO8FETQ is set to 100MΩ or more, so that the voltage at both ends of the fuse F is power supply 1i
Since a voltage difference of about 1 V is generated between voltage DD and vss by the ratio of the on-resistance of aospETQ to the resistance of fuse II', this faulty state can be easily detected.

第１図のようにヒユーズＦと面外に抵抗比が接続された
回路では、ヒユーズＦがＭΩオーダの高抵抗としで存在
しでいると、これに流される電流を測定して切１１す１
の有無を検出する場合には、μＡのオーダの電流を測定
しなくてはならない。そのため検出が非？６に困難であ
ったが、上記実施例では大きな釦１位差を測定して検出
してやればよいので、顧めて容易かつ確実な検出が可能
となる。In a circuit where a resistance ratio is connected to the fuse F out of the plane as shown in Figure 1, if the fuse F exists as a high resistance on the order of MΩ, the current flowing through it is measured and disconnected.
In order to detect the presence or absence of , it is necessary to measure a current on the order of μA. Is that why detection is not possible? However, in the above embodiment, it is only necessary to measure and detect a large one-position difference between the buttons, which makes detection easier and more reliable.

なお、上記実施例において、ＭＯ８ＦＥＴＱのゲート端
子すなわち電源パッドＰ。に供給される電圧を、検出時
にＶｔｈ＋αまで上げてやる代わりに、電源パッドＰＧ
およびグランドラインＧＬの電位はＯＶに測定して、電
源パッドＰＤとＰ８に供給する電圧をそれぞれ■ＤＤ−
（Ｖｔｈ＋α）およびｖｓｓ　（Ｖｔｈ＋α）としてＭ
Ｏ８ＦＥＴＱのオン抵抗を高くさせ、Ｖ８Ｂ　（Ｖｔｈ
＋α）に対するノードｎの電位を測定してヒユーズ１−
の切断の有無を検出するようにしてもよい。In the above embodiment, the gate terminal of MO8FETQ, that is, the power supply pad P. Instead of increasing the voltage supplied to the power supply pad PG to Vth+α at the time of detection,
The potential of the ground line GL is measured to OV, and the voltage supplied to the power supply pads PD and P8 is
(Vth+α) and vss (Vth+α) as M
By increasing the on-resistance of O8FETQ, V8B (Vth
+α) and measure the potential of node n with respect to fuse 1-
Alternatively, the presence or absence of cutting may be detected.

また、上記実施例では回路のグランドジインＧＬの電位
を可変抵抗としてのＭＯ８ＦＥＴＱのゲートに供給して
、ゲート４位を相対的に変化させて抵抗値を変化させる
ようにしているが、例えば第３図に示すように、ＭＯ８
ＦＥＴＱのゲートに供給される二つの電位ｖ３．Ｖｂｅ
切り換えるスイッチＳを設けて抵抗値を変化させるよう
にね成するようにしてもよい。この場合、上記スイッチ
ご３は一対のＭＯＳＦＥＴによシ構成することができる
。Further, in the above embodiment, the potential of the circuit ground input GL is supplied to the gate of MO8FETQ as a variable resistor, and the resistance value is changed by relatively changing the gate 4 position. As shown in the figure, MO8
Two potentials v3. supplied to the gate of FETQ. Vbe
A switch S may be provided to change the resistance value. In this case, the switch 3 can be configured with a pair of MOSFETs.

なお、上記レベル設定手段ｒ、ＣＯＤ、ＥＣ等の基準電
圧発生回路用の電圧調整回路に使用する場合には、第４
図に示すように、おる程度ノく２ツキのある基準電圧ｖ
ｒｃｆを発生する基準電圧発生回路１から供給される基
準電圧Ｖｒｅｆを、正転増＠器をｔｉｆｆ成するオペア
ンプ２の非反転入力端子に入力させる。そして、第２図
もしくは第３図に示すようなレベル設定手段３を複数個
設けて、その設定状態によって、オペアンプ２の出力端
子とグランドとの間に設けた抵抗Ｒ，〜Ｒ□のいずれか
一つのノードのπＬ位を、ＭＯ８スイッチ８１〜Ｓｍに
よってオペフッ１２０反転入力端子に供給できるように
構成する。これによって止転増幅器におけるゲインｔ　
ｌｉｔ　？してやって安定した電圧を発生させ、Ａ／Ｄ
変換器もしくはＤ／Ａ変換器に基準電圧■ＩｔＥＦとし
て供給してやればよい。In addition, when using the above-mentioned level setting means r, a voltage adjustment circuit for a reference voltage generation circuit such as COD, EC, etc., the fourth
As shown in the figure, the reference voltage v has a certain degree of deviation.
A reference voltage Vref supplied from a reference voltage generation circuit 1 that generates rcf is input to a non-inverting input terminal of an operational amplifier 2 forming a tiff of a normal rotation amplifier. A plurality of level setting means 3 as shown in FIG. 2 or 3 are provided, and depending on the setting state, one of the resistors R, ~R The configuration is such that approximately πL of one node can be supplied to the inverting input terminal of the operating switch 120 by the MO8 switches 81 to Sm. This results in a gain t in the stopped amplifier.
lit? to generate a stable voltage, and the A/D
It is sufficient to supply it to the converter or D/A converter as the reference voltage ■ItEF.

なお、この発明は、上記レベル設定手段が上記のように
基準電圧発生回路の電圧調整回路に使用される場合のみ
ならず、メモリの冗長回路における回路切換手段もしく
はアドレス設定手段として、あるいはマスタスライスＬ
ＳＩや時計用ＬＳＩにおける回路切換手段等として使用
される場合にも適用できるものである。The present invention is applicable not only when the level setting means is used in a voltage adjustment circuit of a reference voltage generation circuit as described above, but also as a circuit switching means or an address setting means in a redundant circuit of a memory, or as a master slice L.
It can also be applied when used as a circuit switching means in SI or watch LSI.

〔効果〕〔effect〕

リークによる微少電流を測定することなく、ヒユーズの
切断・接続の有無により明確に決る電位差によるヒーー
ズの切断不良を検査する方式とした為、高信頼度のテス
トを行なうことができる。It is possible to conduct highly reliable tests because it is a method that inspects for fuse disconnection failures based on the potential difference that is clearly determined by whether the fuse is disconnected or connected, without measuring minute currents due to leaks.

第１の電源電圧ＶＤＤ　の端子と第２の電源電圧ＶＳＳ
の端子との間にヒーーズと可変抵抗とを直列接続させ、
ヒーーズの切断・接続状態によって接続ノードのレベル
を設定するようにしたので、ヒユーズの切断の有無を検
査するときには、上記可変抵抗の抵抗値を上げてやるこ
とによシ、ヒーーズが切断不良で高抵抗として存在して
いるときにはこのヒーーズよシも高い抵抗が直列に接続
された状態になるという作用で、ヒコ、−ズの両端に庄
する比較的大きな電位差を測定することによって、不完
全なヒユーズ切断状態を容易かつ確実に検出できるよう
になるという効果がある。The terminal of the first power supply voltage VDD and the second power supply voltage VSS
A heater and a variable resistor are connected in series between the terminals of
Since the level of the connected node is set according to the disconnected/connected state of the fuse, when inspecting whether or not the fuse is disconnected, it is possible to increase the resistance value of the variable resistor mentioned above. When the fuse exists as a resistor, a high resistance is connected in series with the fuse, so by measuring the relatively large potential difference across the fuse and This has the effect that the cutting state can be detected easily and reliably.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その渋旨を逸脱しない範囲で朴々変更可
能であることはいうまでもない。たとえば、電流による
溶断ヒユーズだけでなく、レーザによってトリミングす
るものその他にも適用できることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, it is understood that the present invention is not limited to the above-mentioned examples, and that changes can be made without departing from the spirit of the invention. Needless to say. For example, it goes without saying that the present invention can be applied not only to fuses blown by current, but also to fuses trimmed by laser.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となったオリ用分野である半導体装危におけ
るヒユーズを用いたレベル設定手段に適用した場合につ
いて説明したが、それに限定されるものではなく、ヒー
ーズを有するようなすべての回路においてその切断の有
無を検出する場合に適用できる。The above explanation has mainly been about the case where the invention made by the present inventor is applied to a level setting means using a fuse in the field of semiconductor packaging, which is the background of the invention, but it is not limited thereto. , it can be applied to detecting the presence or absence of disconnection in all circuits that have heats.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明者が本発明に先たち開発したヒユーズを
用いたレベル設定手段を示す回路図、第２図は本発明を
レベル設定手段に適用した場合の−ラＩす絶倒を示ず回
路図・ 第３図は本発明の他の実施例を示す回路図、第４図はレ
ベル設定手段を用いた電圧調整回路を含む基準電圧発生
回路の概略構成を示す回路構成図である。 ３・・・レベル設定手段、Ｆ・・・ヒユーズ、Ｑ・・・
可変抵抗（電界効果型トランジスタ、ＭＯ８ＦＢ’Ｉ’
）、ＩＶ・・・インバータ、ｎ・・・接続ノード。 第　１　図 第　４　図Fig. 1 is a circuit diagram showing a level setting means using a fuse, which the present inventor developed prior to the present invention, and Fig. 2 shows the overwhelming effect when the present invention is applied to the level setting means. FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 is a circuit configuration diagram showing a schematic configuration of a reference voltage generation circuit including a voltage adjustment circuit using level setting means. 3...Level setting means, F...fuse, Q...
Variable resistance (field effect transistor, MO8FB'I'
), IV...inverter, n...connection node. Figure 1 Figure 4

Claims (1)

【特許請求の範囲】 １、第１の電源電圧端子と第２の電源電圧端子との間に
ヒユーズと可変抵抗とを直列に接続し、上記ヒーーズの
切断・接続状態によって上記ヒ一ズと可変抵抗の接続ノ
ードの電位を設定するようにしたことを特徴とする采積
回路。 ２、上記可変抵抗として電界効果型トランジスタを使用
し、該トランジスタのゲート電位を切ｐ換えることによ
りその抵抗値を変化させるようにしたことを特徴とする
特許請求の範囲第１項記載のＭＳ偵回后も ３　外部から上記トランジスタのゲートに対して供給さ
れる電位を切シ換えるだめのスイッチを設けたことを特
徴とする特許請求の範囲第１項記載の県債回路。[Claims] 1. A fuse and a variable resistor are connected in series between a first power supply voltage terminal and a second power supply voltage terminal, and the fuse and the variable resistor are connected in series, and the fuse and the variable resistor are connected in series between the first power supply voltage terminal and the second power supply voltage terminal. A product circuit characterized in that the potential of a connection node of a resistor is set. 2. The MS rectifier according to claim 1, characterized in that a field effect transistor is used as the variable resistor, and the resistance value thereof is changed by switching the gate potential of the transistor. 3. The prefectural bond circuit according to claim 1, further comprising a switch for switching the potential supplied to the gate of the transistor from the outside.
JP12328483A 1983-07-08 1983-07-08 Integrated circuit Granted JPS6015946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12328483A JPS6015946A (en) 1983-07-08 1983-07-08 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12328483A JPS6015946A (en) 1983-07-08 1983-07-08 Integrated circuit

Publications (2)

Publication Number Publication Date
JPS6015946A true JPS6015946A (en) 1985-01-26
JPH0584062B2 JPH0584062B2 (en) 1993-11-30

Family

ID=14856754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12328483A Granted JPS6015946A (en) 1983-07-08 1983-07-08 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS6015946A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021145A (en) * 1987-11-12 1990-01-05 Honeywell Inc Fused state detector
JP2004265523A (en) * 2003-03-03 2004-09-24 Renesas Technology Corp Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5617059A (en) * 1979-07-20 1981-02-18 Fujitsu Ltd Semiconductor switching element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5617059A (en) * 1979-07-20 1981-02-18 Fujitsu Ltd Semiconductor switching element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021145A (en) * 1987-11-12 1990-01-05 Honeywell Inc Fused state detector
JP2004265523A (en) * 2003-03-03 2004-09-24 Renesas Technology Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0584062B2 (en) 1993-11-30

Similar Documents

Publication Publication Date Title
US7629802B2 (en) Semiconductor device including fuse and method for testing the same capable of suppressing erroneous determination
US7471101B2 (en) Systems and methods for controlling of electro-migration
US5525909A (en) Apparatus and method for measuring programmed antifuse resistance
JP3424489B2 (en) Semiconductor overcurrent detection circuit and its inspection method
JP2000206176A (en) Burn-in apparatus
JPH0394177A (en) Circuit for measuring resistance of test piece
JPH08271565A (en) Method for inspecting connecting state of power supply apparatus and power supply apparatus using method thereof
US20090039909A1 (en) Semiconductor device having contact failure detector
JPH1130649A (en) Semiconductor circuit testing method and testing device
JPS6015946A (en) Integrated circuit
EP1118867A1 (en) Method for testing a CMOS integrated circuit
JPH06258384A (en) Current measuring apparatus for integrated-circuit testing and integrated circuit
TW200301904A (en) Evaluation circuit for an anti-fuse
JP2007141882A (en) Semiconductor device, its testing device and method
JP2008140113A (en) Voltage regulator
KR19990037285A (en) Failure Rate Prediction Circuit and Method of Semiconductor Device
JP2589876B2 (en) Semiconductor integrated circuit device
JP3644168B2 (en) Semiconductor integrated circuit
JP2002156402A (en) Method and apparatus for inspecting characteristic of semiconductor element
JP4549320B2 (en) Semiconductor test apparatus, semiconductor test method, and semiconductor manufacturing method
JPH0336748A (en) Semiconductor integrated circuit device
JPH03229171A (en) Testing device for semiconductor device
KR950015176B1 (en) Ic tester
JPH0827307B2 (en) Printed wiring board test equipment
JPH01227467A (en) Semiconductor integrated circuit