JPS60156752U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS60156752U
JPS60156752U JP4292684U JP4292684U JPS60156752U JP S60156752 U JPS60156752 U JP S60156752U JP 4292684 U JP4292684 U JP 4292684U JP 4292684 U JP4292684 U JP 4292684U JP S60156752 U JPS60156752 U JP S60156752U
Authority
JP
Japan
Prior art keywords
insulating substrate
semiconductor equipment
semiconductor device
insulating
sealing material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4292684U
Other languages
Japanese (ja)
Inventor
茂 久保田
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP4292684U priority Critical patent/JPS60156752U/en
Publication of JPS60156752U publication Critical patent/JPS60156752U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

1第1図、第2図は夫々本考案の実施例のデュアルイン
型の半導体装置用パッケージの断面図である。 1.11・・・・・・封止材料、2,12・・・・・・
絶縁蓋部、3,13・・・・・・絶縁基板、4・・・・
・・段付き部、5.15・・・・・・外部リード、6,
16・・・・・・キャビティ、17・・・・・・テーパ
部。
1. FIG. 1 and FIG. 2 are sectional views of a dual-in type semiconductor device package according to an embodiment of the present invention. 1.11... Sealing material, 2,12...
Insulating lid part, 3, 13...Insulating substrate, 4...
...Stepped part, 5.15...External lead, 6,
16...Cavity, 17...Tapered part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)  半導体素子を固着した絶縁基板、封止材料、
外部へ導出するリードフレーム、絶縁蓋部を順次取付け
た半導体装置において、前記絶縁基板の底面側に段ある
いはテーパ部を設けて絶縁基板の巾を小さくした事を特
徴とする半導体装置。 、(2)前記絶縁基板に設ける段の高さは絶縁基板の厚
みの174〜1/2である事を特徴とする請求の範囲第
1項記載の半導体装置。
(1) An insulating substrate to which a semiconductor element is fixed, a sealing material,
1. A semiconductor device in which a lead frame leading to the outside and an insulating cover are sequentially attached, wherein the width of the insulating substrate is reduced by providing a step or a tapered portion on the bottom side of the insulating substrate. (2) The semiconductor device according to claim 1, wherein the height of the step provided on the insulating substrate is 174 to 1/2 of the thickness of the insulating substrate.
JP4292684U 1984-03-26 1984-03-26 semiconductor equipment Pending JPS60156752U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4292684U JPS60156752U (en) 1984-03-26 1984-03-26 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4292684U JPS60156752U (en) 1984-03-26 1984-03-26 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS60156752U true JPS60156752U (en) 1985-10-18

Family

ID=30554117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4292684U Pending JPS60156752U (en) 1984-03-26 1984-03-26 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS60156752U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5879739A (en) * 1981-11-05 1983-05-13 Toshiba Corp Sheath for semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5879739A (en) * 1981-11-05 1983-05-13 Toshiba Corp Sheath for semiconductor

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