JPS60154293A - Display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a display 1111 in a character image information system such as Telecoxt or Videotex.

Background Technology and Intervals - Points □ When a page is sent 1d in TV teletext broadcasting, in standard mode, as shown in Figure 1A, one page is composed of 248 dots horizontally x 204 dots vertically in each field. At the same time, 8 dots in the horizontal direction are displayed using 1 byte of display data.

In such television teletext broadcasting, the first
%! The 1st I! for the original inner (page) MN who would like to give up on IA! ! Inserting another image direction SB like Neo into QB and compositing, the result is a composite screen C as shown in Figure 1 C.
It is being considered to display MP. However, in this case, this inward compositing is performed using the video R for the original screen MN.
A video RAM for the inset SH is provided separately from the AM, and the signal from the other video RAM is combined with the signal from the original video RAM. Also, the size of the inset screen SB is 64 horizontal dots x 4 navy blue dots.
s dot, and the composition position of the embedded screen SH with respect to the original #Ii'IIIMN is arbitrary, but its initial position is specified by the transmitting side.

Therefore, for example, by displaying a car in the direction SH of the inset wA, and by sequentially shifting the timing of the display data of the inset screen SB on the receiving side, the horizontal position of the inset screen SH can be adjusted. If you change them sequentially,
The display appears as if a car is moving, and a simple video can be displayed.

However, in order to display such a composite screen CMP, two counters are required in the receiver to specify the horizontal and vertical positions of the embedded screen SH, and in addition, two counters are required to specify the horizontal and vertical positions of the embedded screen SH. Two counters are also required to form the signals and vertical address signals. Therefore, the receiver must control the 7IIIi direction using a large number of counters.
Moreover, since it is also necessary to control the peripheral circuits, the number of parts used increases, the manufacturing time of the receiver increases, and
: It becomes an I store, and it becomes "ζ". Also, it is less simple in terms of service.

Then, there is an output circuit which shares a counter for determining the horizontal and vertical positions of the inset inward SB and a counter for forming the horizontal address 1a4) and vertical address signal of the inward SH. I can think of it.

That is, FIG. 2 shows an example of this, and in this example, for a wI car, the inset I [I11 Mukagawa's video RA
A case where display data is read from M will be described.

In addition, as shown in Fig. 3, in the composite screen CMP
, from the left (A+1) dot, j and from the top (
B+1) Assume that the dot (reference point) in the upper left column of the inset image m1sB is located at the dot.

(2) in Figure 2 shows the video RAM 2 for the inset screen, which has a capacity of 28mm, but as usual in Figure 14, the lower address (address Bit)^Do~AD2 is the horizontal address, which is in the range of addresses 10''~``7'', and the upper address AD3~^l)6 is the vertical address, which is in the range of addresses 0~7.
63, and the remaining shaded area is unused. .

Further, (22) indicates an 8-bit precenter pull-up/down counter, and its preset inputs D^~DH are connected to the data bus (12) and latch (2) from the CPU (11).
13) Data r that determines the horizontal display position of the screen SH through
A-IJ is supplied, and the clock GK in which one cycle corresponds to one display dot is supplied to the clock GK, and the middle three bits Qs to Qs of the count output Qo"Qy are It is supplied to addresses ^Do to AD2 of the RAM (21).

Furthermore, (23) and (24) are decoders, and these are supplied with the output Qo''Qv of the counter (22) and the clock CI (Q) from the C decoder (23).

The output CZR, which becomes "1" when ~Q7 = "0" Φ, is taken out in synchronization with the clock GK, and the output CENn, which becomes "1" when Q o ~Q v ・= I-63J, is taken out from the decoder (24). is taken out after one cycle of clock Ct<, and these outputs CZR and CBNO are sent to the control signal forming circuit (
25).

This forming circuit (25) receives a control signal ENI3゜M, which will be described later.
It is for forming D, and therefore □ formation!
lI#i (25) is supplied with the horizontal 1.4-period pulse HD at clock C, and as shown in 5111A and 5111B, 1 clock before the start time t1 of the horizontal display period of page MN. A start signal ST that becomes "1" is supplied during the period toxt1. and ζ formation circuit (25)
The signal ENB from the counter (22) is supplied to the count enable manual ENB of the counter (22), and the signal MD is supplied to the counter (22).
) is supplied to the count mode human power υ/D, and R
AM (21) is supplied to the Au I/Put Enable Human Power OE. A signal ST is also supplied to the load input LD' of the counter (22).

Note that in the vertical direction, illustration and description are omitted, but the configuration is similar, and the clock CK and water 1V synchronization pulse HD are replaced by a horizontal synchronization pulse HD and a vertical synchronization pulse VD.

According to such a configuration, at the start time t1 of the horizontal display period of page MN, as shown in FIG. 5B, the signal S
Since T rises, the CPU (1
The horizontal position data 1'A-1,J from 1) is loaded into the counter (22), and as shown in FIG.
is preset to .

Furthermore, the signal ST falls at the time t1, thereby forming 1r! The signal ENB from path 1 (25) is triggered and ENB="1" at time t1, as shown in the fifth diagram. Furthermore, at this time t1, as shown in FIG. 5E, MD="0", so the counter (22) is in the downcount mode due to this signal MD.

Therefore, the counter (22) starts with the clock CK from time t1.
Start counting 0 on the evening of , and the count value Q.

~Q7 decreases by 1°l'' every clock from tA-'IJ.

Then, when Qo = Qv = l' OJ at time L2, this is detected by the detector (23), and CZR- becomes "1" at time t2, as shown in Fig. 5F, and this signal CZR is supplied to the formation circuit (25), so MD="1" at time t3, one clock after time L2, synchronized with clock CK L2.

Therefore, the counter (22) enters the up-counting mode from time t3, and the count value QO-"Qt increases by 11" every clock from "0".

Then, when Qo = Qt-163J at time t4,
This is detected by the decoder (24), and as shown in FIG.
ms+cypi. 94 U, 13°5.96, □wa, o,
8. (All signals are reset at time t5, one clock after time t4 in synchronization with clock GK, and ENB
= ``0'', MD - If it becomes ``O'', the state is λ.
Ku.

In this case, the middle three bits Q3 to QsA of the count value Qo''Qt (horizontal address signal ^
Unlike the signal MD supplied as Do~^D2, the signal MD is supplied to the RAM (21) as the output enable input OE, so that the signal MD is supplied as the output enable input OE during the period t3~ts.
(21) 17) The display data of horizontal pixels m2'ADo'2 and AD3 can be sequentially displayed one byte at a time every 8 clocks. The period t1 to t3 corresponds to the horizontal section of the A dot in FIG. 3, and the period t3 to t6 corresponds to the screen SH in FIG.
It corresponds to the horizontal interval of .

Therefore, similar processing is performed in the vertical direction, and the RAM (
If the outer thread data from 21> is synthesized with the outer leather data from RAM' (1B), a composite screen CMP shown in FIG. 3 or FIG. 1C is displayed.

For example, as shown in FIG. 6, there are some item numbers where the inset screen SB protrudes from the composite screen CMP, but the screen SB is The reference point (upper left dot) of screen SB can be set to screen εMP as shown in
In the case where the data protrudes by A dot in the direction of difference from If the reference point protrudes upward from the inner surface CMP, the same process can be performed by moving it vertically.

In this way, according to the 2111th readout circuit, it is possible to read out the inset screen sBi representation, but
In this case, in particular, according to this readout circuit, the number of components such as the counter and the peripheral circuit, which also serves as a counter that specifies the horizontal position of the inset P4 surface SB and a counter that forms the horizontal address signal, can be reduced. It is possible to reduce the manufacturing time and reduce the number of coats. Furthermore, simplicity can be put to practical use in services.

By the way, the actual table is 11 times RAM (21
) 0, the readout circuit not only continues reading, but also requires the CPU (11) to write (and read) display data into the RAM (21).
Display data access to AM(2]) is performed by the reading circuit shown in FIG. 2 and the CPU(11) in a time-sharing manner. However, if this time division processing is performed, the peripheral circuits of the 21st R1 readout and the 7th circuit will become complicated.

That is, the output Qo''Qv of the counter (22) is
It changes as shown in Figure B (Figure 7A).

B is the same as FIG. 5A and C), bits Q3 to Q6 supplied to RAM (21) as a read address are:
As it changes to Neo in Figure 7 C, there is a beep) Qo””
Q2 has changed as shown in No. 71g1D. Then, each time the bits Q3 to Q5 change (every 8 cycles of the clock CK), the leather data is read out from the RAM (21) one byte at a time.

Therefore, in order for the CPLJ (11) and the continuation circuit to access the RAM (21) in a one-division manner, as shown in FIG. Of these, the first four clock periods τ1 are C
The period during which the PU (11) can access the RAM (21) is defined as the period during which the PU (11) can access the RAM (21).
M(2]) is the access period.

However, in this case, as shown in the 71st RID, the value of the output bit Qo-02 of the counter (22) is 1' 7 J - [4'' in the period τ1 before time t3.
13''~l'OJ' in 2 periods τ2? ? On the other hand, after time t3, the period τ1 is 13'' to 10''.

In period τ2! 71 to "4", and the value of bit Qo"(:12 and CPtJ(11) before and after Jpot3
The relationship between 'r access and the reading circuit is reversed.

Therefore, when the CPU (11) and the readout circuit access the RAM (21) in a time-sharing manner, the counter (22
), output bits Qθ~Q2 of CPU (11
) cannot be used to control the access period of (flaws,
Bit Q o = Q 2 is further processed and used from ζ) t
jL must be. Therefore, when the second IgJ readout circuit is applied to an actual display circuit, the surrounding area! IV
1! becomes complicated.

The object of the present invention is to solve and solve these problems.

Summary of the invention Now, in the readout circuit of the 21st gl, the counter (2
2), the complement of the output bit QO''Q2 (complement of [l''), Qo=Q2, is shown in FIG. 7F. Therefore, a 3-bit counter is provided and the time t
1 is loaded with the complement of data rA-IJ, and thereafter the clock CK is counted up, the count output Yo=Y2 becomes as shown in FIG. 7G.

Then, the value of this count output YONY2 and R1^M
Looking at the relationship between the CPU (11) and the readout circuit's access to (21) (Fig. 7E), this
The same applies before and after 3.

On the other hand, when reading out the display data from (21) by addressing 3 Z by the output Qo''Qv of the counter (22), only bits Q3 to Q6 are used, as shown in FIG. 7C. is used as the continuation address, and bits Qo to Q2 are unnecessary.

First, bits 03 to Q5 of this continuation signal change when a borrow output or a carry output is output from the bit Qo = Q2 (D in Figure 7), which is Q This is also the time when a carry output of force Yo to Y2 is output.

Therefore, in the present invention, the counter (22) is divided into an up counter for the lower 3 bits Qo7Q2 and an up/down counter for the upper 5 bits Q3 to Q7.

Then, at time t1, the complement of the lower 3 bits of data FA-IJ is loaded into the 3-bit up counter, and the upper 5 bits of data rA-, IJ are loaded into the rotary 5-bit up-down counter. 7. Afterwards, the 3-bit counter counts up the clock CK, and the 5-pit door knob down counter counts down the carry output of the 3-bit counter (before time t3) and counts the amplifier (time t3 Jffl&). .

Therefore, from the 3-bit up counter, the output Y o = Y 2 is obtained as shown in FIG. 7G, which is obtained at time t3J.
Since it changes uniformly both before and after U, this output Y
The access timing of CPtJ (11) can be detected from o-%-Y2.

Note that, as shown in Fig. 6, if the reference point of the inset screen SB protrudes to the left of the composite screen CMP, the -F-order 3 bits and the upper 5 bits of data IAJ are directly input to each counter. Just load it and count up.

Further, 'ζ in the vertical direction may be processed in the same way.

Embodiment In FIG. 8, the counter (22) is divided into a 3-bit presettable up counter (221) and a 5-bit presettable up counter (222).
Similarly, the latch (13) is also a 3-bit latch (131).
and a 5-bit latch (132).

1 and from CPIJ(II) to data I') o ”
D? Among them, the lower 3 bits DO"D2 connect the exclusive OR circuits (30) to (32) for 4 complements to 1fr.
The latch output is supplied to the inputs D^~Dc of the latch (131), and the latch output is supplied to the preset inputs D^~Dc of the counter (221), and the data D o '' D from the CPU (11) Top 5 hints D3 among v
~D7 is supplied to the human power D~Dw of the latch (132), and its latch output D3~D7 is supplied to the preset input DA-[)Ig of the counter (222). in this case,
The data Do"Dv from the CPU (11), as shown in FIG.
If it is within the MP, the value is rA-1, and if it is outside the same number on the left, it is the value 1-A.

In addition, the latch signals PLCH and MLCH are connected to the OR circuit (33
) is supplied to the latch clock CK of the latches (131) and (132), and the signal PLCII is supplied to the exclusive OR circuits (30) to (32). 1 In this case, the signal P1. CH is fitted as shown in Figure 1C, and the reference point of the inward SB is synthesized wBiIIICM
If it is within P, data Do7 from CPU (11)
Dv, Zunasechi, data IA-j, latch J (131
,).

(132) is a latch signal that becomes "1" when the signal MLCH is latched, and as shown in FIG.
When the reference point B protrudes to the left of the screen CMP, when latching the data Do"Dt, that is, the data rA, l to the latch (131),
PLCH is a latch signal, and any latch signal PLCH
, MLCH are also formed based on the output of the CPU (11).

The clock CK is a counter (221).

(222), and the carry output CR of the counter (221) is also supplied to the count enable manual ENB of the counter (222).

Further, count outputs Yo to Y2 of the counter (221) are supplied to the memory control circuit (34). This control circuit (
34) is a read signal when reading display data from the RAM (21), a write signal when the CPU (11) accesses the RAM (21), etc.7.16 is formed at the same timing as in Figure 7. This is a circuit that does this.

Therefore, the control circuit (34) further includes a CPU (11).
) to memory request signal MREQ, write signal WR
, the upper 13 bits of the address signal A3-A16, etc. are also supplied to form a read signal RD and a write signal WR of the RAM (2), and are supplied to the RAM (21).

Furthermore, the output (output terminal) of the counter (222) Q^~Q
Bits Q3 to Q6 are extracted from c, and this bit Q3
~Q6 are supplied to the A input of the selector (35), and lower three bits An~A2 of the address signal of the CPU (11) are supplied to the B input of the selector (35).

Then, in the control circuit (34), the signal Y o ”!
Based on Y2 and clock CK, as shown in FIG.
5), and the selector output Y is Y=A when s=“o”.

When “l”, Y=B is controlled, and the output Y is stored in RAM (
21) is supplied to address human power ^Do~^o2.

Also, data (display data) DO from the CPU (11)
"DT is RAM (21) data manual Dlo"Of
to (1 (paid).

In addition, although not mentioned above, circuits (23) to (2) in Figure 2
A circuit similar to 5) is provided, including a counter (221).

The up-count/down-count mode signal MD of the counter (222) and the count enable signal ENB of the counter (221) are formed and supplied from the outputs Yo''Y21 Q3 to Qr of the counter (222).

Further, the signal ST is also supplied to the load input LD of the counters (221) and (222>).

According to such a configuration, as shown in FIG.
-IJ's 3rd bit DO-D2 is inverted in the exclusive OR circuits (30) to (32) and the complement D
o'' D2, and this is latched in the latch (131). Also, the upper 5 bits D3 of data rA-IJ
~D7 is latched as is in the latch (132).

Then, at time t1, signal ST (FIG. 5B) causes complement bits Do to D2 to be loaded into the counter (221), and bits D3 to D7 to be loaded to the counter (222). Subsequently, the counter (221) increments the clock CK by °(, signal '1 =)ENB (D in Figure 5), and the counter (221) outputs the count output Yo~Y2 as shown in Figure 7G. is obtained.

Also, when counting up, the count output is Y.

~ Every time Y2 carries, the carry output CR of the counter (221) becomes 6111, and at this time, the counter (222)
is allowed to count, the counter (222) counts down the clock GK and outputs the count output Q3.
~Q7 is count output Y.

It is decremented by 11 for each carry of ~Y2.

Then, at time t2, Yo = Y2 = r 7
J.

Q3~Qt=rOJ Kfl&(DT!, CZR=
”l, 1 (Fig. 5F), followed by MD at time t3.
-1'''9 (FIG. 5E), the counter (222) enters the up-count mode, and counts up the clock CK every time the count output Yo=Y2 is carried.

Then, at time t4, Yo = Y* = r' OJ,
When Qa~Qv=r7J, CIEND=″1″
(Fig. 5G), and at the next time t6 ENB="0"
”.

MD="0", CHND="0" (5th drawing, B
, G).

On the other hand, as shown in FIG. 6, when the inset screen SB protrudes to the left of the composite screen CMP, the latch signal MLCH becomes "1" and PLCII-0''.
The lower three bits DO-D2 of data rAJ are latched as they are in the latch (131) without being inverted in the exclusive OR circuit (33), and the data l''A
The upper 5 bits D3 to D7 of J are also latched (13
2) is latched. Then, at time t1, the latched bits DO~D21D3~D? are loaded into the counters (221) and (222), and from now on, these counters (221).

1 0 (222) both count up, and from then on, the first
This is the same as after time t3 in the case of FIG.

Then, the 111th! In the case of IC and in the case of Figure 6,
In parallel with the above operations, the address signals An to A2' of the CPU (11) and the outputs Q3 to Q6 of the counter (222)
and the RAM (21) in a time-sharing manner through the selector (35).
), and the write signal WR and read signal RD are also supplied to the RAM (21), so the CPU (11) can write display data to the RAM (21) during the period τ1, and the display data can be written to the RAM (21) during the period τ2. The readout circuit can extract the display data. That is, the CPU (11) and the readout circuit operate during the period τ1. RAM (
21) can be accessed.

This time-sharing type access is performed by the count output Yo
~Y2 is used for timing, but since this count output Yo/%-Y2 is always changing in the increment direction as shown in Fig. 7G, this output Yo xY
The time division timing can be easily detected based on z.

2 Thus, according to the present invention, the time division timing for the RAM (21) can be easily detected.

In addition, in the above, the exclusive OR circuit (30
) to (32), the counter (221) and the control circuit (34)
), and in the case of FIG. 1C, a counter (221) may be used to count down during the period t1 to t3.

Effects of the Invention When the CPU and the readout circuit access the video RAM for moving images in a time-sharing manner, the timing can be easily detected.

[Brief explanation of the drawing]

1 to 7 are diagrams for explaining this invention, and FIG. 8 is a system diagram of an example of this invention. (21) is a video RAM, (34) is a memory control circuit,
(221) is a presetter pull-up counter, (222
) is a presettable up/down counter. 23. 679- JP-A Sho GO-154293 (8) JP-A Sho GO-154293 (9) IHHILI 4th

Claims (1)

[Claims] 'The display data written in the display memory is read out corresponding to horizontal and vertical scanning, and the read display data is supplied to the picture tube and sent to the display circuit where it is displayed as an i-page image. Then, the first counter counts clocks (or horizontal period pulses) for each horizontal scan (or vertical scan), and the second counter counts the clocks (or horizontal period pulses) separately for each carry or carry-down output of the first counter. When the first and second counters count by a predetermined value, this is detected from the decoder ratio, and after this detection output is obtained, the count output of the second counter is used for the display. Addressing a display memory different from the memory to read different display data, and inverting the preset input or count output of the first counter to obtain a detection output to the decoder, either before or after the time. A count output that uniformly changes in an incremental direction or a digital direction is obtained, and this count output is used to read out the above-mentioned different leather data to the display memory for each record, and to read out the above-mentioned different table data using cpum. A display circuit that obtains the timing for time-sharing processing of data access.