JPS5865477A - Large integrated circuit for display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generates a video signal for displaying characters such as a channel number and time on a display device such as a cathode ray tube (CRT), and also makes switching between these displays extremely efficient. The present invention relates to a large-scale integrated circuit for display that can be performed in a variety of ways.

In recent years, efforts have been made to add various functions to television receivers, and as mentioned above, television receivers with functions that can display channel numbers, time, etc. on specific parts of the screen are now available. It has come to fruition.

FIG. 1 is a diagram showing the state of the screen and its display principle when the time, for example, 12:36 (12:35) is displayed, and the time display starts from the nth scanning line,
As shown in the figure, the time of 12:36 is displayed on the screen.

Figure 2 shows two scanning lines and two oscillation output pulses (PO8C).
Conventional large-scale integration for CRT display, in which 1 dot is composed of pulses, 1 character is displayed with 6 x 7 dots, and 1 line is made up of X characters, and the entire display is made up of Y lines. It is a block diagram showing the circuit configuration of the circuit,
As shown in the figure, the oscillation circuit section consists of an inverter, a NAND circuit, and a capacitor.
RS flip-flop 3', hexadecimal counter 4. X-ary counter 6, number memory 6, n-ary counter 7, RS flip-flop 8, hexadecimal counter 9. Y-ary counter 10
It consists of a one character generator (read only memory) 11.degree. output circuit 12 and a NOR gate 13. Note that 14 is a terminal to which a vertical synchronizing signal is applied, 16 is a terminal to which a horizontal synchronizing signal is applied, -, 16 is a terminal to which data is input, and 17 is a terminal to which a signal to the video circuit is output. .

By the way, when the display illustrated in FIG. 1 is performed under control by a large-scale integrated circuit having such a circuit configuration, since one line has six characters, the X-adic counter 5 is constituted by a hexadecimal counter. On the other hand, since the number of displayed lines is one, the Y-adic counter 1o is not necessary. Therefore, the Y-adic counter 10 in the circuit shown in FIG. 2 is removed, and the overflow output terminal OVF of the hexadecimal counter 10 and the clear terminal CLR of the RS flip-flop 8 are directly connected.

The large-scale integrated circuit for CRT display having the configuration described above performs the following operations.

(1) Data to be displayed on the television receiver is sent to terminal 1.
6 to number memory 6.

? ) N-ary counter 7, RS flip-flop 8
All hexadecimal counters are also cleared, and the output from the output terminal 17 to the video circuit is disabled.
).

(3) When the horizontal synchronization signal is input after the vertical synchronization signal disappears, the n-ary counter 7 performs a counting operation, and when the horizontal synchronization signal is input n times, it overflows and sets the RS flip-flop 8. .

Then, a vertical display state is established by the cent of the RS flip-flop 8.

(4) When the horizontal synchronization signal is input, m-ary counter 2,
The RS flip-flop 3, the hexadecimal counter 4', and the hexadecimal counter 5 are all cleared.1. Initialization is performed regarding the horizontal display. As a result, the display is rendered invalid. Furthermore, the oscillation of the oscillation circuit section 1 is also stopped.

(5) When the horizontal synchronization signal disappears, the oscillation circuit section 1 starts oscillating and outputs a signal at a predetermined frequency.

(6) The output signal from the oscillation circuit section 1 is input to the m-ary counter 2, and the m-ary counter 2 overflows due to the arrival of m oscillation output pulses, and the RS flip-flop 3 is set. When both RS flip-flops 3 and 8 are set, only the portions that are enabled both vertically and horizontally will be displayed.

FIG. 3 shows the character generator 11 when the above display is made.
output A and hexadecimal counter 4 and hexadecimal counter 9
FIG.

(a) Read the data addressed by the hexadecimal counter 6 and the contents of the character generator 11 addressed by the hexadecimal counter 4 and the hexadecimal counter 9, and output them to the output circuit 12. It is output to the video circuit via the output terminal 17. That is, in the initial state, the quinary counter 6 addresses the first data 1, and as shown in FIG. The counter 4 addresses the leftmost dot among the six dots in the horizontal direction. At this time, there is no character output from the character generator 11 as shown by the broken line.

(8) The hexadecimal counter 4 executes a counting operation upon receiving the oscillation output pulse from the oscillation circuit section 1, and obtains an output corresponding to the address from the character generator 11.

In the example shown in Figure 3, there is no output in the period from 0 to 3.
There is a character output in the period 4 to 6, and there is no output in the period 6 to e. Note that the period 10 to 11 corresponds to the interval between adjacent characters, and there is no output to the video circuit during this period, regardless of data.

(9) When hexadecimal counter 4 overflows, hexadecimal power,
1 is added to the counter 6, and 2 is addressed to display the next data in the numeric memory 6, 12:36. Thereafter, the video signal is output in the same manner, and a display signal output of six characters corresponding to one scanning line is obtained. and,
When display signals for six characters are output, the quinary counter 6 overflows, the character generator is rendered invalid, and there is no -off display signal.

(10) Next, when the horizontal synchronization signal is input, 1 is added to the hexadecimal counter 9, and the above-mentioned operations (5) to (9) are repeated, and 6 characters are added to the next scanning line. Outputs a minute display signal. Thereafter, scanning is performed sequentially in the same manner, and the display ends when the hexadecimal counter 9 automatically flows.

FIG. 4 is a diagram showing the relationship between the CRT display, the scanning scan, and the output of the character generator 11, which have been explained above.
As shown in Figure (a), the display (12-36) is performed in the scanning period from the nth scanning line to the n+13th scanning line. In addition, FIG. 4(b) shows the horizontal synchronizing signal (H),
Fig. 4(c) shows the output (O20) signal of the oscillation circuit section 1ync, Fig. 4(d), (e), (
f) is the nth, n+1. This is a timing chart showing the relationship with the output signal of the character generator 1 at the time of the (n+2)th scan. At the n+1th scan, 1, 2, 3
．． There is a character signal output in the character generator 11 at the position corresponding to the 4th character of 6, and a character signal output is still generated at the position corresponding to the 5th character of 12:36 at the n+2th position, as shown in Fig. 4 (-). The time is displayed as 12:35. Note that the display based on the output signals shown in FIGS. 4(b) to 4(f) assumes that a white display is made on the screen when the video circuit is at the ground level. That is, in the circuit of FIG. 2, from the character generator 11 to FIG. 4 (dL (8),
When the grammar signal output of the high level to Hn shown in f) occurs, the transistor which is the constituent element of the output circuit 12 becomes conductive, and the level of the terminal 17 becomes the ground level, thereby selectively grounding the video circuit. level. By the way, when the output signal level of the character generator 1'1 is at a low level °'L'', the transistor is cut off and the video circuit is not affected in any way, and the image being received is displayed.

Furthermore, while the character generator is disabled, the character generator outputs I and JT levels regardless of the address and operates so as not to affect the screen.

Figure 4 (q) is the vertical synchronization signal (v), and (h) is the water! ! 7nC flat synchronization signal (H), same (i) r-z character signal output yn
c (CHAR) time relationship, same 0) is horizontal synchronization signal (H)
, (k) is a diagram showing the relationship between the display and the character signal output sy%C (CHAR), and V and H8g7
The relationships other than n0 7nC are as shown in FIGS. 4(b) and 4(C).

A conventional large-scale integrated circuit for CRT display has the above-mentioned configuration and executes the dynamic behavior of displaying the time and the like on the screen. Incidentally, although the display by such a conventional large-scale integrated circuit for CRT display is performed in terms of time or channel, the number of characters displayed is about 10 at most.

However, as television receivers and video tape recorders have rapidly become more sophisticated, it has become necessary to display a large number of characters, far exceeding the 10 or so characters mentioned above.

Figure 6 (-) and (b) are CRTs used in home video.
This shows an example of the display. FIG. 5(a) shows an example of inputting or confirming a program.

The meaning of the screen is program 1 out of many programs.
(PROG 1) starts recording channel 10 on a VTR at 10:46 (ON TIME 10:45) on Sunday (SUN), and starts recording at 11:30 (OFF TIME).
11:30) to end recording. Figure 6(b) is an example of displaying the contents of the tape counter of a VTR, and shows that program 1 (PROGl) is recorded in the tape counter 30oo to 6600.

Although the two types of screens have been described above, in reality, several other types of displays are required, such as displaying the remaining amount of videotape and simply displaying time.

11 Next, a case in which the screen shown in FIG. 6 is displayed using a conventional method will be explained. FIG. 6 shows an example of the configuration of the data memory 6 according to the conventional method. By inputting data to the data input terminal 16, a write address, write data, A write signal is generated and data corresponding to FIG. 6(a) is written into the display data RAM 19. The state at this time is shown in FIG. Also shown in FIG. 7 are RAM addresses consisting of an X address (3) and a Y address (7).

In Figure 7, the parts where characters such as °゛P'' and tRn are written have the corresponding codes written in the RAM, and the other parts have codes written in the RAM to suppress the display. It shows that

Next, from the data input terminals 20 and 21, the X-ary counter 6, Y
The data of the decimal counter 1o is input to the display RAM 19, and the contents of the RAM are sequentially read out to the output line 22 according to the value, and a CRT display signal is generated via the character generator 11. However, in the conventional configuration example shown in FIG. 6, in order to display one screen, it is necessary to transfer a large amount of data corresponding to a total of 80 characters (16×6). Furthermore, as mentioned above, as equipment becomes more sophisticated, it becomes necessary to frequently switch between several types of screens. On the other hand, in order to produce equipment at low cost,
It is essential that the above control be performed by, for example, a 4-bit, 1-chip microcomputer.

Considering this point of view, using the conventional method, in order to change the display screen frequently, it is necessary to transfer a large amount of data, which reduces the processing speed or the number of program steps required. A great inconvenience arises from this point of view.

The present invention was made with the intention of eliminating such inconveniences. When displaying characters on a CRT, the types of screens to be displayed are limited to a few for certain applications such as VTR televisions and video discs. Furthermore, we focused on the fact that most of each screen consists of a common basic screen, and that display is achieved by placing necessary information in a removable form in a part of that basic screen. Large-scale integration 3 The circuit has a built-in memory in which data for one or more basic screens is written, and a RAM that is addressed by this memory and stores data related to the above-mentioned variable information.
The object of the present invention is to provide a large-scale integrated circuit for CRT display in which data transfer associated with changes in RT display is kept to a necessary minimum.

The present invention will be described in detail below with reference to the drawings. First, the basic screen will be explained using FIG. 8. Figure 6 (-) is an example showing the state of the program;
The screen shown in the figure is obtained by adding a variable part whose display content changes based on data corresponding to the program content to the hatched dotted line frame part, that is, the basic part that remains unchanged except for the variable part. At this time, the data of the basic part is 66 out of the total data of 80, while the number of variable parts that change depending on the program is 14, which shows that the number of data in the basic part is overwhelmingly large.

FIG. 9 shows an example of the configuration of a data memory section according to the present invention.

The display according to the present invention will be explained. First, data in the basic screen memory is prepared in advance, and will be explained using the example shown in FIG. X in the diagram.

Y indicates an X address and a Y address, and ■ to ■ correspond to a variable part, and this part stores an address code specifying the address of the variable part memory where the data of the variable part is stored. The data indicated by (1) to (0) is the data to be displayed. Further, the basic screen memory may have only one screen or several types of screens, and one of them may be selected by the basic screen memo recovery control circuit.

Next, the data of the variable part is stored in the variable part memory 26 via the RAM control circuit 18 in response to a signal from the data input terminal 16. At this time, the address where each data is stored corresponds to the position specified in advance when preparing the basic screen. With this kind of configuration, it is possible to specify a fixed location of the variable part based on the basic screen, especially for data that is used redundantly on several types of screens, so there is no need to have duplicate data in the variable part. RAM can be used very efficiently.

16 FIG. 11 is an example of the contents of the variable section memory. A case will be described in which the data is displayed after preparation of the data in the variable memory as shown in the figure is completed. First, the X-base counter output and the Y-base counter output are input to the data input terminal 20.
By adding from 21, the basic screen memory 24 is designated. X at L/s = O-4, Y 7 )' 1
/S=O(7)H'' The data of PROG-17 is read from the basic screen memory 24.

Since this is data and not a code specifying the variable section memory 26, the data switching control path 26 directly outputs this data to the output a22.

Next, when the X address becomes -6 and the Y address becomes -0, the basic plane memory 24 outputs a code specifying the address (2) of the variable section memory 26. This code immediately specifies the address ■ of the variable memory 26, and the variable memory 26
6 outputs data corresponding to the content II 1.7+ of address ■. On the other hand, the data switching control circuit 26 controls the output of the basic screen memory 24 to the variable section memory 26 at this point.
is detected and operates to output the output of the variable section memory 26, that is, the data "1" to the output line 22.

Next, 1 is added to the X address, making the X address = e and the Y address - 0. This time, from the basic screen memory, I-
II (Display suppression for one character) data is output, so the data switching control circuit 26 switches from the variable section memory 26 to the basic screen memory 24, and the data of "-" is output to the output line 2.
2 is output.

Thereafter, similar operations are performed, and the incomplete data stored in the basic screen memory 24 and the variable section memory 26 is output. That is, even by using the data memory 6 having the configuration shown in FIG. 9, the display shown in FIG. 5 can be obtained.

By the way, when considering the transfer of data necessary to perform the above display, in the conventional case it was necessary to transfer 80 characters of data, but when the present invention is adopted, the variable memory 26 It is only necessary to transfer data for the contents of , that is, 14 characters, and the amount of data transferred is significantly reduced.

Next, the basic screen memory 24 will be explained. The main screen memory 24 can be configured with RAM or ROM. When using RAM, there is a method of writing data in the basic screen memory all at once when the power is turned on, and then using it as read-only memory.
When using OM, basic screen data required for each application may be written in advance. When implementing semiconductor integrated circuits, ROM memory occupies a fraction of the area of the semiconductor substrate compared to RAM memory, so for applications that require multiple basic screen memories, the basic screen memory is configured with ROM. If so, the advantages of ROM memory can be fully utilized.

As is clear from the above explanation, the CR of the present invention
The large-scale integrated circuit for T display can keep the transfer of display data to the minimum necessary and can realize an extremely efficient CRT display.

[Brief explanation of the drawing]

゛Figure 1 is a diagram showing the state of the screen and its display principle when a predetermined time is displayed, and Figure 2 is a diagram showing the circuit configuration of a conventional large-scale integrated circuit for CRT display 8 for displaying 6 characters. Figure 3 shows the relationship between the output of the character generator and the hexadecimal and hexadecimal counters when a display is made; Figures 4 (-) to (4 are CRT displays, scanning lines;
A diagram showing the relationship between the horizontal and vertical synchronizing signal 9 oscillation outputs and the character generator output, Figures 6(a) and 6(b) are diagrams showing display examples, and Figure 6 is the configuration of the data entry memory according to the conventional method. A diagram showing an example, FIG. 7 is a display R using the conventional method.
A diagram showing an example of AM data, Figure 8 is an explanatory diagram of the basic screen,
FIG. 9 is a diagram showing an example of the configuration of the data memory according to the present invention, FIG. 10 is a diagram showing an example of the contents of the basic screen memory, and FIG.
The figure is a diagram showing an example of the contents of the variable section memory. 11...Character generator, 12+...External output circuit, 14...Vertical synchronization signal application terminal,
16...Horizontal synchronization signal application terminal, 16...
Data input terminal, 17...Signal output terminal, 18.
...RAM control circuit, 19... RAM for display data, 2o... terminal to which the X-base counter output is applied, 21... terminal to which the Y-base counter output is applied, 22... Data memory section output line, 23...
...19 Basic screen memory control circuit, 24... Basic screen memory, 26... Data switching control circuit, 26...
...Variable part memory. Name of agent: Patent attorney Toshio Nakao and one other person II
Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Section

Claims (1)

[Claims] (1) A first memory that stores one screen of display data consisting of basic screen data and variable screen data, and a rewritable second memory that is addressed by the variable screen data of the first memory. and a circuit section that uses the data output from the data memory section as display data, and the data memory section includes a data memory section that includes a memory and a control circuit that controls these, and a circuit section that uses the data output from the data memory section as display data. A large-scale integrated circuit for display comprising basic screen data output from a first memory and variable screen data output from a second memory addressed by the first memory. 2.) A large-scale integrated circuit for display according to claim 1, wherein the first memory comprises a read-only (ROM) memory. (3) The display large scale according to claim 1, wherein the control circuit is composed of a first memory control circuit, a second memory control control circuit, and a display data switching circuit. Scale integrated circuit.