JPS5865479A - Large integrated circuit for display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] The present invention generates a video signal for displaying characters such as channel number 2 poem engraving display on a display device (CRT) such as a cathode ray tube, and moreover, it greatly facilitates switching of these displays. The present invention relates to a large-scale integrated circuit for display that can be efficiently performed.

In recent years, efforts have been made to add various functions to television receivers, and as mentioned above, television receivers with functions that can display channel numbers, time, etc. on specific parts of the screen are now available. It has come to fruition.

FIG. 1 is a diagram showing the state of the screen and its display principle when the time, for example, 12:36 (12:36) is displayed, and the time display starts from the nth scanning line,
As shown in the figure, the time of 12:35 is displayed on the screen.

Figure 2 shows two scanning lines and two oscillation output pulses (PosC).
Conventional large-scale integration for CRT display, in which 1 dot is composed of pulses, 1 character is displayed with 6 x 7 dots, and 1 line is made up of X characters, and the entire display is made up of Y lines. It is a block diagram showing the circuit configuration of the circuit,
As shown in the figure, an oscillation circuit section 1 consisting of an inverter, a NAND circuit, and a capacitor, an m-ary counter 2,
RS flip-flop 3. Hexadecimal counter 4, X-base counter 5, numeric memory 6, N-base counter 7, RS flip-flop 8. Hexadecimal counter 9, Y-base counter 10. It consists of a character generator (read-only memory) 11, an output circuit 12, and a NOR gate 13. In addition, 14
16 is a terminal to which a vertical synchronizing signal is applied, 16 is a terminal to which data is input, and 17 is a terminal to which a signal to the video circuit is output.

By the way, when the display illustrated in FIG. 1 is performed under control by a large-scale integrated circuit having such a circuit configuration, since one line consists of five characters, the real counter 5 is constituted by a hexadecimal counter. On the other hand, since the number of displayed lines is one, Y
The advance counter 10 becomes unnecessary. Therefore, the Y-adic counter 1o in the circuit shown in FIG. 2 is removed, and the overflow output terminal OVF of the hexadecimal counter 10 and the clear terminal CLR of the RS flip-flop 8 are directly connected.

The large-scale integrated circuit for CRT display having the configuration described above performs the following operations.

°” (1), data to be displayed on the television receiver is input from the terminal 16 to the numeric memory 6.

(2) The n-ary counter 7, the RS flip-flop 8, and the hexadecimal counter are all cleared by the vertical synchronization signal indicating the start of one screen of the television receiver;
The output from the output terminal 17 to the video circuit is disabled (dis
When the horizontal synchronization signal is input after the vertical synchronization signal disappears, the n-ary counter 7 performs a counting operation, and when the horizontal synchronization signal is input n times, it overflows. Set RS flip-flop 8.

By setting the RS flip-flop 8, a vertical display state is established.

(4) When the horizontal synchronization signal is input, the m-ary counter'
2. RS Flip Fluorozo 3. The decimal counter 4 and the hexadecimal counter 6 are all cleared and initialized with respect to the horizontal display. As a result, the display is rendered invalid. Furthermore, the oscillation of the oscillation circuit section 1 is also stopped.

(5) When the horizontal synchronizing signal disappears, the oscillation circuit section 1 starts oscillating, and a signal of a predetermined frequency is output.

(6) The output signal from the oscillation circuit section 1 is sent to the m-ary counter 2.
, and the m-ary counter 2 overflows 1. due to the arrival of m oscillation output pulses. , RS flip-flop 3 are set. When both the RS clip flops 3 and 8 are set, only the portions that are enabled in both the vertical and horizontal directions will be displayed.

FIG. 3 shows the character generator 11 when the above display is made.
Output A1 of binary counter 4 and hexadecimal counter 9
FIG.

(Complete), reads out the data addressed by the hexadecimal counter 6 and the contents of the character generator 11 addressed by the hexadecimal counter 4 and the hexadecimal counter 9, and outputs it via the output circuit 12 and the output terminal 17 to the video circuit. Output to. That is, in the initial state, the quinary counter 5 addresses the first data 1, and as shown in FIG. The counter 4 addresses the leftmost dot among the five dots in the horizontal direction. At this time, there is no character output from the character generator 11 as shown by the broken line.

(8) The hexadecimal counter 4 executes a counting operation upon receiving the oscillation output pulse from the oscillation circuit section 1, and obtains an output corresponding to the address from the character generator 11.

In the example shown in FIG. 3, there is no output in the period 0 to 3, there is character output in the period 4 to 6, and there is no output in the period 6 to 9. Note that the period 10 to 110 corresponds to the interval between adjacent characters, and there is no output to the video circuit during this period, regardless of data.

(9) When the hexadecimal counter 4 exceeds 70-, 1 is added to the quinary counter 5, and when the next data in the numerical memory 6, -12:35, is to be displayed, 2 is addressed. Thereafter, video signals are output in the same manner, and a display signal output for five characters corresponding to one scanning line is obtained. Then, when display signals for five characters are output, the hexadecimal counter 6 overflows, the character generator is disabled, and there is no -off display signal.

(1o), When the next horizontal synchronization signal is input, 1 is added to the hexadecimal counter 9, and the operations (6) to (9) described above are repeated, and 1 is added to the hexadecimal counter 9. Outputs display signals for characters. Thereafter, scanning is performed sequentially in the same manner, and the display ends when the hexadecimal counter 9 overflows.

FIG. 4 is a diagram showing the relationship between the CRT display, the scanning line, and the output of the character generator 11 explained above. As shown in FIG. 4 (,), the display (12:35) is the nth This is done in the scanning period from the (n+13th) scanning line to the (n+13th) scanning line. In addition, FIG. 4(b) shows the horizontal synchronization signal (Hsy
nc), and FIG. 4(C) shows the output signal (O2
0), Figures 4(d), (e), and (f) are the nth and n+1. This is a timing chart showing the relationship with the output signal of the character generator 1 at the time of the (n+2)th scan. During the n+1st scan, the character generator 11 outputs character signals at locations corresponding to the 4 characters 1.2.3.5, and during the n+2nd scan, character signals are output at locations corresponding to the 6 characters 12:35. be.

Thereafter, a character signal is output at the n+13th scanning interval, and 12:35 is displayed as shown in FIG. 4(,). Note that the display based on the output signals shown in FIGS. 4(b) to 4(f) assumes that a white display is made on the screen when the video circuit is at the ground level.

That is, in the circuit of FIG. 2, when the character signal output of the high level "H" shown in FIG. 4(d), (@1), and (f) is generated from the character generator 11, the output circuit 12
The video circuit can be selectively brought to the ground level by making the transistor which is a component of the circuit conductive and bringing the level of the terminal 17 to the ground level. When the level is "L", the transistor is cut off, and the video circuit is not affected at all, and the image being received is displayed. Further, while the character generator is in an invalid state, the character generator outputs an "L" level regardless of the address and operates so as not to affect the screen.

Figure 4 (q) shows the vertical synchronization signal (Vsync) and the vertical synchronization signal (Vsync).
h) is the horizontal synchronization signal (Hsync), (i) is the time relationship between the character signal output (CHAR), (1) is the horizontal synchronization signal (Hsync), (k) is the display, and (1) is the character It is a diagram showing the relationship between signal output (CHAR), and Vsync
Figure 4(b) except for the relationship between and Hsync.
Co).

A conventional large-scale integrated circuit for CRT display has the above-mentioned configuration and performs an operation of displaying the time and the like on the screen. By the way, although the display by such a conventional large-scale integrated circuit for CRT display takes time or channels, the number of displayed characters is about 10 at most.

However, as television receivers, video tape recorders, etc. have rapidly become more sophisticated, it has become necessary to display a large number of characters, far exceeding the 10 or so characters described above. -Figure 6 (a), (b
) shows an example of CRT display on program television. Figure 6) shows an example of a screen for inputting or confirming a program. The meaning of the screen is 7'ogram 1 (PROG 1) out of many programs.
) f is 10 channels (CH) on the 1st day (SUN)
ANNEL 1o) turned on at 10:46am
TIME 10:45 ), 11:3o 11cIr
-yfru (OFF TIME 11:3o). Figure 6(b) shows that if you were watching TV on Sunday, 1 minute before Program 1 started running,
An example is shown in which a notice is displayed at the corner of the TV screen at 1:44 to warn viewers that the program will start in one minute and change to channel 10.

Although the above two types of screens have been described above, in reality, as devices become more sophisticated, usage becomes more complicated, and users are likely to misuse them more frequently. Therefore, in order to prevent this, it is necessary to perform operations in a conversational manner with the user, and it is also necessary to increase the number of screens.

On the other hand, in order to make equipment cheaply, the above control should be
It is necessary to perform this with a 1-bit chip microcontroller. Considering the display example shown in FIG. 6 from this point of view, if the remaining display data shown in the figure is transmitted to the data memory in the large-scale integrated circuit for CRT display each time the screen changes, There is a great inconvenience in terms of data processing speed or the number of program steps required. The present invention was made with the intention of eliminating such inconveniences, and it is difficult to display characters on a CRT. p, VTR,
Focusing on the fact that the data that must be displayed is often fixed for certain applications such as televisions and video discs, we developed CRT.
The present invention aims to provide a large-scale integrated circuit for CRT display in which a ROM for generating certain data is built into the large-scale integrated circuit for display, and data transfer is kept to the necessary minimum.

The present invention will be explained in detail below with reference to the drawings.

FIG. 6 is a diagram showing an example of the configuration of a data memory in a conventional example. By inputting a defuter to the data input terminal 16, the display data RA is transferred from the RAM control circuit 18.
A write address, write data, and write signal to M19 are generated, and data corresponding to, for example, FIG. 5 is written to the display data RAM 19. The state of RAM at this time is
As shown in the figure. In FIG. 7, the address of the RAM is also shown 2. In FIG. 7, X indicates an X address and a yFiy address. In order to make the following explanation easier to understand, we will limit ourselves to the display example shown in FIG. 5(a) and refer to the
It is assumed that the Y-adic counter is composed of a quinary-adic counter. In Figure 7, the parts where letters such as “P” and “R” are written are as follows:
It shows that codes corresponding to each character and codes for suppressing display in other parts are written in the RAM. By the way, when the data of the x-base counter s and the Y-base counter 1o are input to the display data RAM 19 from the data input terminals 20 and 2f, R
The contents of AM are sequentially called out to the output signal line 22, and a CRT display signal is generated via the character generator 11.

However, in the conventional configuration example shown in Fig. 6, data equivalent to 16 x 6 characters, a total of 80 characters, is required to transfer the data of one 8 screens, and as mentioned above, there are problems in terms of processing speed, etc. A serious inconvenience will occur.The present invention attempts to keep data transfer to a necessary minimum by using a ROM that generates certain data in this data memory section.

FIG. 8 shows an example of the configuration of a data memory section according to the present invention. In the data memory section of FIG. 8, the display data RAM 19 and its control are the same as in the conventional case, but when a certain code is output to the output of the display data RAM 19, the ROM address control circuit 24 uses that code to By selecting the designated display data ROM 25 and further operating the display data switching circuit 23, the display data RAM 1 is switched on until a return command is issued.
9 output from signal line 22, R for display data
0 is characterized in that the output of the OM 25 is output to the character generator 11 via the output line 22. (2) to 0 indicate addresses of the display data ROM. To explain the contents of the ROM, ■ (address -1) UP, R, 9, G, -+
(Display suppression for one character) is displayed, ■ is w-1 (,2
(display suppression for 3 characters), D, A, Y, -W-, (display suppression for 3 characters) display, and the same display for ■~■,
In addition, ■ assumes that the display is suppressed for 8 characters and a return command is issued after each. RA'M 1 for display data
The contents of 9 are shown in Figure 10. In the figure, ■ to ■ indicate codes that specify the address of the display data ROM 25.
Also, small numbers such as (PROG,) are indicated by ■
The contents of the ROM specified by ~0. The above portions indicate certain display contents, so to speak, and can of course be applied to, for example, the display shown in FIG. 6(b). Other parts (encircled by broken lines in the figure) are undefined information such as time and program number.
1, and each character code is stored in these parts as shown in Figure 7.

Next, the display data RAM 19' is connected to the data input terminal 21.
Addresses are specified by the outputs of the X-base counter s and the Y-base counter 1o added from 22, and the display data is sent to the output line 22.
We will explain how to output from. First, when the Y address is specified and the X address 20 is turned on, the display data RA
Code ■ is output from M19. Since this is a ROM code, it is transmitted to the display data ROM 25 by the ROM address control circuit 24, and the first address
Code P'' of ROMX address 20 is RO for display data
It is output from M25. In addition, the display data switching circuit 23
is switched when the ROM code ■ is detected, and data "P" in the display data ROM 25 is output to the output line 22.

Next, when the hexadecimal counter 4 overflows, the signal is transmitted to the ROM address control circuit 24 via 26, and 1 is added to the ROMX address to designate the ROMX address (at this time, 1 is also added to the RAMX address).
is glassed).

Since the return signal is not output at this time, the output of the display data ROM 25, that is, "R" is output as the data output. Thereafter, the ROMX address is specified in the same way, and at this stage, the ROM data "-" (one character display suppression) is output from the data output, a return command is issued, and the display data switching circuit 23 outputs RAM data. Switch to

Next, when the hexadecimal counter overflows, the X address of the RAM continues to count during the above display data output operation, so the display data RAM1e (DX7
Dress ldRAMX7)"L/S=5, 61"
The code is output from the RAM.

Since this is a numeric code, it is output as is to the output line 22 via the display data switching circuit 23.
At X address=6 and RAMX address -7, RAM data "-", -" is output to the output line 22.

Next, in the display data RAM 16, when the X address is designated, 0 is output, and the mode changes to output ROM data. The same operation is executed thereafter, and a display similar to that shown in FIG. 7 is obtained. The number of data required to set the display data RAM 19 as shown in FIG. 1 up to 0
This corresponds to data, and the total of this data number and other data is 34 data. Therefore, by transferring 34 data, the display data RAM 19 can be set as shown in FIG.

X and Y in FIG. 10 indicate an X address and a Y address. The number of data is greatly reduced compared to 80 under the conventional method shown in FIG. Incidentally, in the case of using the circuit configuration of the present invention, the situation shown in FIG. 6 is unavoidable.

However, the display data switching circuit 23 can be composed of a simple multiplexer and a flip-flop, the ROM address control circuit 24 can be composed of a 4-pit preset counter, and the display data ROM 25 can be composed of a small-capacity ROM. Therefore, although the number of circuit elements increases, the increase in number is extremely small, and there is no risk of changing the size of the semiconductor substrate. By rewriting the ROM 25 for display data, it is possible to easily apply the present invention to other devices such as video discs.

As is clear from the above explanation, the CRT of the present invention
Large-scale display integrated circuits are capable of keeping the transfer of display data to the minimum necessary and can realize extremely efficient CRT displays.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the state of the screen and its display principle when a predetermined time is displayed, and FIG. 2 is a diagram showing the circuit configuration of a conventional large-scale integrated circuit for CRT display for displaying 5 characters.
Figure 3 shows the output of the character generator when displaying and 1
FIG. 1 shows the relationship between binary and hexadecimal counters; FIG. 4(a) to t1j, 1 shows the relationship between the CRT display, scanning lines, horizontal and vertical synchronizing signals, oscillation output, and character generator output. 5(a) and 5(b) are diagrams showing actual display examples, FIG. 6 is a configuration diagram of a data memory according to a conventional example, and FIG. 7 is a diagram showing data in a display RAM according to a conventional example. FIG. 8 is a block diagram of a data memory according to an embodiment of the present invention, FIG. 9 is a diagram showing an example of a display data ROM according to the present invention, and FIG. 10 is a diagram showing an example of data of a display RAM according to the present invention. It is. 11... Character generator, 12... External output circuit, 14... Vertical synchronization signal application terminal, 16... Horizontal synchronization signal application terminal , 16...
...Data input terminal, 17...Signal output terminal, 18...RAM control circuit, 19...
...RAM for display data, 20...Terminal to which the X-base counter output is applied, 21...Terminal to which the Y-base counter output is applied, 22......Data memory section output line , 23...display data switching circuit, 24...
...ROM address control circuit, 25...Display data ROM, 26...Terminal 0 to which hexadecimal counter overflow output is applied Name of agent: Patent attorney Toshio Nakao and 1 other person 1
Figure 2 Figure ＼ C ＼ L-11 Misaki --- Hibiki Shoichi'' Figure 5 Figure 6 Figure 7 × 8rlA 9th Ward

Claims (2)

[Claims] (1) A data memory section consisting of a rewritable memory into which display data and ROM address designation data can be input from the outside, a ROM in which predetermined data is written in advance, and a control circuit that controls these; and a circuit section that uses the data output from the data memory section as display data, and the data output of the data memory section is designated by the display data input to the rewritable memory and ROM address designation data. RO
A large-scale integrated circuit for displaying ξ arrival, characterized in that it is composed of data written in M addresses. (2) Memory control circuit with rewritable control circuit and RO
2. The large-scale integrated circuit for display according to claim 1, comprising an M address control circuit and a display data switching circuit.