JPS62126474A - Image synthesizer - Google Patents

Abstract

PURPOSE:To synthesize plural images having complex shapes and to simply move the images by providing a means for storing the address on a border line of images to be synthesized and a means for switching an image to be displayed on an address. CONSTITUTION:A CPU 5 transfers data stored in an image memory 3-1 to a V-RAM 2 based on the program stored in a ROM 4 until the data coincide with the initial address stored in a control RAM 6. From the coincidence of the initial address, data in an image memory 3-2 are transferred to the V-RAM 2 until the data coincide with the 2nd address stored in the RAM 6. After the coincidence with the 2nd address, the data in the image memory 3-1 are transferred to the V-RAM 2 until the data coincide with the 3rd address stored in the RAM 6. Consequently, at least two images having complex shapes can be synthesized and the images can be simply moved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an image compositing device for composing at least two images.

[Prior Art] In conventional image synthesis devices, once synthesis is performed, it cannot be canceled or moved. Furthermore, even if it could be moved, it was necessary to divide the compositing area into rectangles, so complex shapes could not be handled.

[Problems to be Solved by the Invention] The present invention provides an image compositing device that eliminates the drawbacks of the above-mentioned conventional example and makes it possible to compose images of complex shapes and to compose them after further movement.

[Means for Solving the Problem] As a means for solving this problem, for example, the image synthesis apparatus shown in FIG.
M) Image memory group 3 consisting of image memories equal to the number of composite images, ROM 4, CPU 5, and control RAM 6
Equipped with. The image memory group 3 sequentially includes n image memories from image memories 3-1 to 3-n.

[Function] In the configuration shown in FIG.
First, the data in the image memory 3-1 is transferred to the control RAM 6.
V-RAM until it matches the first address stored in
Transfer to 2. From the time when the addresses match, the data in the image memory 3-2 is transferred to the V-RAM 2 until it matches the second address stored in the control RAM 6. From the time when the second address matches, the data in the image memory 3-1 is again transferred to the V-RAM 2 until it matches the third address stored in the control RAM 6. Thereafter, the above operations are repeated in sequence until the end address is reached, and the contents of the V-RAM 6 are output to the CRTI.

[Example] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an image synthesis device, in which the image memory 3-1 stores the image data in FIG. 2(a), and the image memory 3-2 stores the image data in FIG. 2(b). ing. The control RAM 6 stores the address of the boundary line when the above two image data are to be combined, as shown in FIG. 2(C).

In this embodiment, one screen is 256 x 256 and the at least one screen is HEX (0000 to FFFF). First, in step S31, the image address is initialized to HEX (0000). Next, in step 332, the image data of FIG. 2(a) is sent from the image memory 3-1 to the V-RAM 2. The image address is counted up in step S33 and becomes HEX (0001).
Then, in step S34, the completion of the transfer is checked, and in step S35, it is compared with the first address HEX (IABO) of the control RAM shown in FIG. 2(e). Since both addresses are not equal, the process returns to step S32 and the data of image address HEX (0001) is sent to V-RAM2. From then on, the image data in the image memory 3-1 is V-RA until the image address becomes HEX (IABO).
Sent to M2. Image address is HEX (IABO)
, the address in the control RAM matches the address in the control RAM in step S35, so the process advances to step S36, and the 0 image address at which the image data in the image memory 3-2 (FIG. 2(b)) is sent to the V-RAM 2 is determined in step S37. It is counted up and becomes HEX (IABL), step S38.
The completion of the transfer is checked in step S39, and in step S39, the address HEX (IABI) and the control RO shown in FIG.
Since the second address HEX (IAB3) in M6 is not equal to the compared 0, the process returns to step S36, and the following steps are performed.
Steps 336-37-38-39 are repeated until the image address becomes HEX (IAB3), and the image data in the image memory 3-2 is sent to the V-RAM2.

When the image address becomes HEX (IAB3), the process advances from step S39 to step S32, and the image address becomes HEX (IAB3).
The image data in the image memory 3-1 is V again until it matches the third address HEX (IBAC) in Figure (e).
- Sent to RAM2.

The image data is then sent until the end address is reached, and the combination of image memories 3-1 and 3-2 is achieved as shown in FIG. 2(C).

Next, an example of moving and compositing images will be described according to the flowchart of the image moving program shown in FIG.

For example, the customer may specify the amount of movement of the image in the X direction.
EX (60) and V-direction niblus HEX (10) are input. First, the amount of movement is read in step S41 in FIG. 4, and the process goes from step S42 to step S43.
EX(60) is drawn and the contents of the control RAM 6 are converted from FIG. 2(e) to FIG. 2(f) at step S
45, minus HEX (60) in the X direction is the control RAM
6 is stored. In steps 547-48, the control R
The number obtained by multiplying the sign of the amount of movement in the X direction by HEX (FF) by HEX (FF) is added to the address in AM5, and the contents of control RAM 6 are as shown in Figure 2 (f).
to FIG. 2(g), in step S49, the 0 image in which the plus HEX (lO) in the X direction is stored in the control RAM 5 is synthesized according to the flowchart of the third drawing image synthesis. Image memory 3-2 to V
- When transferring image data to the RAM 2, the read address from the image memory 3-2 is HEx (60) and HEx depending on the movement amount stored in the control RAM 5.
(l ox FF) is added and becomes larete, so Fig. 2(d)
A composite image like this is obtained.

In the embodiment, the case where there are two image memories has been described, but if the number of image memories is increased, that number of images can be synthesized.

Further, the method of obtaining the image address, the method of calculating the amount of movement, etc. are not limited to those of this embodiment.If the image memory is rotated by the amount of movement when moving the 0 image, processing at the time of compositing becomes easier.

[Effects of the Invention] As described above, according to the present invention, it is possible to synthesize at least two images having a complex shape without changing the configuration of a conventional image synthesis device, and it is also possible to easily move the images. can be done.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an image synthesis device. Figure 2-(a) is image 1, Figure 2-(b) is image 2, Figure 2-(C), (d) is a composite image, Figure 2-(e), (f) , (g) shows the boundary line address in the control RAM, FIG. 3 is a flowchart of the image synthesis program, and FIG. 4 is a flowchart of the image movement program. In the figure, 1.CRT, 2-V-RAM, 3.4 medium memory group, 4.ROM, 5.CPU, 6.
...Control RAM. Patent applicant: Canon Co., Ltd., Figure 1, page 5, Izuka? Go left＼” Tabobaru 5og “Bansho° Circle Diagram 3

Claims (2)

[Claims] (1) An image compositing device for composing at least two images, including means for storing the address of the boundary line of the images to be composited, and means for switching the image to be displayed at the address. An image synthesis device characterized by moving and composing images. (2) The image synthesizing device according to claim 1, wherein the address of the boundary line changes in accordance with the movement of the image.