JPS60153169A - Varistic transistor - Google Patents

Varistic transistor

Info

Publication number
JPS60153169A
JPS60153169A JP976884A JP976884A JPS60153169A JP S60153169 A JPS60153169 A JP S60153169A JP 976884 A JP976884 A JP 976884A JP 976884 A JP976884 A JP 976884A JP S60153169 A JPS60153169 A JP S60153169A
Authority
JP
Japan
Prior art keywords
control electrode
length
transistor
ratio
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP976884A
Other languages
Japanese (ja)
Inventor
Terue Kataoka
片岡 照栄
Noburo Hashizume
橋爪 信郎
Kazutaka Tomizawa
冨澤 一隆
Yuji Awano
祐二 粟野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP976884A priority Critical patent/JPS60153169A/en
Publication of JPS60153169A publication Critical patent/JPS60153169A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8122Vertical transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To contrive the improvement in controllability and transconductance by a method wherein the shape of a control electrode is set at the ratio of its longitudinal length to the length in the direction rectangular to the longitudinal direction, i.e. its lateral length of more than 1. CONSTITUTION:The longitudinal length (a) of the control electrode 4 is increased to increase the controllability of the electrode 4, and the lateral width (b) of this electrode 4 is reduced to reduce the capacitance between electrodes. Normally, the ratio of the longitudinal length (a) of the control electrode to its lateral width (b) is more than 1 (a/b>1): the larger is the ratio (a/b), the better is the performance of the transistor. In this case, a depletion layer 5 formed around the control electrode 4 extends to lateral directions with good efficiency; therefore, resulting in the improvement in transconductance gm.

Description

【発明の詳細な説明】 本発明は、半導体中で電子があまり衝突を受けない程電
極間の距離の小さい、所謂バリスチ、りΦトランジスタ
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called varisti Φ transistor in which the distance between electrodes is so small that electrons in the semiconductor are not subject to many collisions.

第1図に示すのは従来提案されているパリスチック拳ト
ランジスタの断面図である。同図に示すように、電子が
あまり衝突を受けない程長さlの短い半導体lの両端に
電極2.3を設けた素子のは!中央に、 −制御電極 tを埋め込むが、半導体の長さlが極めて小さく、例え
ば0.2!rpm位であるために、埋め込む制御電極の
形状も、半導体の長さ方向の”大きさaを極めて小さく
シ、両端の電極2.3に平行な方向の大きさbを太きく
L、a/b<</なるものであった。これは、上記の素
子の製造に当っては、一方の電極上に半導体結晶を成長
させてゆき、その過程で金属等の制御電極tを形成する
方法が考えられていたために、必然的に、制御電極の長
さ方向の大きさaが小さくなっていたものである。
FIG. 1 is a cross-sectional view of a conventionally proposed Pallistic fist transistor. As shown in the figure, what is the element in which electrodes 2.3 are provided at both ends of a semiconductor l whose length l is so short that electrons do not receive much collision? - A control electrode t is embedded in the center, but the length l of the semiconductor is extremely small, for example 0.2! rpm, the shape of the control electrode to be embedded is also such that the size a in the longitudinal direction of the semiconductor is extremely small, and the size b in the direction parallel to the electrodes 2.3 at both ends is large, L, a/ This is because when manufacturing the above device, a semiconductor crystal is grown on one electrode, and a control electrode t made of metal or the like is formed in the process. As a result, the lengthwise dimension a of the control electrode was inevitably reduced.

この場合には、制御電極に負の電圧が加えられた場合に
形成される空乏層Sは第1図のように側面が円味を帯び
る。もし制御電極の長さaが十分大きければ空乏層5の
側面は端を除いて平らになる0また、空乏層jが横に延
びる距離も制御電極の長さaが小さければ小さい。
In this case, the side surfaces of the depletion layer S formed when a negative voltage is applied to the control electrode are rounded as shown in FIG. If the length a of the control electrode is sufficiently large, the side surfaces of the depletion layer 5 will be flat except for the edges. Furthermore, if the length a of the control electrode is small, the distance that the depletion layer j extends laterally will also be small.

一方、電流は相隣り合う制御電極弘 +lの間の半導体
で空乏層の拡がっていない部分を流れるので、制御電極
に加える電圧で電流を制御しようとする場合に効率が悪
く、トランジスタのトランスコンダクタンスgm が著
しく低くなるという欠点があった。殊に、バリスチ、り
・トランジスタにおいては従来の電極間距離の大きいト
ランジスタに比して、制御電極グの長さaが小さく、従
って空乏層Sは半導体の長さ方向の大きさが必然的に小
さく、例えばθ/ p mのオーダになるため制御電極
の制御性を悪くするという欠点があった。
On the other hand, since the current flows through the part of the semiconductor between adjacent control electrodes where the depletion layer has not expanded, it is inefficient when trying to control the current with the voltage applied to the control electrode, and the transconductance gm of the transistor The disadvantage was that the value was significantly lower. In particular, in varistor transistors, the length a of the control electrode is smaller than in conventional transistors with a large distance between electrodes, and therefore the depletion layer S is necessarily large in the longitudinal direction of the semiconductor. Since it is small, for example on the order of θ/pm, it has the disadvantage of worsening the controllability of the control electrode.

本発明は、上記の欠点を解決するためになされたもので
、制御電極の形状を制御電極の長さ方向の大きさと、長
さ方向と直角方向の長さ、すなわち横方向の長さとの比
を7より大とすることにより、性能を著しく向上させた
トランジスタを提供することを目的とする。
The present invention has been made in order to solve the above-mentioned drawbacks, and the shape of the control electrode is determined by adjusting the ratio between the length of the control electrode in the longitudinal direction and the length in the direction perpendicular to the length, that is, the length in the lateral direction. It is an object of the present invention to provide a transistor whose performance is significantly improved by setting .

詳細な計算機シミュレーションの結果では、制御1d極
の長さ方向の大きさaを大きくした方が制御性が向上し
、トランジスタのトランスコンダクタンスgm が向上
することが明らかになった。しかし、制御電極の長さ方
向の大きさaを大きくすれば、制御電極qと、半導体l
の両端の電極コ、3の間の距離が小さくなるために、そ
の間の容量が増加し特性が劣化する。
The results of detailed computer simulations revealed that increasing the length a of the control pole 1d improves controllability and improves the transconductance gm of the transistor. However, if the length a of the control electrode is increased, the control electrode q and the semiconductor l
Since the distance between the electrodes 3 at both ends of the electrode becomes smaller, the capacitance between them increases and the characteristics deteriorate.

第2図は、本発明によるパリスチ、り・トランジスタの
構成概略図である。制御電極tの制御性を増大させるた
めに、制御電極lの長さ方向の大きさaを大きくシ、電
極間の容量を減少させるために、制御型a< <Zの横
方向の大きさbを小さくしたものである。一般には、制
御電極の長さ方向の大きさaと制御雷、 f@の横方向
の大きさbとの比がlより大(!!−>/)で、その比
(−)が大きい程トランジスタの性能はよくなり る。この場合には、第2図に示すように、制御電極tの
周囲に形成される空乏層jは横方向に効率よく延びるの
で、その結果トランスコンダクタンスgm は向上する
FIG. 2 is a schematic diagram of the structure of a transistor according to the present invention. In order to increase the controllability of the control electrode t, the longitudinal size a of the control electrode l is increased, and in order to reduce the capacitance between the electrodes, the lateral size b of the control type a<<Z is increased. It is a smaller version of . Generally, the ratio of the longitudinal size a of the control electrode and the lateral size b of the control lightning, f@, is larger than l (!!->/), and the larger the ratio (-), the more Transistor performance will improve. In this case, as shown in FIG. 2, the depletion layer j formed around the control electrode t efficiently extends in the lateral direction, and as a result, the transconductance gm is improved.

以−ヒ、詳細に説明したように、従来のパリスチック・
トランジスタにおいては、制御電極の形状が制御電極の
長さ方向の大きさと横方向の大きさとの比がlより小(
τくくl)であったものを、本発明では、制御電極の長
さ方向の大きさと横方向の大きさとの比を/より大(τ
>>/)とすることによって、トランジスタのトランス
コンダクタンスgm を向上させ、高速性を発揮させ、
その性能を著しく向上することができる。
As explained in detail below, the traditional
In a transistor, the shape of the control electrode is such that the ratio of the longitudinal size to the lateral size of the control electrode is smaller than l (
In the present invention, the ratio between the longitudinal size and the lateral size of the control electrode is set to / larger than (τ
>>/), the transconductance gm of the transistor is improved and high speed performance is achieved.
Its performance can be significantly improved.

本発明は、特に超゛高途の論理素子、超高周波のミIJ
波素子として、優れた性能を示し、我が国の情報処理産
業及び通信績業に貢献するところ大なるものがある。
The present invention is particularly applicable to ultra-high-performance logic elements, ultra-high frequency micro-IJs, etc.
As a wave element, it shows excellent performance and makes a great contribution to Japan's information processing industry and telecommunications industry.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のバリスチ、り・トランジスタの構成概略
図、第2図は本発明のパリスチック・トランジスタの構
成R13図である。 ・図中、lは半導体、2は陰極、
3は陽極、lは制御電極、Sは空乏層、乙は電子の流れ
である。 ■霞 化1シ沖く部貞 轡ブ種儂婦へゴhツ1ば 晶−工 吻
第 1 図 第 2 図
FIG. 1 is a schematic diagram of the structure of a conventional balistic transistor, and FIG. 2 is a diagram illustrating the structure of a balistic transistor of the present invention.・In the figure, l is a semiconductor, 2 is a cathode,
3 is an anode, l is a control electrode, S is a depletion layer, and B is an electron flow. ■Kasumi 1st place Okukubesada 轡Bu seed maiden to Gotsu 1st part Akira-technose 1st figure 2nd figure

Claims (1)

【特許請求の範囲】[Claims] 電子の平均自由行程程度の長さ、または前記電子の平均
自由行程程度より短い長さ、を有する半導体の両端に陽
極及び陰極を設け、前記半導体中に瞭骨怜台制御電極を
埋め込んだパリ・スーチック・トランジスタにおいて、
前記制御電極゛の形状を、前記半導体の長さの方向の長
さaと曳この長さaと直角方向の長さbとの比をlkり
一大、(a/b>7)としたことを特徴とするパリスチ
ック・トランジスタ。
An anode and a cathode are provided at both ends of a semiconductor having a length approximately equal to the mean free path of electrons or a length shorter than the mean free path of said electrons, and a transparent control electrode is embedded in said semiconductor. In the Suchic transistor,
The shape of the control electrode is such that the ratio of the length a in the longitudinal direction of the semiconductor to the length a in the perpendicular direction to the length b in the perpendicular direction is greater than lk (a/b>7). A pallistic transistor characterized by:
JP976884A 1984-01-23 1984-01-23 Varistic transistor Pending JPS60153169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP976884A JPS60153169A (en) 1984-01-23 1984-01-23 Varistic transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP976884A JPS60153169A (en) 1984-01-23 1984-01-23 Varistic transistor

Publications (1)

Publication Number Publication Date
JPS60153169A true JPS60153169A (en) 1985-08-12

Family

ID=11729442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP976884A Pending JPS60153169A (en) 1984-01-23 1984-01-23 Varistic transistor

Country Status (1)

Country Link
JP (1) JPS60153169A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339882A (en) * 1976-09-24 1978-04-12 Nec Corp Production of vertical field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339882A (en) * 1976-09-24 1978-04-12 Nec Corp Production of vertical field effect transistor

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