JPH10340912A - Semiconductor device and manufacture of semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which facilitates chip layout design, enable reduction in the mounting area, and has superior electrical characteristics. SOLUTION: In this semiconductor device, finger portions 1a, 1b constituting a gate electrode (1), a source electrode 2, and a drain electrode 3 are formed substantially symmetrically with respect to the direction of cleavage of a compound semiconductor substrate, and pads 4 to 6 are formed corresponding to these electrodes. With such a structure, the electrical characteristics of the respective electrodes can be made equivalent on both sides of the direction of cleavage, and a semiconductor device having superior high-frequency characteristics can be formed. Also, since the electrodes are formed symmetrically in the direction of the cleavage, the chip layout design can be simplified, thus enabling reduction in design time and in chip size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-finger gate structure formed on a semiconductor substrate and a method of manufacturing the semiconductor, and more particularly to a case of manufacturing a high-frequency FET using a compound semiconductor as a substrate material. And

[0002]

2. Description of the Related Art When manufacturing a high-frequency FET using a compound semiconductor such as GaAs as a substrate material, a gate electrode is often comb-shaped in order to reduce a chip size and a gate resistance. Such a gate electrode is also called a multi-finger gate.

Since a compound semiconductor has a large carrier mobility depending on the crystal orientation of the substrate, when a multi-finger gate is formed on a compound semiconductor substrate, the fingers constituting the gate electrode are arranged in parallel. In many cases, a so-called parallel linear gate structure is used in which the direction of the current flowing through the finger portion is constant.

FIG. 7 is a view showing an example of such a parallel linear gate structure, in which two finger portions 1a and 1b constituting a gate electrode 1, a source electrode 2 and a drain electrode 3 are arranged in parallel. ing. The finger portions 1a and 1b are electrically connected to the pad 4, the source electrode 2 is electrically connected to the pad 5, and the drain electrode 3 is electrically connected to the pad 6.

[0005]

The chip size tends to be reduced with higher integration and lower power consumption, and when the chip size is reduced, the gate width in the chip also becomes shorter. However, the gate width has an optimum length, and desired electrical characteristics cannot be obtained if the gate width is too short or too long. Therefore, when the chip size is reduced, it is necessary to increase the gate width by, for example, processing the gate electrode 1 into a non-linear shape as shown in FIG.

However, when a multi-finger gate is formed in a small-sized chip, each of the finger portions 1a and 1b has a non-linear shape as shown in FIG.
The electric characteristics (the amount of operating current, the direction of current, etc.) of the finger portions 1a and 1b must be equalized, which complicates the layout design of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device in which a layout of a chip can be easily designed, a mounting area can be reduced, and electrical characteristics are excellent. It is in.

[0008]

According to a first aspect of the present invention, a gate electrode having a plurality of finger portions, a drain electrode, and a source electrode are formed on a compound semiconductor substrate. In the semiconductor device, the finger portion is formed symmetrically with respect to a cleavage direction of the compound semiconductor substrate.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, an angle formed between the finger portion and the cleavage direction is set to approximately 45 degrees.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, each of the finger portions has a non-linear shape.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, at least one of the drain electrode and the source electrode is formed symmetrically with respect to a cleavage direction of the compound semiconductor substrate. .

According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, an electrode formed symmetrically with respect to the cleavage direction has a non-linear shape.

According to a sixth aspect of the present invention, in the semiconductor device according to any one of the first to fifth aspects, two or more types of gate electrodes each having a plurality of finger portions are formed on the compound semiconductor substrate, Each finger portion of these gate electrodes is formed symmetrically with respect to the cleavage direction of the compound semiconductor substrate.

According to a seventh aspect of the present invention, when the angle between the orientation flat direction and the cleavage direction of the compound semiconductor substrate is approximately 45 degrees, the compound semiconductor substrate is parallel to the orientation flat direction. The semiconductor device described above is formed adjacent to the semiconductor device.

In a preferred embodiment of the present invention, when the direction of the orientation flat and the cleavage direction of the compound semiconductor substrate are parallel to each other, the compound semiconductor substrate is parallel to a direction inclined approximately 45 degrees from the direction of the orientation flat. Are formed adjacent to each other.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device and a semiconductor manufacturing method to which the present invention is applied will be specifically described with reference to the drawings.

FIG. 1 is a layout diagram of a semiconductor device according to the present invention. FIG. 1 shows an example in which a MESFET is formed using a compound semiconductor such as GaAs as a substrate material.

The dotted line AA 'in FIG. 1 indicates the cleavage direction of the compound semiconductor substrate. The gate electrode 1 and the source electrode 2 are almost symmetrical with respect to the cleavage direction of the compound semiconductor substrate.
And drain electrodes 3 are formed, and pads 4, 5, and 6 are formed corresponding to these electrodes, respectively. The gate electrode 1 and the pad 4, the source electrode 2 and the pad 5, and the drain electrode 3 and the pad 6 are electrically connected respectively.

The gate electrode 1 has a plurality of finger portions 1a,
1b, and each finger portion 1a, 1b is bent at approximately 90 degrees about the cleavage direction as an axis. Similarly, the source electrode 2 is also bent at substantially 90 degrees, and the source electrode 2 is formed separately at symmetrical positions on both sides in the cleavage direction. The gate electrode 1, the source electrode 2 and the drain electrode 3 are made of, for example, Au or Al,
5 and 6 are formed of, for example, Au.

FIG. 2 is an external view of a wafer on which the semiconductor device of FIG. 1 is formed. FIG. 2A shows an orientation flat (hereinafter, referred to as an orientation flat) 10 inclined at 45 degrees with respect to a cleavage direction. FIG. 2B shows a so-called orientation flat wafer in which the orientation flat 10 is parallel to the cleavage plane. Each of the illustrated frames corresponds to a chip formation region.

When using a 45 ° orientation flat wafer,
As shown in FIG. 2A, the semiconductor device of FIG. 1 is formed substantially parallel to the direction of the orientation flat. On the other hand, when the parallel flat wafer is used, the semiconductor device is formed in a direction inclined by 45 degrees from the direction of the flat flat as shown in FIG. 2B.

FIG. 3 is a schematic view showing a part of a reticle (mask) used in manufacturing the semiconductor device of FIG. 1, and FIG. 3 (a) is a reticle corresponding to a 45 ° orientation flat wafer. FIG. 2B shows a reticle corresponding to a wafer having parallel orientation flats. Each of the frames shown in FIGS. 3A and 3B corresponds to a chip, and a square portion in each chip corresponds to a pad.

As shown in FIGS. 3 (a) and 3 (b), the angle of the reticle pattern formed on the reticle differs between the case of using the 45 ° wafer of the orientation flat and the case of using the parallel wafer of the orientation flat. For example, when a wafer with a 45 ° orientation flat is used, a reticle pattern is formed substantially parallel to the edge of the reticle as shown in FIG. 3A, whereas when a wafer with a parallel orientation flat is used, FIG.
As shown in (b), a reticle pattern is formed in a direction inclined approximately 45 degrees from the edge direction of the reticle.

As described above, in the first embodiment, the gate electrode 1, the drain electrode 3 and the source electrode 2 are formed symmetrically in the cleavage direction on the compound semiconductor wafer, and cut into individual chips based on the cleavage direction. , Electrical characteristics of each electrode on both sides in cleavage direction (carrier mobility etc.)
Can be made equivalent, and a semiconductor device having excellent high-frequency characteristics can be formed. In addition, since the electrodes are formed symmetrically in the cleavage direction, the chip layout can be designed relatively easily, and the design time can be reduced.

[Second Embodiment] The second embodiment is characterized in that the gate electrode 1 and the source electrode 2 are formed in a non-linear shape.

FIG. 4 is a chip layout diagram of a second embodiment of the semiconductor device. The gate electrode 1, the source electrode 2 and the drain electrode 3 are in the cleavage direction (A-A '
Line), and pads 4 to 6 are formed corresponding to the respective electrodes.

Finger part 1 constituting gate electrode 1
The a, 1b, the source electrode 2 and the drain electrode 3 are all processed into a non-linear shape in order to increase the channel width. Therefore, even if the chip size is reduced,
The gate width, drain length, and source length do not become shorter.

Since the optimum gate width and drain length are different depending on the type of the compound semiconductor, it is desirable to set the shape such as the gate width according to the type of the compound semiconductor to be used.

In FIG. 4, the shapes of the gate electrode 1, the drain electrode 3 and the source electrode 2 are all formed into a non-linear shape. However, only some of the electrodes may be formed into a non-linear shape. Further, the specific shape of the gate electrode and the like is not limited to that shown in FIG.

[Third Embodiment] The third embodiment is characterized in that it has a dual gate structure.

FIG. 5 is a chip layout diagram of a third embodiment of the semiconductor device. Two gate electrodes 1 on the substrate
Are formed, and the gate electrode 1, the source electrode 2 and the drain electrode 3 are formed symmetrically with respect to the cleavage direction (the AA 'line in the drawing).

FIG. 6 is an equivalent circuit diagram of the semiconductor device shown in FIG. As shown in FIG. 6, the semiconductor device of FIG.
The drain terminal of the FET 11 and the source terminal of the FET 12 are connected, and the gate terminals each have an external input terminal separately.

As described above, according to the third embodiment, when a semiconductor device having a dual gate structure is formed, the finger portion of each gate electrode is formed to have a shape symmetrical with respect to the cleavage direction. The amount and the direction of the current can be made common, and the electrical characteristics of the semiconductor device do not vary.

Although FIG. 5 shows an example in which the finger portion has a linear shape, the finger portion may have a non-linear shape as shown in FIG.

[0035]

As described above in detail, according to the present invention, since the finger portions of the gate electrode are formed symmetrically with respect to the cleavage direction on the compound semiconductor substrate, the finger portions on both sides in the cleavage direction are formed. Electrical characteristics can be equivalent, and a semiconductor device having excellent high-frequency characteristics can be obtained. In addition, if the finger portion of the gate electrode and the drain electrode are formed symmetrically with respect to the cleavage direction of the compound semiconductor substrate, the electrical characteristics of each electrode can be made equivalent without routing the electrode pattern on the substrate. The layout design of the substrate can be performed relatively easily, and the design time can be reduced. At the same time, the chip size can be reduced, and the shape of each electrode can be made relatively non-linear.

[Brief description of the drawings]

FIG. 1 is a chip layout diagram of a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is an external view of a wafer on which the semiconductor device of FIG. 1 is formed.

FIG. 3 is a schematic view showing a part of a reticle used when manufacturing the semiconductor device of FIG. 1;

FIG. 4 is a chip layout diagram of a second embodiment of the semiconductor device according to the present invention.

FIG. 5 is a chip layout diagram of a third embodiment of the semiconductor device according to the present invention.

6 is an equivalent circuit diagram of the semiconductor device shown in FIG.

FIG. 7 is a chip layout diagram showing an example of a conventional parallel linear gate structure.

FIG. 8 is a conventional chip layout diagram having a non-linear gate electrode and the like.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate electrode 1a, 1b Finger part 2 Source electrode 3 Drain electrode 4-6 Pad 10 Orientation flat (orientation flat)

Claims (8)

[Claims] 1. A semiconductor device in which a gate electrode having a plurality of finger portions, a drain electrode, and a source electrode are formed on a compound semiconductor substrate, wherein the finger portions are symmetrical with respect to a cleavage direction of the compound semiconductor substrate. A semiconductor device characterized by being formed. 2. The semiconductor device according to claim 1, wherein an angle formed between said finger portion and said cleavage direction is set to approximately 45 degrees. 3. The semiconductor device according to claim 1, wherein each of said finger portions has a non-linear shape. 4. The semiconductor device according to claim 1, wherein at least one of said drain electrode and said source electrode is formed symmetrically with respect to a cleavage direction of said compound semiconductor substrate. 5. The semiconductor device according to claim 4, wherein an electrode formed symmetrically with respect to the cleavage direction has a non-linear shape. 6. The compound semiconductor substrate is formed with two or more types of gate electrodes each having a plurality of finger portions, and each finger portion of the gate electrode is symmetric with respect to a cleavage direction of the compound semiconductor substrate. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is formed. 7. The semiconductor according to claim 1, wherein said compound semiconductor substrate is parallel to said orientation flat direction when an angle formed by an orientation flat direction and a cleavage direction is approximately 45 degrees. A method for manufacturing a semiconductor, comprising forming devices adjacent to each other. 8. The method according to claim 1, wherein when the direction of the orientation flat and the cleavage direction of the compound semiconductor substrate are parallel to each other, the direction is parallel to a direction inclined by approximately 45 degrees from the direction of the orientation flat. A semiconductor manufacturing method characterized by forming the above semiconductor devices adjacent to each other.